wb_sdram.v

changeset 16
49f3a5bd860e
parent 15
da71a5efdf98
child 17
ac979332d5fd
     1.1 diff -r da71a5efdf98 -r 49f3a5bd860e wb_sdram.v
     1.2 --- a/wb_sdram.v	Wed Aug 11 01:15:20 2010 +0100
     1.3 +++ b/wb_sdram.v	Wed Aug 11 01:19:03 2010 +0100
     1.4 @@ -45,12 +45,18 @@
     1.5  parameter	CLOCK_RATE		= 25_000_000;
     1.6  
     1.7  // SDRAM timings in nanoseconds
     1.8 +// Precharge to refresh/row activate command (same bank) -- Trp
     1.9  parameter	TIME_Trp			= 20;
    1.10 +// RAS# to CAS# delay -- Trcd
    1.11  parameter	TIME_Trcd		= 20;
    1.12 +// Row cycle time -- Trfc, also known as Trc
    1.13  parameter	TIME_Trfc		= 70;
    1.14 +// Time between refresh cycles -- refresh interval divided by number of rows to refresh (in this case, 64e-3/4096*1e9 --> 15.625us or 15,625ns)
    1.15  parameter	TIME_Refresh	= 15_625;
    1.16 -parameter	TIME_InitDelay	= 2_000_000;	// 2ms init period
    1.17 -parameter	TIME_InitFinal	= 2_000;			// 2us before the end of the init period, raise CKE
    1.18 +// 2ms power-up init period
    1.19 +parameter	TIME_InitDelay	= 2_000_000;
    1.20 +// 2us before the end of the init period, raise CKE
    1.21 +parameter	TIME_InitFinal	= 2_000;
    1.22  
    1.23  // Calculate clock period in nanoseconds
    1.24  localparam	CLOCK_PERIOD = 1_000_000_000 / CLOCK_RATE;