wb_sdram.v

changeset 14
b541478bbb73
parent 13
07b3fd53e7a5
child 15
da71a5efdf98
     1.1 diff -r 07b3fd53e7a5 -r b541478bbb73 wb_sdram.v
     1.2 --- a/wb_sdram.v	Tue Aug 10 22:51:47 2010 +0100
     1.3 +++ b/wb_sdram.v	Tue Aug 10 23:11:10 2010 +0100
     1.4 @@ -63,6 +63,7 @@
     1.5  // Lock DEBUG pins low
     1.6  assign debug = 3'd0;
     1.7  
     1.8 +
     1.9  /****
    1.10   * SDRAM data output buffer
    1.11   ****/
    1.12 @@ -73,7 +74,6 @@
    1.13  assign sdram_dq = sdram_dq_oe ? sdram_dq_r : 32'hZZZZ;
    1.14  
    1.15  
    1.16 -
    1.17  /****
    1.18   * State timer
    1.19   * This is used to ensure that the state machine abides by RAM timing