wb_sdram.v

changeset 15
da71a5efdf98
parent 14
b541478bbb73
child 16
49f3a5bd860e
     1.1 diff -r b541478bbb73 -r da71a5efdf98 wb_sdram.v
     1.2 --- a/wb_sdram.v	Tue Aug 10 23:11:10 2010 +0100
     1.3 +++ b/wb_sdram.v	Wed Aug 11 01:15:20 2010 +0100
     1.4 @@ -41,16 +41,33 @@
     1.5   ****/
     1.6  // CAS latency -- either 2 or 3   [2010-08-10: tested with CL=3, worked fine]
     1.7  parameter	CAS_LATENCY		= 3'd2;
     1.8 +// System clock frequency
     1.9 +parameter	CLOCK_RATE		= 25_000_000;
    1.10 +
    1.11 +// SDRAM timings in nanoseconds
    1.12 +parameter	TIME_Trp			= 20;
    1.13 +parameter	TIME_Trcd		= 20;
    1.14 +parameter	TIME_Trfc		= 70;
    1.15 +parameter	TIME_Refresh	= 15_625;
    1.16 +parameter	TIME_InitDelay	= 2_000_000;	// 2ms init period
    1.17 +parameter	TIME_InitFinal	= 2_000;			// 2us before the end of the init period, raise CKE
    1.18 +
    1.19 +// Calculate clock period in nanoseconds
    1.20 +localparam	CLOCK_PERIOD = 1_000_000_000 / CLOCK_RATE;
    1.21 +
    1.22  // T_rp  ==> 20ns
    1.23 -parameter	TIME_Trp			= 32'd1;
    1.24 +localparam	TCY_Trp			= (TIME_Trp+CLOCK_PERIOD-1) / CLOCK_PERIOD - 1;
    1.25  // T_rcd ==> 20ns
    1.26 -parameter	TIME_Trcd		= 32'd1;
    1.27 +localparam	TCY_Trcd			= (TIME_Trcd+CLOCK_PERIOD-1) / CLOCK_PERIOD - 1;
    1.28  // T_rfc (a.k.a. T_rc) ==> 70ns
    1.29 -parameter	TIME_Trfc		= 32'd2;
    1.30 +localparam	TCY_Trfc			= (TIME_Trfc+CLOCK_PERIOD-1) / CLOCK_PERIOD - 1;
    1.31  // T_mrd ==> 2 clock cycles
    1.32 -parameter	TIME_Tmrd		= 32'd2;
    1.33 +localparam	TCY_Tmrd			= 32'd2;
    1.34  // Maximum allowed time between two refresh cycles
    1.35 -parameter	TIME_REFRESH	= 32'd390;
    1.36 +localparam	TCY_Refresh		= (TIME_Refresh+CLOCK_PERIOD-1) / CLOCK_PERIOD - 1;
    1.37 +
    1.38 +localparam	TCY_InitDelay	= (TIME_InitDelay+CLOCK_PERIOD-1) / CLOCK_PERIOD - 1;
    1.39 +localparam	TCY_InitFinal	= (TIME_InitFinal+CLOCK_PERIOD-1) / CLOCK_PERIOD - 1;
    1.40  
    1.41  
    1.42  /****
    1.43 @@ -119,14 +136,14 @@
    1.44  	if (wb_rst_i | !refresh_timer_en) begin
    1.45  		// Reset; clear timer, unset REFRESH REQUEST
    1.46  		refresh_req <= 1'b0;
    1.47 -		refresh_timer <= TIME_REFRESH - 32'd1;
    1.48 +		refresh_timer <= TCY_Refresh - 32'd1;
    1.49  	end else if (refresh_ack) begin
    1.50  		// Refresh Ack, clear Refresh Request.
    1.51  		refresh_req <= 1'b0;
    1.52  	end else if (refresh_timer == 0) begin
    1.53  		// Refresh timer timed out, make a Refresh Request and reload the timer
    1.54  		refresh_req <= 1'b1;
    1.55 -		refresh_timer <= TIME_REFRESH - 32'd1;
    1.56 +		refresh_timer <= TCY_Refresh - 32'd1;
    1.57  	end else begin
    1.58  		// Otherwise just decrement the timer
    1.59  		refresh_timer <= refresh_timer - 32'd1;
    1.60 @@ -203,7 +220,7 @@
    1.61  			ST_INIT1: begin
    1.62  					// INIT1: Set up for initial power-up wait
    1.63  					state <= ST_INIT2;
    1.64 -					timer <= 32'd50_000;		// TODO: dependent on core clock rate. Needs to be >= 100us
    1.65 +					timer <= TCY_InitDelay;		// Needs to be >= 100us
    1.66  					
    1.67  					// SDRAM state
    1.68  					sdram_cke	<= 1'b0;			// clock disabled
    1.69 @@ -221,7 +238,7 @@
    1.70  					if (timer == 32'd0) begin
    1.71  						// Timer hit zero. Send a NOP.
    1.72  						state <= ST_NOP1;
    1.73 -					end else if (timer < 32'd50) begin
    1.74 +					end else if (timer < TCY_InitFinal) begin
    1.75  						// Timer value is more than zero but less than 50; CKE is on, but
    1.76  						// keep waiting for the timer to actually expire.
    1.77  						sdram_cke	<= 1'b1;
    1.78 @@ -239,7 +256,7 @@
    1.79  			ST_PrechargeAll: begin
    1.80  					// Precharge All, then wait T_rp (20ns)
    1.81  					sdram_mode <= M_PrechargeAll;
    1.82 -					timer <= TIME_Trp - 32'd1;
    1.83 +					timer <= TCY_Trp - 32'd1;
    1.84  					state <= ST_PrechargeAll_Wait;
    1.85  				end
    1.86  
    1.87 @@ -255,7 +272,7 @@
    1.88  			ST_AutoRefresh1: begin
    1.89  					// Auto Refresh 1 of 2, wait T_rfc (70ns) after each
    1.90  					sdram_mode <= M_AutoRefresh;
    1.91 -					timer <= TIME_Trfc - 32'd1;
    1.92 +					timer <= TCY_Trfc - 32'd1;
    1.93  					state <= ST_AutoRefresh1_Wait;
    1.94  				end
    1.95  				
    1.96 @@ -271,7 +288,7 @@
    1.97  			ST_AutoRefresh2: begin
    1.98  					// Auto Refresh 2 of 2, wait T_rfc (70ns) after each
    1.99  					sdram_mode <= M_AutoRefresh;
   1.100 -					timer <= TIME_Trfc - 32'd1;
   1.101 +					timer <= TCY_Trfc - 32'd1;
   1.102  					state <= ST_AutoRefresh2_Wait;
   1.103  				end
   1.104  				
   1.105 @@ -301,7 +318,7 @@
   1.106  					sdram_mode <= M_LoadModeRegister;
   1.107  
   1.108  					// Wait T_mrd (2 clock cycles)
   1.109 -					timer <= TIME_Tmrd - 32'd1;
   1.110 +					timer <= TCY_Tmrd - 32'd1;
   1.111  					state <= ST_LoadModeRegister_Wait;
   1.112  				end
   1.113  
   1.114 @@ -347,7 +364,7 @@
   1.115  					// Tell the SDRAM to do a Refresh
   1.116  					sdram_mode <= M_AutoRefresh;
   1.117  					// Wait for T_rfc
   1.118 -					timer <= TIME_Trfc;
   1.119 +					timer <= TCY_Trfc;
   1.120  					state <= ST_Refresh_Wait;
   1.121  				end
   1.122  				
   1.123 @@ -368,7 +385,7 @@
   1.124  					sdram_mode <= M_BankActivate;
   1.125  					sdram_addr <= row_addr;
   1.126  					sdram_ba   <= bank_addr;
   1.127 -					timer <= TIME_Trcd - 32'd1;
   1.128 +					timer <= TCY_Trcd - 32'd1;
   1.129  					state <= ST_Activate_Wait;
   1.130  				end
   1.131  				
   1.132 @@ -395,7 +412,7 @@
   1.133  					sdram_dqm	<= ~wb_sel_i;
   1.134  					
   1.135  					// Wait T_rp (20ns)
   1.136 -					timer <= TIME_Trp - 32'd1;
   1.137 +					timer <= TCY_Trp - 32'd1;
   1.138  					state <= ST_Wait_Trp;
   1.139  				end
   1.140  
   1.141 @@ -417,7 +434,7 @@
   1.142  						// Latch data
   1.143  						wb_dat_o <= sdram_dq;
   1.144  						// Wait T_rp (20ns)
   1.145 -						timer <= TIME_Trp - 32'd1;
   1.146 +						timer <= TCY_Trp - 32'd1;
   1.147  						state <=	ST_Wait_Trp;
   1.148  					end
   1.149  				end