IPCores/wb_sdram / file diff

     1.1 diff -r 2e7c2bcdac0e -r efeebc7c7498 wb_sdram.v
     1.2 --- a/wb_sdram.v	Tue Aug 10 22:11:51 2010 +0100
     1.3 +++ b/wb_sdram.v	Tue Aug 10 22:14:22 2010 +0100
     1.4 @@ -1,4 +1,4 @@
     1.5 -/****************************************************************************
     1.6 +	/****************************************************************************
     1.7   *
     1.8   *
     1.9   ****************************************************************************/
    1.10 @@ -58,7 +58,8 @@
    1.11  assign wb_err_o = 1'b0;
    1.12  // Can't request retries
    1.13  assign wb_rty_o = 1'b0;
    1.14 -
    1.15 +// Lock DEBUG pins low
    1.16 +assign debug = 3'd0;
    1.17  
    1.18  /****
    1.19   * SDRAM data output buffer
    1.20 @@ -131,8 +132,6 @@
    1.21  	end
    1.22  end
    1.23  
    1.24 -assign debug = { 1'b0, refresh_req, refresh_ack };
    1.25 -
    1.26  
    1.27  /****
    1.28   * Address decoder
    1.29 @@ -178,7 +177,6 @@
    1.30  	if (wb_rst_i) begin
    1.31  		// Initialise state machine and timer
    1.32  		state <= ST_INIT1;
    1.33 -//		debug <= 3'd0;
    1.34  		timer <= 32'd0;
    1.35  		
    1.36  		// Clear REFRESH ACK flag and disable refresh timer
    1.37 @@ -227,7 +225,6 @@
    1.38  						// keep waiting for the timer to actually expire.
    1.39  						sdram_cke	<= 1'b1;
    1.40  						state			<= ST_INIT2;
    1.41 -//						debug <= 3'd1;
    1.42  					end
    1.43  					sdram_mode <= M_Inhibit;
    1.44  				end