Wed, 18 Aug 2010 14:14:38 +0100
move all user parameters into top of module
| wb_sdram.v | file | annotate | diff | revisions |
1.1 diff -r ac979332d5fd -r 275105a6a36b wb_sdram.v 1.2 --- a/wb_sdram.v Wed Aug 18 14:10:48 2010 +0100 1.3 +++ b/wb_sdram.v Wed Aug 18 14:14:38 2010 +0100 1.4 @@ -4,10 +4,29 @@ 1.5 ****************************************************************************/ 1.6 1.7 module wb_sdram #( 1.8 + // Data and address bus parameters 1.9 parameter DATA_BITS = 32, // Width of SDRAM data bus 1.10 parameter COLADDR_BITS = 9, // Number of SDRAM Column Address bits 1.11 parameter BANKADDR_BITS = 2, // Number of SDRAM Bank Address bits 1.12 - parameter ROWADDR_BITS = 12 // Number of SDRAM Row Address bits 1.13 + parameter ROWADDR_BITS = 12, // Number of SDRAM Row Address bits 1.14 + 1.15 + // Timer parameters 1.16 + parameter CAS_LATENCY = 3'd2, // CAS latency -- either 2 or 3 1.17 + parameter CLOCK_RATE = 25_000_000, // System clock frequency in Hz 1.18 + 1.19 + // SDRAM timings in nanoseconds 1.20 + // Precharge to refresh/row activate command (same bank) -- Trp 1.21 + parameter TIME_Trp = 20, 1.22 + // RAS# to CAS# delay -- Trcd 1.23 + parameter TIME_Trcd = 20, 1.24 + // Row cycle time -- Trfc, also known as Trc 1.25 + parameter TIME_Trfc = 70, 1.26 + // Time between refresh cycles -- refresh interval divided by number of rows to refresh (in this case, 64e-3/4096*1e9 --> 15.625us or 15,625ns) 1.27 + parameter TIME_Refresh = 15_625, 1.28 + // 2ms power-up init period (2e6 nanoseconds = 2ms) 1.29 + parameter TIME_InitDelay = 2_000_000, 1.30 + // 2us before the end of the init period, raise CKE (2000ns = 2us) 1.31 + parameter TIME_InitFinal = 2_000 1.32 ) ( 1.33 // Clocks and resets 1.34 input wb_clk_i, // WISHBONE clock 1.35 @@ -37,29 +56,9 @@ 1.36 inout [DATA_BITS-1:0] sdram_dq // SDRAM data bus 1.37 ); 1.38 1.39 - 1.40 /**** 1.41 - * Timer values 1.42 + * Timer values -- don't touch! 1.43 ****/ 1.44 -// CAS latency -- either 2 or 3 [2010-08-10: tested with CL=3, worked fine] 1.45 -parameter CAS_LATENCY = 3'd2; 1.46 -// System clock frequency 1.47 -parameter CLOCK_RATE = 25_000_000; 1.48 - 1.49 -// SDRAM timings in nanoseconds 1.50 -// Precharge to refresh/row activate command (same bank) -- Trp 1.51 -parameter TIME_Trp = 20; 1.52 -// RAS# to CAS# delay -- Trcd 1.53 -parameter TIME_Trcd = 20; 1.54 -// Row cycle time -- Trfc, also known as Trc 1.55 -parameter TIME_Trfc = 70; 1.56 -// Time between refresh cycles -- refresh interval divided by number of rows to refresh (in this case, 64e-3/4096*1e9 --> 15.625us or 15,625ns) 1.57 -parameter TIME_Refresh = 15_625; 1.58 -// 2ms power-up init period 1.59 -parameter TIME_InitDelay = 2_000_000; 1.60 -// 2us before the end of the init period, raise CKE 1.61 -parameter TIME_InitFinal = 2_000; 1.62 - 1.63 // Calculate clock period in nanoseconds 1.64 localparam CLOCK_PERIOD = 1_000_000_000 / CLOCK_RATE; 1.65