Tue, 10 Aug 2010 22:11:51 +0100
[wb_sdram] parameterise timing and CAS latency
| wb_sdram.v | file | annotate | diff | revisions |
1.1 diff -r 413ec22a27cd -r 2e7c2bcdac0e wb_sdram.v 1.2 --- a/wb_sdram.v Tue Aug 10 19:23:01 2010 +0100 1.3 +++ b/wb_sdram.v Tue Aug 10 22:11:51 2010 +0100 1.4 @@ -37,6 +37,21 @@ 1.5 1.6 1.7 /**** 1.8 + * Timer values 1.9 + ****/ 1.10 +// CAS latency -- either 2 or 3 1.11 +parameter CAS_LATENCY = 3'd2; 1.12 +// T_rp ==> 20ns 1.13 +parameter TIME_Trp = 32'd1; 1.14 +// T_rcd ==> 20ns 1.15 +parameter TIME_Trcd = 32'd1; 1.16 +// T_rfc (a.k.a. T_rc) ==> 70ns 1.17 +parameter TIME_Trfc = 32'd2; 1.18 +// T_mrd ==> 2 clock cycles 1.19 +parameter TIME_Tmrd = 32'd2; 1.20 + 1.21 + 1.22 +/**** 1.23 * WISHBONE status pins 1.24 ****/ 1.25 // Can't raise bus errors 1.26 @@ -226,7 +241,7 @@ 1.27 ST_PrechargeAll: begin 1.28 // Precharge All, then wait T_rp (20ns) 1.29 sdram_mode <= M_PrechargeAll; 1.30 - timer <= 32'd0; // wait 1tcy (40ns) ---> TIMER HERE 1.31 + timer <= TIME_Trp - 32'd1; 1.32 state <= ST_PrechargeAll_Wait; 1.33 end 1.34 1.35 @@ -242,7 +257,7 @@ 1.36 ST_AutoRefresh1: begin 1.37 // Auto Refresh 1 of 2, wait T_rfc (70ns) after each 1.38 sdram_mode <= M_AutoRefresh; 1.39 - timer <= 32'd1; // wait 2tcy (80ns) ---> TIMER HERE 1.40 + timer <= TIME_Trfc - 32'd1; 1.41 state <= ST_AutoRefresh1_Wait; 1.42 end 1.43 1.44 @@ -258,7 +273,7 @@ 1.45 ST_AutoRefresh2: begin 1.46 // Auto Refresh 2 of 2, wait T_rfc (70ns) after each 1.47 sdram_mode <= M_AutoRefresh; 1.48 - timer <= 32'd1; // wait 2tcy (80ns) ---> TIMER HERE 1.49 + timer <= TIME_Trfc - 32'd1; 1.50 state <= ST_AutoRefresh2_Wait; 1.51 end 1.52 1.53 @@ -279,16 +294,16 @@ 1.54 * - A11,10 = 00 [RFU] 1.55 * - A9 = 0 [WBL -- write burst length same as read burst length] 1.56 * - A8,7 = 00 [Test Mode off] 1.57 - * - A6..4 = 010 [CAS Latency = 2 clocks] 1.58 + * - A6..4 = 010 [CAS Latency = 2 or 3 clocks, set above] 1.59 * - A3 = 0 [Burst type = sequential] 1.60 * - A2..0 = 000 [Burst length = 1 word] 1.61 */ 1.62 sdram_ba <= 2'b00; 1.63 - sdram_addr <= 12'b00_0_00_010_000; 1.64 + sdram_addr <= {5'b00_0_00, CAS_LATENCY[2:0], 3'b000}; 1.65 sdram_mode <= M_LoadModeRegister; 1.66 1.67 // Wait T_mrd (2 clock cycles) 1.68 - timer <= 32'd1; // (2cy)-1 ---> TIMER HERE 1.69 + timer <= TIME_Tmrd - 32'd1; 1.70 state <= ST_LoadModeRegister_Wait; 1.71 end 1.72 1.73 @@ -334,7 +349,7 @@ 1.74 // Tell the SDRAM to do a Refresh 1.75 sdram_mode <= M_AutoRefresh; 1.76 // Wait for T_rfc 1.77 - timer <= 32'd1; // wait Trfc (70ns ideally, we give 80ns) ---> TIMER HERE 1.78 + timer <= TIME_Trfc; 1.79 state <= ST_Refresh_Wait; 1.80 end 1.81 1.82 @@ -355,7 +370,7 @@ 1.83 sdram_mode <= M_BankActivate; 1.84 sdram_addr <= row_addr; 1.85 sdram_ba <= bank_addr; 1.86 - timer <= 32'd0; // Wait T_rcd (20ns ideally, here 40ns) ---> TIMER HERE 1.87 + timer <= TIME_Trcd - 32'd1; 1.88 state <= ST_Activate_Wait; 1.89 end 1.90 1.91 @@ -382,7 +397,7 @@ 1.92 sdram_dqm <= ~wb_sel_i; 1.93 1.94 // Wait T_rp (20ns) 1.95 - timer <= 32'd0; // wait 1tcy (40ns) ---> TIMER HERE 1.96 + timer <= TIME_Trp - 32'd1; 1.97 state <= ST_Wait_Trp; 1.98 end 1.99 1.100 @@ -392,7 +407,7 @@ 1.101 sdram_addr <= column_addr; 1.102 sdram_dq_oe <= 1'b0; // SDRAM drives the DQ bus 1.103 sdram_dqm <= 4'b0000; // Grab all the data (it's just easier that way...) 1.104 - timer <= 32'd2 - 32'd1; // CAS# Latency ---> TIMER HERE 1.105 + timer <= CAS_LATENCY - 32'd1; // CAS# Latency 1.106 state <= ST_Read_Wait; 1.107 end 1.108 1.109 @@ -404,7 +419,7 @@ 1.110 // Latch data 1.111 wb_dat_o <= sdram_dq; 1.112 // Wait T_rp (20ns) 1.113 - timer <= 32'd0; // wait 1tcy (40ns) ---> TIMER HERE 1.114 + timer <= TIME_Trp - 32'd1; 1.115 state <= ST_Wait_Trp; 1.116 end 1.117 end