make test work like a R/W checkerboard instead (looks better on the LA)

Tue, 10 Aug 2010 18:04:05 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Tue, 10 Aug 2010 18:04:05 +0100
changeset 6
39984d9ff640
parent 5
dd6f40c05963
child 7
001f5282bff0

make test work like a R/W checkerboard instead (looks better on the LA)

wb_sdram.v file | annotate | diff | revisions
     1.1 diff -r dd6f40c05963 -r 39984d9ff640 wb_sdram.v
     1.2 --- a/wb_sdram.v	Tue Aug 10 17:42:18 2010 +0100
     1.3 +++ b/wb_sdram.v	Tue Aug 10 18:04:05 2010 +0100
     1.4 @@ -150,6 +150,7 @@
     1.5  localparam	ST_Test_Precharge_All_Wait	= 32'd507;
     1.6   
     1.7  reg [31:0] state;
     1.8 +reg [31:0] captured_data;
     1.9  always @(posedge wb_clk_i) begin
    1.10  	if (wb_rst_i) begin
    1.11  		// Initialise state machine and timer
    1.12 @@ -362,7 +363,7 @@
    1.13  					sdram_dqm <= 4'b1111;		// Disable SDRAM output buffers
    1.14  					if (timer == 32'd0) begin
    1.15  						state <= ST_Test_Read_Finish;
    1.16 -						// TODO: capture data locally
    1.17 +						captured_data <= sdram_dq;
    1.18  					end
    1.19  				end
    1.20  
    1.21 @@ -377,7 +378,7 @@
    1.22  					// Write to SDRAM
    1.23  					sdram_mode <= M_Write;
    1.24  					sdram_addr <= column_addr;
    1.25 -					sdram_dq_r <= 32'h55AA_BCDE;
    1.26 +					sdram_dq_r <= ~captured_data; //32'h55AA_BCDE;
    1.27  					sdram_dq_oe <= 1'b1;		// output enable
    1.28  					sdram_dqm <= 4'b0000;		// Allow data through (DQM = OE# = 1 to mask off, 0 to allow)
    1.29  					state <= ST_Test_Precharge_All;