Wed, 18 Aug 2010 14:10:48 +0100
parameterise data and addr. buses, tidy up
Parameterised the width of the data and address buses, and the number of
COLUMN, ROW and BANK address bits.
Tidied up code to (hopefully!) work when bus widths are changed.
| wb_sdram.v | file | annotate | diff | revisions |
1.1 diff -r 49f3a5bd860e -r ac979332d5fd wb_sdram.v 1.2 --- a/wb_sdram.v Wed Aug 11 01:19:03 2010 +0100 1.3 +++ b/wb_sdram.v Wed Aug 18 14:10:48 2010 +0100 1.4 @@ -1,38 +1,40 @@ 1.5 - /**************************************************************************** 1.6 +/**************************************************************************** 1.7 * 1.8 * 1.9 ****************************************************************************/ 1.10 1.11 -module wb_sdram ( 1.12 +module wb_sdram #( 1.13 + parameter DATA_BITS = 32, // Width of SDRAM data bus 1.14 + parameter COLADDR_BITS = 9, // Number of SDRAM Column Address bits 1.15 + parameter BANKADDR_BITS = 2, // Number of SDRAM Bank Address bits 1.16 + parameter ROWADDR_BITS = 12 // Number of SDRAM Row Address bits 1.17 +) ( 1.18 // Clocks and resets 1.19 - input wb_clk_i, // WISHBONE clock 1.20 - input wb_rst_i, // WISHBONE reset 1.21 + input wb_clk_i, // WISHBONE clock 1.22 + input wb_rst_i, // WISHBONE reset 1.23 1.24 // WISHBONE bus 1.25 - input [31:0] wb_adr_i, // WISHBONE address 1.26 - input [31:0] wb_dat_i, // WISHBONE data in 1.27 - output reg [31:0] wb_dat_o, // WISHBONE data out 1.28 - input [3:0] wb_sel_i, // WISHBONE byte select 1.29 - input wb_we_i, // WISHBONE write enable (R/#W) 1.30 - input wb_cyc_i, // WISHBONE cycle 1.31 - input wb_stb_i, // WISHBONE strobe 1.32 - output reg wb_ack_o, // WISHBONE cycle acknowledge (data available, DTACK) 1.33 - output wb_err_o, // WISHBONE bus error 1.34 - output wb_rty_o, // WISHBONE retry-later 1.35 + input [31:0] wb_adr_i, // WISHBONE address 1.36 + input [DATA_BITS-1:0] wb_dat_i, // WISHBONE data in 1.37 + output reg [DATA_BITS-1:0] wb_dat_o, // WISHBONE data out 1.38 + input [(DATA_BITS/4)-1:0] wb_sel_i, // WISHBONE byte select 1.39 + input wb_we_i, // WISHBONE write enable (R/#W) 1.40 + input wb_cyc_i, // WISHBONE cycle 1.41 + input wb_stb_i, // WISHBONE strobe 1.42 + output reg wb_ack_o, // WISHBONE cycle acknowledge (data available, DTACK) 1.43 + output wb_err_o, // WISHBONE bus error 1.44 + output wb_rty_o, // WISHBONE retry-later 1.45 1.46 // SDRAM 1.47 - output reg sdram_cke, // SDRAM clock enable 1.48 - output sdram_cs_n, // SDRAM chip select (active low) 1.49 - output sdram_ras_n, // SDRAM row address strobe (active low) 1.50 - output sdram_cas_n, // SDRAM column address strobe (active low) 1.51 - output sdram_we_n, // SDRAM write enable (active low) 1.52 - output [11:0] sdram_a, // SDRAM address 1.53 - output reg [1:0] sdram_ba, // SDRAM bank address 1.54 - output reg [3:0] sdram_dqm, // SDRAM data mask (OE#; 0=active, 1=disabled) 1.55 - inout [31:0] sdram_dq, // SDRAM data bus 1.56 - 1.57 - // Debugging 1.58 - output /*reg*/ [2:0] debug // debug bits 1.59 + output reg sdram_cke, // SDRAM clock enable 1.60 + output sdram_cs_n, // SDRAM chip select (active low) 1.61 + output sdram_ras_n, // SDRAM row address strobe (active low) 1.62 + output sdram_cas_n, // SDRAM column address strobe (active low) 1.63 + output sdram_we_n, // SDRAM write enable (active low) 1.64 + output [ROWADDR_BITS-1:0] sdram_a, // SDRAM address 1.65 + output reg [BANKADDR_BITS-1:0] sdram_ba, // SDRAM bank address 1.66 + output reg [(DATA_BITS/4)-1:0] sdram_dqm, // SDRAM data mask (OE#; 0=active, 1=disabled) 1.67 + inout [DATA_BITS-1:0] sdram_dq // SDRAM data bus 1.68 ); 1.69 1.70 1.71 @@ -83,8 +85,6 @@ 1.72 assign wb_err_o = 1'b0; 1.73 // Can't request retries 1.74 assign wb_rty_o = 1'b0; 1.75 -// Lock DEBUG pins low 1.76 -assign debug = 3'd0; 1.77 1.78 1.79 /**** 1.80 @@ -93,8 +93,8 @@ 1.81 // OE=1 for output mode, 0 for input 1.82 reg sdram_dq_oe; 1.83 // SDRAM output register 1.84 -reg [31:0] sdram_dq_r; 1.85 -assign sdram_dq = sdram_dq_oe ? sdram_dq_r : 32'hZZZZ; 1.86 +reg [DATA_BITS-1:0] sdram_dq_r; 1.87 +assign sdram_dq = sdram_dq_oe ? sdram_dq_r : {DATA_BITS{1'bZ}}; 1.88 1.89 1.90 /**** 1.91 @@ -160,14 +160,14 @@ 1.92 /**** 1.93 * Address decoder 1.94 ****/ 1.95 -wire [8:0] column_addr; 1.96 -wire [11:0] row_addr; 1.97 -wire [1:0] bank_addr; 1.98 +wire [COLADDR_BITS-1:0] column_addr; 1.99 +wire [ROWADDR_BITS-1:0] row_addr; 1.100 +wire [BANKADDR_BITS-1:0] bank_addr; 1.101 1.102 // Convert a 23-bit linear address into an SDRAM address 1.103 -assign column_addr = wb_adr_i[8:0]; 1.104 -assign bank_addr = wb_adr_i[10:9]; 1.105 -assign row_addr = wb_adr_i[22:11]; 1.106 +assign column_addr = wb_adr_i[COLADDR_BITS-1:0]; 1.107 +assign bank_addr = wb_adr_i[COLADDR_BITS+BANKADDR_BITS-1:COLADDR_BITS]; 1.108 +assign row_addr = wb_adr_i[COLADDR_BITS+BANKADDR_BITS+ROWADDR_BITS-1:COLADDR_BITS+BANKADDR_BITS]; 1.109 1.110 1.111 /**** 1.112 @@ -210,11 +210,11 @@ 1.113 // Initialisation state for SDRAM 1.114 sdram_cke <= 1'b0; 1.115 sdram_mode <= M_Inhibit; 1.116 - sdram_addr <= 12'h000; 1.117 - sdram_ba <= 2'b00; 1.118 - sdram_dqm <= 4'b0000; 1.119 - sdram_dq_oe <= 1'b0; // data output disabled 1.120 - sdram_dq_r <= 32'd0; 1.121 + sdram_addr <= 0; 1.122 + sdram_ba <= 0; 1.123 + sdram_dqm <= 0; 1.124 + sdram_dq_oe <= 0; // data output disabled 1.125 + sdram_dq_r <= 0; 1.126 end else begin 1.127 // timer logic 1.128 if (timer > 32'd0) begin 1.129 @@ -231,11 +231,11 @@ 1.130 // SDRAM state 1.131 sdram_cke <= 1'b0; // clock disabled 1.132 sdram_mode <= M_Inhibit; 1.133 - sdram_addr <= 12'h000; 1.134 - sdram_ba <= 2'b00; 1.135 - sdram_dqm <= 4'b1111; 1.136 - sdram_dq_oe <= 1'b0; // data output disabled 1.137 - sdram_dq_r <= 32'd0; 1.138 + sdram_addr <= 0; 1.139 + sdram_ba <= 0; 1.140 + sdram_dqm <= {(DATA_BITS/4){1'b1}}; 1.141 + sdram_dq_oe <= 0; // data output disabled 1.142 + sdram_dq_r <= 0; 1.143 end 1.144 1.145 ST_INIT2: begin 1.146 @@ -319,7 +319,7 @@ 1.147 * - A3 = 0 [Burst type = sequential] 1.148 * - A2..0 = 000 [Burst length = 1 word] 1.149 */ 1.150 - sdram_ba <= 2'b00; 1.151 + sdram_ba <= 0; 1.152 sdram_addr <= {5'b00_0_00, CAS_LATENCY[2:0], 3'b000}; 1.153 sdram_mode <= M_LoadModeRegister; 1.154 1.155 @@ -331,8 +331,8 @@ 1.156 ST_LoadModeRegister_Wait: begin 1.157 // Wait for LMR to complete 1.158 sdram_mode <= M_Nop; 1.159 - sdram_ba <= 2'd0; 1.160 - sdram_addr <= 12'd0; 1.161 + sdram_ba <= 0; 1.162 + sdram_addr <= 0; 1.163 if (timer == 32'd0) begin 1.164 // Timer hit zero. Continue 1.165 state <= ST_Spin; 1.166 @@ -413,8 +413,8 @@ 1.167 // Write cycle handler 1.168 sdram_mode <= M_WritePrecharge; 1.169 sdram_addr <= column_addr; 1.170 - sdram_dq_r <= wb_dat_i; 1.171 - sdram_dq_oe <= 1'b1; // FPGA drives the DQ bus 1.172 + sdram_dq_r <= 0; 1.173 + sdram_dq_oe <= 1; // FPGA drives the DQ bus 1.174 sdram_dqm <= ~wb_sel_i; 1.175 1.176 // Wait T_rp (20ns) 1.177 @@ -426,8 +426,8 @@ 1.178 // Read cycle handler 1.179 sdram_mode <= M_ReadPrecharge; 1.180 sdram_addr <= column_addr; 1.181 - sdram_dq_oe <= 1'b0; // SDRAM drives the DQ bus 1.182 - sdram_dqm <= 4'b0000; // Grab all the data (it's just easier that way...) 1.183 + sdram_dq_oe <= 0; // SDRAM drives the DQ bus 1.184 + sdram_dqm <= 0; // Grab all the data (easier than playing with WB_SEL...) 1.185 timer <= CAS_LATENCY - 32'd1; // CAS# Latency 1.186 state <= ST_Read_Wait; 1.187 end 1.188 @@ -435,7 +435,7 @@ 1.189 ST_Read_Wait: begin 1.190 // Wait for CAS# latency 1.191 sdram_mode <= M_Nop; 1.192 - sdram_dqm <= 4'b1111; // Make SDRAM DQ bus float 1.193 + sdram_dqm <= {(DATA_BITS/4){1'b1}}; // Make SDRAM DQ bus float 1.194 if (timer == 32'd0) begin 1.195 // Latch data 1.196 wb_dat_o <= sdram_dq; 1.197 @@ -455,10 +455,10 @@ 1.198 ST_Ack: begin 1.199 // Ack the transfer to the WISHBONE host 1.200 sdram_mode <= M_Nop; 1.201 - sdram_addr <= 32'd0; 1.202 - sdram_dq_r <= 32'd0; 1.203 - sdram_dq_oe <= 1'b0; // SDRAM drives the DQ bus 1.204 - sdram_dqm <= 4'b1111; // mask off DQM 1.205 + sdram_addr <= 0; 1.206 + sdram_dq_r <= 0; 1.207 + sdram_dq_oe <= 0; // SDRAM drives the DQ bus 1.208 + sdram_dqm <= {(DATA_BITS/4){1'b1}}; // mask off DQM 1.209 if (wb_cyc_i & wb_stb_i) begin 1.210 // CYC and STB high, ack the transfer 1.211 wb_ack_o <= 1'b1;