move all user parameters into top of module

Wed, 18 Aug 2010 14:14:38 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Wed, 18 Aug 2010 14:14:38 +0100
changeset 18
275105a6a36b
parent 17
ac979332d5fd
child 19
d39b0f302ca3

move all user parameters into top of module

wb_sdram.v file | annotate | diff | revisions
     1.1 --- a/wb_sdram.v	Wed Aug 18 14:10:48 2010 +0100
     1.2 +++ b/wb_sdram.v	Wed Aug 18 14:14:38 2010 +0100
     1.3 @@ -4,10 +4,29 @@
     1.4   ****************************************************************************/
     1.5   
     1.6  module wb_sdram #(
     1.7 +	// Data and address bus parameters
     1.8  	parameter	DATA_BITS				= 32,				// Width of SDRAM data bus
     1.9  	parameter	COLADDR_BITS			= 9,				// Number of SDRAM Column Address bits
    1.10  	parameter	BANKADDR_BITS			= 2,				// Number of SDRAM Bank Address bits
    1.11 -	parameter	ROWADDR_BITS			= 12				// Number of SDRAM Row Address bits
    1.12 +	parameter	ROWADDR_BITS			= 12,				// Number of SDRAM Row Address bits
    1.13 +	
    1.14 +	// Timer parameters
    1.15 +	parameter	CAS_LATENCY				= 3'd2,	// CAS latency -- either 2 or 3
    1.16 +	parameter	CLOCK_RATE				= 25_000_000,			// System clock frequency in Hz
    1.17 +
    1.18 +	// SDRAM timings in nanoseconds
    1.19 +	// Precharge to refresh/row activate command (same bank) -- Trp
    1.20 +	parameter	TIME_Trp					= 20,
    1.21 +	// RAS# to CAS# delay -- Trcd
    1.22 +	parameter	TIME_Trcd				= 20,
    1.23 +	// Row cycle time -- Trfc, also known as Trc
    1.24 +	parameter	TIME_Trfc				= 70,
    1.25 +	// Time between refresh cycles -- refresh interval divided by number of rows to refresh (in this case, 64e-3/4096*1e9 --> 15.625us or 15,625ns)
    1.26 +	parameter	TIME_Refresh			= 15_625,
    1.27 +	// 2ms power-up init period (2e6 nanoseconds = 2ms)
    1.28 +	parameter	TIME_InitDelay			= 2_000_000,
    1.29 +	// 2us before the end of the init period, raise CKE (2000ns = 2us)
    1.30 +	parameter	TIME_InitFinal			= 2_000
    1.31  ) (
    1.32  	// Clocks and resets
    1.33  	input										wb_clk_i,		// WISHBONE clock
    1.34 @@ -37,29 +56,9 @@
    1.35  	inout			[DATA_BITS-1:0]		sdram_dq			// SDRAM data bus
    1.36  );
    1.37  
    1.38 -
    1.39  /****
    1.40 - * Timer values
    1.41 + * Timer values -- don't touch!
    1.42   ****/
    1.43 -// CAS latency -- either 2 or 3   [2010-08-10: tested with CL=3, worked fine]
    1.44 -parameter	CAS_LATENCY		= 3'd2;
    1.45 -// System clock frequency
    1.46 -parameter	CLOCK_RATE		= 25_000_000;
    1.47 -
    1.48 -// SDRAM timings in nanoseconds
    1.49 -// Precharge to refresh/row activate command (same bank) -- Trp
    1.50 -parameter	TIME_Trp			= 20;
    1.51 -// RAS# to CAS# delay -- Trcd
    1.52 -parameter	TIME_Trcd		= 20;
    1.53 -// Row cycle time -- Trfc, also known as Trc
    1.54 -parameter	TIME_Trfc		= 70;
    1.55 -// Time between refresh cycles -- refresh interval divided by number of rows to refresh (in this case, 64e-3/4096*1e9 --> 15.625us or 15,625ns)
    1.56 -parameter	TIME_Refresh	= 15_625;
    1.57 -// 2ms power-up init period
    1.58 -parameter	TIME_InitDelay	= 2_000_000;
    1.59 -// 2us before the end of the init period, raise CKE
    1.60 -parameter	TIME_InitFinal	= 2_000;
    1.61 -
    1.62  // Calculate clock period in nanoseconds
    1.63  localparam	CLOCK_PERIOD = 1_000_000_000 / CLOCK_RATE;
    1.64