[wb_sdram] parameterise timing and CAS latency

Tue, 10 Aug 2010 22:11:51 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Tue, 10 Aug 2010 22:11:51 +0100
changeset 10
2e7c2bcdac0e
parent 9
413ec22a27cd
child 11
efeebc7c7498

[wb_sdram] parameterise timing and CAS latency

wb_sdram.v file | annotate | diff | revisions
     1.1 --- a/wb_sdram.v	Tue Aug 10 19:23:01 2010 +0100
     1.2 +++ b/wb_sdram.v	Tue Aug 10 22:11:51 2010 +0100
     1.3 @@ -37,6 +37,21 @@
     1.4  
     1.5  
     1.6  /****
     1.7 + * Timer values
     1.8 + ****/
     1.9 +// CAS latency -- either 2 or 3
    1.10 +parameter	CAS_LATENCY	= 3'd2;
    1.11 +// T_rp  ==> 20ns
    1.12 +parameter	TIME_Trp		= 32'd1;
    1.13 +// T_rcd ==> 20ns
    1.14 +parameter	TIME_Trcd	= 32'd1;
    1.15 +// T_rfc (a.k.a. T_rc) ==> 70ns
    1.16 +parameter	TIME_Trfc	= 32'd2;
    1.17 +// T_mrd ==> 2 clock cycles
    1.18 +parameter	TIME_Tmrd	= 32'd2;
    1.19 +
    1.20 +
    1.21 +/****
    1.22   * WISHBONE status pins
    1.23   ****/
    1.24  // Can't raise bus errors
    1.25 @@ -226,7 +241,7 @@
    1.26  			ST_PrechargeAll: begin
    1.27  					// Precharge All, then wait T_rp (20ns)
    1.28  					sdram_mode <= M_PrechargeAll;
    1.29 -					timer <= 32'd0;	// wait 1tcy (40ns)   ---> TIMER HERE
    1.30 +					timer <= TIME_Trp - 32'd1;
    1.31  					state <= ST_PrechargeAll_Wait;
    1.32  				end
    1.33  
    1.34 @@ -242,7 +257,7 @@
    1.35  			ST_AutoRefresh1: begin
    1.36  					// Auto Refresh 1 of 2, wait T_rfc (70ns) after each
    1.37  					sdram_mode <= M_AutoRefresh;
    1.38 -					timer <= 32'd1;	// wait 2tcy (80ns)  ---> TIMER HERE
    1.39 +					timer <= TIME_Trfc - 32'd1;
    1.40  					state <= ST_AutoRefresh1_Wait;
    1.41  				end
    1.42  				
    1.43 @@ -258,7 +273,7 @@
    1.44  			ST_AutoRefresh2: begin
    1.45  					// Auto Refresh 2 of 2, wait T_rfc (70ns) after each
    1.46  					sdram_mode <= M_AutoRefresh;
    1.47 -					timer <= 32'd1;	// wait 2tcy (80ns)  ---> TIMER HERE
    1.48 +					timer <= TIME_Trfc - 32'd1;
    1.49  					state <= ST_AutoRefresh2_Wait;
    1.50  				end
    1.51  				
    1.52 @@ -279,16 +294,16 @@
    1.53  					 *   - A11,10 = 00  [RFU]
    1.54  					 *   - A9     = 0   [WBL -- write burst length same as read burst length]
    1.55  					 *   - A8,7   = 00  [Test Mode off]
    1.56 -					 *   - A6..4  = 010 [CAS Latency = 2 clocks]
    1.57 +					 *   - A6..4  = 010 [CAS Latency = 2 or 3 clocks, set above]
    1.58  					 *   - A3     = 0   [Burst type = sequential]
    1.59  					 *   - A2..0  = 000 [Burst length = 1 word]
    1.60  					 */
    1.61  					sdram_ba <= 2'b00;
    1.62 -					sdram_addr <= 12'b00_0_00_010_000;
    1.63 +					sdram_addr <= {5'b00_0_00, CAS_LATENCY[2:0], 3'b000};
    1.64  					sdram_mode <= M_LoadModeRegister;
    1.65  
    1.66  					// Wait T_mrd (2 clock cycles)
    1.67 -					timer <= 32'd1;	// (2cy)-1  ---> TIMER HERE
    1.68 +					timer <= TIME_Tmrd - 32'd1;
    1.69  					state <= ST_LoadModeRegister_Wait;
    1.70  				end
    1.71  
    1.72 @@ -334,7 +349,7 @@
    1.73  					// Tell the SDRAM to do a Refresh
    1.74  					sdram_mode <= M_AutoRefresh;
    1.75  					// Wait for T_rfc
    1.76 -					timer <= 32'd1;	// wait Trfc (70ns ideally, we give 80ns)  ---> TIMER HERE
    1.77 +					timer <= TIME_Trfc;
    1.78  					state <= ST_Refresh_Wait;
    1.79  				end
    1.80  				
    1.81 @@ -355,7 +370,7 @@
    1.82  					sdram_mode <= M_BankActivate;
    1.83  					sdram_addr <= row_addr;
    1.84  					sdram_ba   <= bank_addr;
    1.85 -					timer <= 32'd0;		// Wait T_rcd (20ns ideally, here 40ns)	---> TIMER HERE
    1.86 +					timer <= TIME_Trcd - 32'd1;
    1.87  					state <= ST_Activate_Wait;
    1.88  				end
    1.89  				
    1.90 @@ -382,7 +397,7 @@
    1.91  					sdram_dqm	<= ~wb_sel_i;
    1.92  					
    1.93  					// Wait T_rp (20ns)
    1.94 -					timer <= 32'd0;	// wait 1tcy (40ns)   ---> TIMER HERE
    1.95 +					timer <= TIME_Trp - 32'd1;
    1.96  					state <= ST_Wait_Trp;
    1.97  				end
    1.98  
    1.99 @@ -392,7 +407,7 @@
   1.100  					sdram_addr	<= column_addr;
   1.101  					sdram_dq_oe	<= 1'b0;		// SDRAM drives the DQ bus
   1.102  					sdram_dqm	<= 4'b0000;	// Grab all the data (it's just easier that way...)
   1.103 -					timer <= 32'd2 - 32'd1;	// CAS# Latency ---> TIMER HERE
   1.104 +					timer <= CAS_LATENCY - 32'd1;	// CAS# Latency
   1.105  					state <= ST_Read_Wait;
   1.106  				end
   1.107  				
   1.108 @@ -404,7 +419,7 @@
   1.109  						// Latch data
   1.110  						wb_dat_o <= sdram_dq;
   1.111  						// Wait T_rp (20ns)
   1.112 -						timer <= 32'd0;	// wait 1tcy (40ns)   ---> TIMER HERE
   1.113 +						timer <= TIME_Trp - 32'd1;
   1.114  						state <=	ST_Wait_Trp;
   1.115  					end
   1.116  				end