IPCores/wb_sdram / files

     1.1 --- a/wb_sdram.v	Tue Aug 10 17:42:18 2010 +0100
     1.2 +++ b/wb_sdram.v	Tue Aug 10 18:04:05 2010 +0100
     1.3 @@ -150,6 +150,7 @@
     1.4  localparam	ST_Test_Precharge_All_Wait	= 32'd507;
     1.5   
     1.6  reg [31:0] state;
     1.7 +reg [31:0] captured_data;
     1.8  always @(posedge wb_clk_i) begin
     1.9  	if (wb_rst_i) begin
    1.10  		// Initialise state machine and timer
    1.11 @@ -362,7 +363,7 @@
    1.12  					sdram_dqm <= 4'b1111;		// Disable SDRAM output buffers
    1.13  					if (timer == 32'd0) begin
    1.14  						state <= ST_Test_Read_Finish;
    1.15 -						// TODO: capture data locally
    1.16 +						captured_data <= sdram_dq;
    1.17  					end
    1.18  				end
    1.19  
    1.20 @@ -377,7 +378,7 @@
    1.21  					// Write to SDRAM
    1.22  					sdram_mode <= M_Write;
    1.23  					sdram_addr <= column_addr;
    1.24 -					sdram_dq_r <= 32'h55AA_BCDE;
    1.25 +					sdram_dq_r <= ~captured_data; //32'h55AA_BCDE;
    1.26  					sdram_dq_oe <= 1'b1;		// output enable
    1.27  					sdram_dqm <= 4'b0000;		// Allow data through (DQM = OE# = 1 to mask off, 0 to allow)
    1.28  					state <= ST_Test_Precharge_All;