Tue, 10 Aug 2010 19:23:01 +0100
[wb_sdram] move ACK logic around and set DQM from wb_sel_i
write mask (DQM) is now set from WB_SEL_I. reads still pull the whole word.
| wb_sdram.v | file | annotate | diff | revisions |
1.1 --- a/wb_sdram.v Tue Aug 10 18:35:50 2010 +0100 1.2 +++ b/wb_sdram.v Tue Aug 10 19:23:01 2010 +0100 1.3 @@ -309,17 +309,13 @@ 1.4 1.5 // Idle the SDRAM (Inhibit is lower power than NOP on some SDRAMs) 1.6 sdram_mode <= M_Inhibit; 1.7 - 1.8 - // Clear the WISHBONE Ack flag -- NOTE: is this required? 1.9 - wb_ack_o <= 1'b0; 1.10 1.11 + // Check if a refresh is due (these have highest priority) 1.12 if (refresh_req) begin 1.13 // Refresh request received. Ack it and do a refresh. 1.14 refresh_ack <= 1'b1; 1.15 state <= ST_Refresh; 1.16 end else begin 1.17 - //state <= ST_Spin; // NOTE: turned off to run a ram test... 1.18 - //state <= ST_Test_Activate; 1.19 if (wb_cyc_i & wb_stb_i) begin 1.20 // CYC and STB high. A Wishbone cycle just started. 1.21 state <= ST_Activate; 1.22 @@ -383,7 +379,7 @@ 1.23 sdram_addr <= column_addr; 1.24 sdram_dq_r <= wb_dat_i; 1.25 sdram_dq_oe <= 1'b1; // FPGA drives the DQ bus 1.26 - sdram_dqm <= 4'b0000; // TODO: use WB_SEL_I to set these 1.27 + sdram_dqm <= ~wb_sel_i; 1.28 1.29 // Wait T_rp (20ns) 1.30 timer <= 32'd0; // wait 1tcy (40ns) ---> TIMER HERE 1.31 @@ -432,7 +428,8 @@ 1.32 wb_ack_o <= 1'b1; 1.33 state <= ST_Ack; 1.34 end else begin 1.35 - // CYC and STB low, back to the start again... 1.36 + // CYC and STB low, go back and wait for another transaction 1.37 + wb_ack_o <= 1'b0; 1.38 state <= ST_Spin; 1.39 end 1.40 end