IPCores/wb_sdram / files

     1.1 --- a/wb_sdram.v	Wed Aug 11 01:15:20 2010 +0100
     1.2 +++ b/wb_sdram.v	Wed Aug 11 01:19:03 2010 +0100
     1.3 @@ -45,12 +45,18 @@
     1.4  parameter	CLOCK_RATE		= 25_000_000;
     1.5  
     1.6  // SDRAM timings in nanoseconds
     1.7 +// Precharge to refresh/row activate command (same bank) -- Trp
     1.8  parameter	TIME_Trp			= 20;
     1.9 +// RAS# to CAS# delay -- Trcd
    1.10  parameter	TIME_Trcd		= 20;
    1.11 +// Row cycle time -- Trfc, also known as Trc
    1.12  parameter	TIME_Trfc		= 70;
    1.13 +// Time between refresh cycles -- refresh interval divided by number of rows to refresh (in this case, 64e-3/4096*1e9 --> 15.625us or 15,625ns)
    1.14  parameter	TIME_Refresh	= 15_625;
    1.15 -parameter	TIME_InitDelay	= 2_000_000;	// 2ms init period
    1.16 -parameter	TIME_InitFinal	= 2_000;			// 2us before the end of the init period, raise CKE
    1.17 +// 2ms power-up init period
    1.18 +parameter	TIME_InitDelay	= 2_000_000;
    1.19 +// 2us before the end of the init period, raise CKE
    1.20 +parameter	TIME_InitFinal	= 2_000;
    1.21  
    1.22  // Calculate clock period in nanoseconds
    1.23  localparam	CLOCK_PERIOD = 1_000_000_000 / CLOCK_RATE;