add basic R/W test

Tue, 10 Aug 2010 17:36:00 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Tue, 10 Aug 2010 17:36:00 +0100
changeset 4
96badb38531d
parent 3
6a724779fb48
child 5
dd6f40c05963

add basic R/W test

wb_sdram.v file | annotate | diff | revisions
     1.1 --- a/wb_sdram.v	Tue Aug 10 14:41:06 2010 +0100
     1.2 +++ b/wb_sdram.v	Tue Aug 10 17:36:00 2010 +0100
     1.3 @@ -109,6 +109,20 @@
     1.4  
     1.5  assign debug = { 1'b0, refresh_req, refresh_ack };
     1.6  
     1.7 +
     1.8 +/****
     1.9 + * Address decoder
    1.10 + ****/
    1.11 +wire [8:0] column_addr;
    1.12 +wire [11:0] row_addr;
    1.13 +wire [1:0] bank_addr;
    1.14 +
    1.15 +// Convert a 22-bit linear address into an SDRAM address
    1.16 +assign column_addr	= wb_adr_i[8:0];
    1.17 +assign bank_addr		= wb_adr_i[10:9];
    1.18 +assign row_addr		= wb_adr_i[21:11];
    1.19 +
    1.20 +
    1.21  /****
    1.22   * Finite State Machine
    1.23   ****/
    1.24 @@ -126,6 +140,13 @@
    1.25  localparam	ST_Spin							= 32'd11;		// <<== main 'spin' / 'idle' state
    1.26  localparam	ST_Refresh						= 32'd12;
    1.27  localparam	ST_Refresh_Wait				= 32'd13;
    1.28 +localparam	ST_Test_Activate				= 32'd500;
    1.29 +localparam	ST_Test_Activate_Wait		= 32'd501;
    1.30 +localparam	ST_Test_Read					= 32'd502;
    1.31 +localparam	ST_Test_Read_Wait				= 32'd503;
    1.32 +localparam	ST_Test_Write					= 32'd504;
    1.33 +localparam	ST_Test_Precharge_All		= 32'd505;
    1.34 +localparam	ST_Test_Precharge_All_Wait	= 32'd506;
    1.35   
    1.36  reg [31:0] state;
    1.37  always @(posedge wb_clk_i) begin
    1.38 @@ -283,7 +304,8 @@
    1.39  						refresh_ack <= 1'b1;
    1.40  						state <= ST_Refresh;
    1.41  					end else begin
    1.42 -						state <= ST_Spin;
    1.43 +						//state <= ST_Spin;		// NOTE: turned off to run a ram test...
    1.44 +						state <= ST_Test_Activate;
    1.45  					end
    1.46  				end
    1.47  				
    1.48 @@ -306,6 +328,74 @@
    1.49  						state <= ST_Spin;
    1.50  					end
    1.51  				end
    1.52 +				
    1.53 +			ST_Test_Activate: begin
    1.54 +					// Activate bank
    1.55 +					sdram_mode <= M_BankActivate;
    1.56 +					sdram_addr <= row_addr;
    1.57 +					sdram_ba <= bank_addr;
    1.58 +					timer <= 32'd0;	// wait Trcd (20ns ideally, this is 40ns)		---> TIMER HERE
    1.59 +					state <= ST_Test_Activate_Wait;
    1.60 +				end
    1.61 +				
    1.62 +			ST_Test_Activate_Wait: begin
    1.63 +					// Wait for Activate Bank to complete
    1.64 +					sdram_mode <= M_Nop;
    1.65 +					if (timer == 32'd0) begin
    1.66 +						state <= ST_Test_Read;
    1.67 +					end
    1.68 +				end
    1.69 +				
    1.70 +			ST_Test_Read: begin
    1.71 +					// Do the Read operation
    1.72 +					sdram_mode <= M_Read;
    1.73 +					sdram_addr <= column_addr;
    1.74 +					sdram_dqm <= 4'b0000;		// Allow data through (DQM = OE# = 1 to mask off, 0 to allow)
    1.75 +					timer <= 32'd3 - 32'd1;		// wait CAS# Latency (2 clock cycles)	---> TIMER HERE
    1.76 +					state <= ST_Test_Read_Wait;
    1.77 +				end
    1.78 +				
    1.79 +			ST_Test_Read_Wait: begin
    1.80 +					// Wait for CAS latency
    1.81 +					sdram_mode <= M_Nop;
    1.82 +					sdram_dqm <= 4'b1111;		// Disable SDRAM output buffers
    1.83 +					if (timer == 32'd0) begin
    1.84 +						state <= ST_Test_Write;
    1.85 +						// TODO: capture data locally
    1.86 +					end
    1.87 +				end
    1.88 +			
    1.89 +			ST_Test_Write: begin
    1.90 +					// Write to SDRAM
    1.91 +					sdram_mode <= M_Write;
    1.92 +					sdram_addr <= column_addr;
    1.93 +					sdram_dq_r <= 32'h55AA_BCDE;
    1.94 +					sdram_dq_oe <= 1'b1;		// output enable
    1.95 +					sdram_dqm <= 4'b0000;		// Allow data through (DQM = OE# = 1 to mask off, 0 to allow)
    1.96 +					state <= ST_Test_Precharge_All;
    1.97 +				end
    1.98 +				
    1.99 +			ST_Test_Precharge_All: begin
   1.100 +					// Precharge All
   1.101 +					sdram_mode <= M_PrechargeAll;
   1.102 +					sdram_addr <= 12'd0;
   1.103 +					sdram_dq_oe <= 1'b0;		// output disable
   1.104 +					sdram_dqm <= 4'b1111;		// Disable SDRAM output buffers
   1.105 +					sdram_dq_r <= 32'd0;
   1.106 +					state <= ST_Spin;
   1.107 +					// Wait T_rp (20ns)
   1.108 +					timer <= 32'd0;	// wait 1tcy (40ns)   ---> TIMER HERE
   1.109 +					state <= ST_Test_Precharge_All_Wait;
   1.110 +				end
   1.111 +
   1.112 +			ST_Test_Precharge_All_Wait: begin
   1.113 +					// Wait for T_rp after Precharge All
   1.114 +					sdram_mode <= M_Nop;
   1.115 +					if (timer == 32'd0) begin
   1.116 +						// Timer hit zero. Continue
   1.117 +						state <= ST_Spin;
   1.118 +					end
   1.119 +				end
   1.120  		endcase
   1.121  	end
   1.122  end