IPCores/wb_sdram / files

     1.1 --- a/wb_sdram.v	Tue Aug 10 22:51:47 2010 +0100
     1.2 +++ b/wb_sdram.v	Tue Aug 10 23:11:10 2010 +0100
     1.3 @@ -63,6 +63,7 @@
     1.4  // Lock DEBUG pins low
     1.5  assign debug = 3'd0;
     1.6  
     1.7 +
     1.8  /****
     1.9   * SDRAM data output buffer
    1.10   ****/
    1.11 @@ -73,7 +74,6 @@
    1.12  assign sdram_dq = sdram_dq_oe ? sdram_dq_r : 32'hZZZZ;
    1.13  
    1.14  
    1.15 -
    1.16  /****
    1.17   * State timer
    1.18   * This is used to ensure that the state machine abides by RAM timing