comment cleanup default tip

Wed, 18 Aug 2010 14:17:42 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Wed, 18 Aug 2010 14:17:42 +0100
changeset 19
d39b0f302ca3
parent 18
275105a6a36b

comment cleanup

wb_sdram.v file | annotate | diff | revisions
     1.1 --- a/wb_sdram.v	Wed Aug 18 14:14:38 2010 +0100
     1.2 +++ b/wb_sdram.v	Wed Aug 18 14:17:42 2010 +0100
     1.3 @@ -1,6 +1,10 @@
     1.4  /****************************************************************************
     1.5 + * WISHBONE SDRAM CONTROLLER MODULE / IP CORE
     1.6 + * (C) 2010 Philip Pemberton. All Rights Reserved.
     1.7   *
     1.8 - *
     1.9 + * This IP core provides a WISHBONE-compliant interface for most standard
    1.10 + * SDR SDRAM ICs (e.g. the ISSI part on the Enterpoint Drigmorn2 and
    1.11 + * Craignell2 boards).
    1.12   ****************************************************************************/
    1.13   
    1.14  module wb_sdram #(
    1.15 @@ -11,8 +15,8 @@
    1.16  	parameter	ROWADDR_BITS			= 12,				// Number of SDRAM Row Address bits
    1.17  	
    1.18  	// Timer parameters
    1.19 -	parameter	CAS_LATENCY				= 3'd2,	// CAS latency -- either 2 or 3
    1.20 -	parameter	CLOCK_RATE				= 25_000_000,			// System clock frequency in Hz
    1.21 +	parameter	CAS_LATENCY				= 3'd2,			// CAS latency -- either 2 or 3
    1.22 +	parameter	CLOCK_RATE				= 25_000_000,	// System clock frequency in Hz
    1.23  
    1.24  	// SDRAM timings in nanoseconds
    1.25  	// Precharge to refresh/row activate command (same bank) -- Trp