add NOP after read to avoid bus contention when doing back-to-back R/Ws

Tue, 10 Aug 2010 17:42:18 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Tue, 10 Aug 2010 17:42:18 +0100
changeset 5
dd6f40c05963
parent 4
96badb38531d
child 6
39984d9ff640

add NOP after read to avoid bus contention when doing back-to-back R/Ws

wb_sdram.v file | annotate | diff | revisions
     1.1 --- a/wb_sdram.v	Tue Aug 10 17:36:00 2010 +0100
     1.2 +++ b/wb_sdram.v	Tue Aug 10 17:42:18 2010 +0100
     1.3 @@ -144,9 +144,10 @@
     1.4  localparam	ST_Test_Activate_Wait		= 32'd501;
     1.5  localparam	ST_Test_Read					= 32'd502;
     1.6  localparam	ST_Test_Read_Wait				= 32'd503;
     1.7 -localparam	ST_Test_Write					= 32'd504;
     1.8 -localparam	ST_Test_Precharge_All		= 32'd505;
     1.9 -localparam	ST_Test_Precharge_All_Wait	= 32'd506;
    1.10 +localparam	ST_Test_Read_Finish			= 32'd504;
    1.11 +localparam	ST_Test_Write					= 32'd505;
    1.12 +localparam	ST_Test_Precharge_All		= 32'd506;
    1.13 +localparam	ST_Test_Precharge_All_Wait	= 32'd507;
    1.14   
    1.15  reg [31:0] state;
    1.16  always @(posedge wb_clk_i) begin
    1.17 @@ -351,7 +352,7 @@
    1.18  					sdram_mode <= M_Read;
    1.19  					sdram_addr <= column_addr;
    1.20  					sdram_dqm <= 4'b0000;		// Allow data through (DQM = OE# = 1 to mask off, 0 to allow)
    1.21 -					timer <= 32'd3 - 32'd1;		// wait CAS# Latency (2 clock cycles)	---> TIMER HERE
    1.22 +					timer <= 32'd2 - 32'd1;		// wait CAS# Latency (2 clock cycles)	---> TIMER HERE
    1.23  					state <= ST_Test_Read_Wait;
    1.24  				end
    1.25  				
    1.26 @@ -360,10 +361,17 @@
    1.27  					sdram_mode <= M_Nop;
    1.28  					sdram_dqm <= 4'b1111;		// Disable SDRAM output buffers
    1.29  					if (timer == 32'd0) begin
    1.30 -						state <= ST_Test_Write;
    1.31 +						state <= ST_Test_Read_Finish;
    1.32  						// TODO: capture data locally
    1.33  					end
    1.34  				end
    1.35 +
    1.36 +			ST_Test_Read_Finish: begin
    1.37 +					// Additional NOP after read to avoid bus contention if next transaction is a write
    1.38 +					sdram_mode <= M_Nop;
    1.39 +					sdram_dqm <= 4'b1111;	// Disable SDRAM output buffers
    1.40 +					state <= ST_Test_Write;
    1.41 +				end
    1.42  			
    1.43  			ST_Test_Write: begin
    1.44  					// Write to SDRAM