IPCores/wb_sdram / files

     1.1 --- a/wb_sdram.v	Tue Aug 10 22:11:51 2010 +0100
     1.2 +++ b/wb_sdram.v	Tue Aug 10 22:14:22 2010 +0100
     1.3 @@ -1,4 +1,4 @@
     1.4 -/****************************************************************************
     1.5 +	/****************************************************************************
     1.6   *
     1.7   *
     1.8   ****************************************************************************/
     1.9 @@ -58,7 +58,8 @@
    1.10  assign wb_err_o = 1'b0;
    1.11  // Can't request retries
    1.12  assign wb_rty_o = 1'b0;
    1.13 -
    1.14 +// Lock DEBUG pins low
    1.15 +assign debug = 3'd0;
    1.16  
    1.17  /****
    1.18   * SDRAM data output buffer
    1.19 @@ -131,8 +132,6 @@
    1.20  	end
    1.21  end
    1.22  
    1.23 -assign debug = { 1'b0, refresh_req, refresh_ack };
    1.24 -
    1.25  
    1.26  /****
    1.27   * Address decoder
    1.28 @@ -178,7 +177,6 @@
    1.29  	if (wb_rst_i) begin
    1.30  		// Initialise state machine and timer
    1.31  		state <= ST_INIT1;
    1.32 -//		debug <= 3'd0;
    1.33  		timer <= 32'd0;
    1.34  		
    1.35  		// Clear REFRESH ACK flag and disable refresh timer
    1.36 @@ -227,7 +225,6 @@
    1.37  						// keep waiting for the timer to actually expire.
    1.38  						sdram_cke	<= 1'b1;
    1.39  						state			<= ST_INIT2;
    1.40 -//						debug <= 3'd1;
    1.41  					end
    1.42  					sdram_mode <= M_Inhibit;
    1.43  				end