comment cleanup
default tip
Philip Pemberton
Wed, 18 Aug 2010 14:17:42 +0100
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move all user parameters into top of module
Philip Pemberton
Wed, 18 Aug 2010 14:14:38 +0100
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parameterise data and addr. buses, tidy up
Philip Pemberton
Wed, 18 Aug 2010 14:10:48 +0100
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[wb_sdram] add nice comments to explain sdram timings
Philip Pemberton
Wed, 11 Aug 2010 01:19:03 +0100
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fully parameterise CLOCK_RATE and SDRAM timing
Philip Pemberton
Wed, 11 Aug 2010 01:15:20 +0100
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[wb_sdram] code tidy up
Philip Pemberton
Tue, 10 Aug 2010 23:11:10 +0100
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[wb_sdram] add note re. CL=3 testing
Philip Pemberton
Tue, 10 Aug 2010 22:51:47 +0100
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[wb_sdram] tidy up refresh time parameterisation
Philip Pemberton
Tue, 10 Aug 2010 22:49:21 +0100
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[wb_sdram] lock debug pins low
Philip Pemberton
Tue, 10 Aug 2010 22:14:22 +0100
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[wb_sdram] parameterise timing and CAS latency
Philip Pemberton
Tue, 10 Aug 2010 22:11:51 +0100
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[wb_sdram] move ACK logic around and set DQM from wb_sel_i
Philip Pemberton
Tue, 10 Aug 2010 19:23:01 +0100
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[wb_sdram] add drivers for unused WISHBONE i/os
Philip Pemberton
Tue, 10 Aug 2010 18:35:50 +0100
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[wb_sdram] remove test logic and convert into a proper WISHBONE peripheral
Philip Pemberton
Tue, 10 Aug 2010 18:33:25 +0100
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make test work like a R/W checkerboard instead (looks better on the LA)
Philip Pemberton
Tue, 10 Aug 2010 18:04:05 +0100
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add NOP after read to avoid bus contention when doing back-to-back R/Ws
Philip Pemberton
Tue, 10 Aug 2010 17:42:18 +0100
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add basic R/W test
Philip Pemberton
Tue, 10 Aug 2010 17:36:00 +0100
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add refresh timer and refresh FSM logic
Philip Pemberton
Tue, 10 Aug 2010 14:41:06 +0100
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implement (almost) complete SDRAM init sequence
Philip Pemberton
Tue, 10 Aug 2010 13:23:58 +0100
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make spinstate more noticeable on LA, fix CKE init timer
Philip Pemberton
Tue, 10 Aug 2010 12:58:34 +0100
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add clock generator DCM and preliminary homebrew WISHBONE SDRAM controller
Philip Pemberton
Mon, 09 Aug 2010 20:45:49 +0100
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