3b1emu / file diff

diff: src/main.c

src/main.c

changeset 87
822d8b2c4639
parent 79
674226015c8a
child 90
934ae2efdd01
     1.1 --- a/src/main.c	Thu Dec 30 00:37:03 2010 +0000
     1.2 +++ b/src/main.c	Thu Dec 30 00:41:48 2010 +0000
     1.3 @@ -210,7 +210,7 @@
     1.4  	uint32_t next_timeslot = SDL_GetTicks() + MILLISECS_PER_TIMESLOT;
     1.5  	uint32_t clock_cycles = 0;
     1.6  	bool exitEmu = false;
     1.7 -	bool lastirq_fdc = false;
     1.8 +//	bool lastirq_fdc = false;
     1.9  	for (;;) {
    1.10  		// Run the CPU for however many cycles we need to. CPU core clock is
    1.11  		// 10MHz, and we're running at 240Hz/timeslot. Thus: 10e6/240 or
    1.12 @@ -333,6 +333,7 @@
    1.13  				lastirq_fdc = false;
    1.14  			}
    1.15  		} else {
    1.16 +			lastirq_fdc = wd2797_get_irq(&state.fdc_ctx);
    1.17  			m68k_set_irq(0);
    1.18  		}
    1.19  */