Sat, 17 Nov 2012 22:26:53 +0000
Add support for MSR2, partial reads from GENSTAT
* GENSTAT is sometimes read in 8bit mode. Handle this properly.
* Add support for the MSR2 register (additional HDD head select bit only at
the moment)
1 #include <stdio.h>
2 #include <stdlib.h>
3 #include <stdint.h>
4 #include <stdbool.h>
5 #include <assert.h>
6 #include "musashi/m68k.h"
7 #include "state.h"
8 #include "utils.h"
9 #include "memory.h"
11 /******************
12 * Memory mapping
13 ******************/
15 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
17 uint32_t mapAddr(uint32_t addr, bool writing)/*{{{*/
18 {
19 if (addr < 0x400000) {
20 // RAM access. Check against the Map RAM
21 // Start by getting the original page address
22 uint16_t page = (addr >> 12) & 0x3FF;
24 // Look it up in the map RAM and get the physical page address
25 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
27 // Update the Page Status bits
28 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
29 // Pagebits --
30 // 0 = not present
31 // 1 = present but not accessed
32 // 2 = present, accessed (read from)
33 // 3 = present, dirty (written to)
34 switch (pagebits) {
35 case 0:
36 // Page not present
37 // This should cause a page fault
38 LOGS("Whoa! Pagebit update, when the page is not present!");
39 break;
41 case 1:
42 // Page present -- first access
43 state.map[page*2] &= 0x9F; // turn off "present" bit (but not write enable!)
44 if (writing)
45 state.map[page*2] |= 0x60; // Page written to (dirty)
46 else
47 state.map[page*2] |= 0x40; // Page accessed but not written
48 break;
50 case 2:
51 case 3:
52 // Page present, 2nd or later access
53 if (writing)
54 state.map[page*2] |= 0x60; // Page written to (dirty)
55 break;
56 }
58 // Return the address with the new physical page spliced in
59 return (new_page_addr << 12) + (addr & 0xFFF);
60 } else {
61 // I/O, VRAM or MapRAM space; no mapping is performed or required
62 // TODO: assert here?
63 return addr;
64 }
65 }/*}}}*/
67 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)/*{{{*/
68 {
69 // Get the page bits for this page.
70 uint16_t page = (addr >> 12) & 0x3FF;
71 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
73 // Check page is present (but only for RAM zone)
74 if ((addr < 0x400000) && ((pagebits & 0x03) == 0)) {
75 LOG("Page not mapped in: addr %08X, page %04X, mapbits %04X", addr, page, MAPRAM(page));
76 return MEM_PAGEFAULT;
77 }
79 // Are we in Supervisor mode?
80 if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
81 // Yes. We can do anything we like.
82 return MEM_ALLOWED;
84 // If we're here, then we must be in User mode.
85 // Check that the user didn't access memory outside of the RAM area
86 if (addr >= 0x400000) {
87 LOGS("User accessed privileged memory");
88 return MEM_UIE;
89 }
91 // User attempt to access the kernel
92 // A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
93 if (((addr >> 19) & 0x0F) == 0) {
94 LOGS("Attempt by user code to access kernel space");
95 return MEM_KERNEL;
96 }
98 // Check page is write enabled
99 if (writing && ((pagebits & 0x04) == 0)) {
100 LOG("Page not write enabled: inaddr %08X, page %04X, mapram %04X [%02X %02X], pagebits %d",
101 addr, page, MAPRAM(page), state.map[page*2], state.map[(page*2)+1], pagebits);
102 return MEM_PAGE_NO_WE;
103 }
105 // Page access allowed.
106 return MEM_ALLOWED;
107 }/*}}}*/
109 #undef MAPRAM
112 /********************************************************
113 * m68k memory read/write support functions for Musashi
114 ********************************************************/
116 /**
117 * @brief Check memory access permissions for a write operation.
118 * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but
119 * gcc throws warnings when you have a return-with-value in a void
120 * function, even if the return-with-value is completely unreachable.
121 * Similarly it doesn't like it if you have a return without a value
122 * in a non-void function, even if it's impossible to ever reach the
123 * return-with-no-value. UGH!
124 */
125 /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
126 #define ACCESS_CHECK_WR(address, bits) \
127 do { \
128 bool fault = false; \
129 MEM_STATUS st; \
130 switch (st = checkMemoryAccess(address, true)) { \
131 case MEM_ALLOWED: \
132 /* Access allowed */ \
133 break; \
134 case MEM_PAGEFAULT: \
135 /* Page fault */ \
136 state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0); \
137 fault = true; \
138 break; \
139 case MEM_UIE: \
140 /* User access to memory above 4MB */ \
141 state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0); \
142 fault = true; \
143 break; \
144 case MEM_KERNEL: \
145 case MEM_PAGE_NO_WE: \
146 /* kernel access or page not write enabled */ \
147 /* XXX: is this the correct value? */ \
148 state.genstat = 0x9BFF | (state.pie ? 0x0400 : 0); \
149 fault = true; \
150 break; \
151 } \
152 \
153 if (fault) { \
154 if (bits >= 16) \
155 state.bsr0 = 0x7C00; \
156 else \
157 state.bsr0 = (address & 1) ? 0x7E00 : 0x7D00; \
158 state.bsr0 |= (address >> 16); \
159 state.bsr1 = address & 0xffff; \
160 LOG("Bus Error while writing, addr %08X, statcode %d", address, st); \
161 if (state.ee) m68k_pulse_bus_error(); \
162 return; \
163 } \
164 } while (0)
165 /*}}}*/
167 /**
168 * @brief Check memory access permissions for a read operation.
169 * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but
170 * gcc throws warnings when you have a return-with-value in a void
171 * function, even if the return-with-value is completely unreachable.
172 * Similarly it doesn't like it if you have a return without a value
173 * in a non-void function, even if it's impossible to ever reach the
174 * return-with-no-value. UGH!
175 */
176 /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
177 #define ACCESS_CHECK_RD(address, bits) \
178 do { \
179 bool fault = false; \
180 MEM_STATUS st; \
181 switch (st = checkMemoryAccess(address, false)) { \
182 case MEM_ALLOWED: \
183 /* Access allowed */ \
184 break; \
185 case MEM_PAGEFAULT: \
186 /* Page fault */ \
187 state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0); \
188 fault = true; \
189 break; \
190 case MEM_UIE: \
191 /* User access to memory above 4MB */ \
192 state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0); \
193 fault = true; \
194 break; \
195 case MEM_KERNEL: \
196 case MEM_PAGE_NO_WE: \
197 /* kernel access or page not write enabled */ \
198 /* XXX: is this the correct value? */ \
199 state.genstat = 0xDBFF | (state.pie ? 0x0400 : 0); \
200 fault = true; \
201 break; \
202 } \
203 \
204 if (fault) { \
205 if (bits >= 16) \
206 state.bsr0 = 0x7C00; \
207 else \
208 state.bsr0 = (address & 1) ? 0x7E00 : 0x7D00; \
209 state.bsr0 |= (address >> 16); \
210 state.bsr1 = address & 0xffff; \
211 LOG("Bus Error while reading, addr %08X, statcode %d", address, st); \
212 if (state.ee) m68k_pulse_bus_error(); \
213 if (bits == 32) \
214 return 0xFFFFFFFF; \
215 else \
216 return (1UL << bits)-1; \
217 } \
218 } while (0)
219 /*}}}*/
221 bool access_check_dma(int reading)
222 {
223 // Check memory access permissions
224 bool access_ok;
225 switch (checkMemoryAccess(state.dma_address, !reading)) {
226 case MEM_PAGEFAULT:
227 // Page fault
228 state.genstat = 0xABFF
229 | (reading ? 0x4000 : 0)
230 | (state.pie ? 0x0400 : 0);
231 access_ok = false;
232 break;
234 case MEM_UIE:
235 // User access to memory above 4MB
236 // FIXME? Shouldn't be possible with DMA... assert this?
237 state.genstat = 0xBAFF
238 | (reading ? 0x4000 : 0)
239 | (state.pie ? 0x0400 : 0);
240 access_ok = false;
241 break;
243 case MEM_KERNEL:
244 case MEM_PAGE_NO_WE:
245 // Kernel access or page not write enabled
246 /* XXX: is this correct? */
247 state.genstat = 0xBBFF
248 | (reading ? 0x4000 : 0)
249 | (state.pie ? 0x0400 : 0);
250 access_ok = false;
251 break;
253 case MEM_ALLOWED:
254 access_ok = true;
255 break;
256 }
257 if (!access_ok) {
258 state.bsr0 = 0x3C00;
259 state.bsr0 |= (state.dma_address >> 16);
260 state.bsr1 = state.dma_address & 0xffff;
261 if (state.ee) m68k_set_irq(7);
262 printf("BUS ERROR FROM DMA: genstat=%04X, bsr0=%04X, bsr1=%04X\n", state.genstat, state.bsr0, state.bsr1);
263 }
264 return (access_ok);
265 }
267 // Logging macros
268 #define LOG_NOT_HANDLED_R(bits) \
269 if (!handled) printf("unhandled read%02d, addr=0x%08X\n", bits, address);
271 #define LOG_NOT_HANDLED_W(bits) \
272 if (!handled) printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
274 /********************************************************
275 * I/O read/write functions
276 ********************************************************/
278 /**
279 * Issue a warning if a read operation is made with an invalid size
280 */
281 inline static void ENFORCE_SIZE(int bits, uint32_t address, bool read, int allowed, char *regname)
282 {
283 assert((bits == 8) || (bits == 16) || (bits == 32));
284 if ((bits & allowed) == 0) {
285 printf("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits);
286 }
287 }
289 inline static void ENFORCE_SIZE_R(int bits, uint32_t address, int allowed, char *regname)
290 {
291 ENFORCE_SIZE(bits, address, true, allowed, regname);
292 }
294 inline static void ENFORCE_SIZE_W(int bits, uint32_t address, int allowed, char *regname)
295 {
296 ENFORCE_SIZE(bits, address, false, allowed, regname);
297 }
299 void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/
300 {
301 bool handled = false;
303 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
304 // I/O register space, zone A
305 switch (address & 0x0F0000) {
306 case 0x010000: // General Status Register
307 if (bits == 16)
308 state.genstat = (data & 0xffff);
309 else if (bits == 8) {
310 if (address & 0)
311 state.genstat = data;
312 else
313 state.genstat = data << 8;
314 }
315 handled = true;
316 break;
317 case 0x030000: // Bus Status Register 0
318 break;
319 case 0x040000: // Bus Status Register 1
320 break;
321 case 0x050000: // Phone status
322 break;
323 case 0x060000: // DMA Count
324 ENFORCE_SIZE_W(bits, address, 16, "DMACOUNT");
325 state.dma_count = (data & 0x3FFF);
326 state.idmarw = ((data & 0x4000) == 0x4000);
327 state.dmaen = ((data & 0x8000) == 0x8000);
328 // This handles the "dummy DMA transfer" mentioned in the docs
329 // disabled because it causes the floppy test to fail
330 #if 0
331 if (!state.idmarw){
332 if (access_check_dma(true)){
333 uint32_t newAddr = mapAddr(state.dma_address, true);
334 // RAM access
335 if (newAddr <= 0x1fffff)
336 WR16(state.base_ram, newAddr, state.base_ram_size - 1, 0xFF);
337 else if (address <= 0x3FFFFF)
338 WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, 0xFF);
339 }
340 }
341 #endif
342 state.dma_count++;
343 handled = true;
344 break;
345 case 0x070000: // Line Printer Status Register
346 break;
347 case 0x080000: // Real Time Clock
348 break;
349 case 0x090000: // Phone registers
350 switch (address & 0x0FF000) {
351 case 0x090000: // Handset relay
352 case 0x098000:
353 break;
354 case 0x091000: // Line select 2
355 case 0x099000:
356 break;
357 case 0x092000: // Hook relay 1
358 case 0x09A000:
359 break;
360 case 0x093000: // Hook relay 2
361 case 0x09B000:
362 break;
363 case 0x094000: // Line 1 hold
364 case 0x09C000:
365 break;
366 case 0x095000: // Line 2 hold
367 case 0x09D000:
368 break;
369 case 0x096000: // Line 1 A-lead
370 case 0x09E000:
371 break;
372 case 0x097000: // Line 2 A-lead
373 case 0x09F000:
374 break;
375 }
376 break;
377 case 0x0A0000: // Miscellaneous Control Register
378 ENFORCE_SIZE_W(bits, address, 16, "MISCCON");
379 // TODO: handle the ctrl bits properly
380 if (data & 0x8000){
381 state.timer_enabled = 1;
382 }else{
383 state.timer_enabled = 0;
384 state.timer_asserted = 0;
385 }
386 state.dma_reading = (data & 0x4000);
387 if (state.leds != ((~data & 0xF00) >> 8)) {
388 state.leds = (~data & 0xF00) >> 8;
389 printf("LEDs: %s %s %s %s\n",
390 (state.leds & 8) ? "R" : "-",
391 (state.leds & 4) ? "G" : "-",
392 (state.leds & 2) ? "Y" : "-",
393 (state.leds & 1) ? "R" : "-");
394 }
395 handled = true;
396 break;
397 case 0x0B0000: // TM/DIALWR
398 break;
399 case 0x0C0000: // Clear Status Register
400 state.genstat = 0xFFFF;
401 state.bsr0 = 0xFFFF;
402 state.bsr1 = 0xFFFF;
403 handled = true;
404 break;
405 case 0x0D0000: // DMA Address Register
406 if (address & 0x004000) {
407 // A14 high -- set most significant bits
408 state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
409 } else {
410 // A14 low -- set least significant bits
411 state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
412 }
413 handled = true;
414 break;
415 case 0x0E0000: // Disk Control Register
416 {
417 bool fd_selected;
418 bool hd_selected;
419 ENFORCE_SIZE_W(bits, address, 16, "DISKCON");
420 // B7 = FDD controller reset
421 if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
422 // B6 = drive 0 select
423 fd_selected = (data & 0x40) != 0;
424 // B5 = motor enable -- TODO
425 // B4 = HDD controller reset
426 if ((data & 0x10) == 0) wd2010_reset(&state.hdc_ctx);
427 // B3 = HDD0 select
428 hd_selected = (data & 0x08) != 0;
429 // B2,1,0 = HDD0 head select -- TODO?
430 if (hd_selected && !state.hd_selected){
431 state.fd_selected = false;
432 state.hd_selected = true;
433 }else if (fd_selected && !state.fd_selected){
434 state.hd_selected = false;
435 state.fd_selected = true;
436 }
437 handled = true;
438 break;
439 }
440 case 0x0F0000: // Line Printer Data Register
441 break;
442 }
443 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
444 // I/O register space, zone B
445 switch (address & 0xF00000) {
446 case 0xC00000: // Expansion slots
447 case 0xD00000:
448 switch (address & 0xFC0000) {
449 case 0xC00000: // Expansion slot 0
450 case 0xC40000: // Expansion slot 1
451 case 0xC80000: // Expansion slot 2
452 case 0xCC0000: // Expansion slot 3
453 case 0xD00000: // Expansion slot 4
454 case 0xD40000: // Expansion slot 5
455 case 0xD80000: // Expansion slot 6
456 case 0xDC0000: // Expansion slot 7
457 fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data);
458 handled = true;
459 break;
460 }
461 break;
462 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
463 case 0xF00000:
464 switch (address & 0x070000) {
465 case 0x000000: // [ef][08]xxxx ==> WD2010 hard disc controller
466 wd2010_write_reg(&state.hdc_ctx, (address >> 1) & 7, data);
467 handled = true;
468 break;
469 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
470 /*ENFORCE_SIZE_W(bits, address, 16, "FDC REGISTERS");*/
471 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data);
472 handled = true;
473 break;
474 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
475 // MCR2 - UNIX PC Rev. P5.1 HDD head select b3 and potential HDD#2 select
476 wd2010_write_reg(&state.hdc_ctx, UNIXPC_REG_MCR2, data);
477 handled = true;
478 break;
479 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
480 break;
481 case 0x040000: // [ef][4c]xxxx ==> General Control Register
482 switch (address & 0x077000) {
483 case 0x040000: // [ef][4c][08]xxx ==> EE
484 // Error Enable. If =0, Level7 intrs and bus errors are masked.
485 ENFORCE_SIZE_W(bits, address, 16, "EE");
486 state.ee = ((data & 0x8000) == 0x8000);
487 handled = true;
488 break;
489 case 0x041000: // [ef][4c][19]xxx ==> PIE
490 ENFORCE_SIZE_W(bits, address, 16, "PIE");
491 state.pie = ((data & 0x8000) == 0x8000);
492 handled = true;
493 break;
494 case 0x042000: // [ef][4c][2A]xxx ==> BP
495 break;
496 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
497 ENFORCE_SIZE_W(bits, address, 16, "ROMLMAP");
498 state.romlmap = ((data & 0x8000) == 0x8000);
499 handled = true;
500 break;
501 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
502 ENFORCE_SIZE_W(bits, address, 16, "L1 MODEM");
503 break;
504 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
505 ENFORCE_SIZE_W(bits, address, 16, "L2 MODEM");
506 break;
507 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
508 ENFORCE_SIZE_W(bits, address, 16, "D/N CONNECT");
509 break;
510 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
511 ENFORCE_SIZE_W(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO");
512 break;
513 }
514 case 0x050000: // [ef][5d]xxxx ==> 8274
515 break;
516 case 0x060000: // [ef][6e]xxxx ==> Control regs
517 switch (address & 0x07F000) {
518 default:
519 break;
520 }
521 break;
522 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
523 // TODO: figure out which sizes are valid (probably just 8 and 16)
524 // ENFORCE_SIZE_W(bits, address, 16, "KEYBOARD CONTROLLER");
525 if (bits == 8) {
526 printf("KBD WR %02X => %02X\n", (address >> 1) & 3, data);
527 keyboard_write(&state.kbd, (address >> 1) & 3, data);
528 handled = true;
529 } else if (bits == 16) {
530 printf("KBD WR %02X => %04X\n", (address >> 1) & 3, data);
531 keyboard_write(&state.kbd, (address >> 1) & 3, data >> 8);
532 handled = true;
533 }
534 break;
535 }
536 }
537 }
539 LOG_NOT_HANDLED_W(bits);
540 }/*}}}*/
542 uint32_t IoRead(uint32_t address, int bits)/*{{{*/
543 {
544 bool handled = false;
545 uint32_t data = 0xFFFFFFFF;
547 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
548 // I/O register space, zone A
549 switch (address & 0x0F0000) {
550 case 0x010000: // General Status Register
551 /* ENFORCE_SIZE_R(bits, address, 16, "GENSTAT"); */
552 if (bits == 32) {
553 return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
554 } else if (bits == 16) {
555 return (uint16_t)state.genstat;
556 } else {
557 return (uint8_t)(state.genstat & 0xff);
558 }
559 break;
560 case 0x030000: // Bus Status Register 0
561 ENFORCE_SIZE_R(bits, address, 16, "BSR0");
562 return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
563 break;
564 case 0x040000: // Bus Status Register 1
565 ENFORCE_SIZE_R(bits, address, 16, "BSR1");
566 return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
567 break;
568 case 0x050000: // Phone status
569 ENFORCE_SIZE_R(bits, address, 8 | 16, "PHONE STATUS");
570 break;
571 case 0x060000: // DMA Count
572 // TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
573 // Bit 14 is always unused, so leave it set
574 ENFORCE_SIZE_R(bits, address, 16, "DMACOUNT");
575 return (state.dma_count & 0x3fff) | 0xC000;
576 break;
577 case 0x070000: // Line Printer Status Register
578 data = 0x00120012; // no parity error, no line printer error, no irqs from FDD or HDD
579 data |= wd2797_get_irq(&state.fdc_ctx) ? 0x00080008 : 0;
580 data |= wd2010_get_irq(&state.hdc_ctx) ? 0x00040004 : 0;
581 return data;
582 break;
583 case 0x080000: // Real Time Clock
584 printf("READ NOTIMP: Realtime Clock\n");
585 break;
586 case 0x090000: // Phone registers
587 switch (address & 0x0FF000) {
588 case 0x090000: // Handset relay
589 case 0x098000:
590 break;
591 case 0x091000: // Line select 2
592 case 0x099000:
593 break;
594 case 0x092000: // Hook relay 1
595 case 0x09A000:
596 break;
597 case 0x093000: // Hook relay 2
598 case 0x09B000:
599 break;
600 case 0x094000: // Line 1 hold
601 case 0x09C000:
602 break;
603 case 0x095000: // Line 2 hold
604 case 0x09D000:
605 break;
606 case 0x096000: // Line 1 A-lead
607 case 0x09E000:
608 break;
609 case 0x097000: // Line 2 A-lead
610 case 0x09F000:
611 break;
612 }
613 break;
614 case 0x0A0000: // Miscellaneous Control Register -- write only!
615 handled = true;
616 break;
617 case 0x0B0000: // TM/DIALWR
618 break;
619 case 0x0C0000: // Clear Status Register -- write only!
620 handled = true;
621 break;
622 case 0x0D0000: // DMA Address Register
623 break;
624 case 0x0E0000: // Disk Control Register
625 break;
626 case 0x0F0000: // Line Printer Data Register
627 break;
628 }
629 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
630 // I/O register space, zone B
631 switch (address & 0xF00000) {
632 case 0xC00000: // Expansion slots
633 case 0xD00000:
634 switch (address & 0xFC0000) {
635 case 0xC00000: // Expansion slot 0
636 case 0xC40000: // Expansion slot 1
637 case 0xC80000: // Expansion slot 2
638 case 0xCC0000: // Expansion slot 3
639 case 0xD00000: // Expansion slot 4
640 case 0xD40000: // Expansion slot 5
641 case 0xD80000: // Expansion slot 6
642 case 0xDC0000: // Expansion slot 7
643 fprintf(stderr, "NOTE: RD%d from expansion card space, addr=0x%08X\n", bits, address);
644 handled = true;
645 break;
646 }
647 break;
648 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
649 case 0xF00000:
650 switch (address & 0x070000) {
651 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
652 return (wd2010_read_reg(&state.hdc_ctx, (address >> 1) & 7));
654 break;
655 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
656 /*ENFORCE_SIZE_R(bits, address, 16, "FDC REGISTERS");*/
657 return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
658 break;
659 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
660 break;
661 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
662 break;
663 case 0x040000: // [ef][4c]xxxx ==> General Control Register
664 switch (address & 0x077000) {
665 case 0x040000: // [ef][4c][08]xxx ==> EE
666 case 0x041000: // [ef][4c][19]xxx ==> PIE
667 case 0x042000: // [ef][4c][2A]xxx ==> BP
668 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
669 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
670 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
671 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
672 // All write-only registers... TODO: bus error?
673 handled = true;
674 break;
675 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
676 break;
677 }
678 break;
679 case 0x050000: // [ef][5d]xxxx ==> 8274
680 break;
681 case 0x060000: // [ef][6e]xxxx ==> Control regs
682 switch (address & 0x07F000) {
683 default:
684 break;
685 }
686 break;
687 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
688 // TODO: figure out which sizes are valid (probably just 8 and 16)
689 //ENFORCE_SIZE_R(bits, address, 16, "KEYBOARD CONTROLLER");
690 {
691 if (bits == 8) {
692 return keyboard_read(&state.kbd, (address >> 1) & 3);
693 } else {
694 return keyboard_read(&state.kbd, (address >> 1) & 3) << 8;
695 }
696 return data;
697 }
698 break;
699 }
700 }
701 }
703 LOG_NOT_HANDLED_R(bits);
705 return data;
706 }/*}}}*/
709 /********************************************************
710 * m68k memory read/write support functions for Musashi
711 ********************************************************/
713 /**
714 * @brief Read M68K memory, 32-bit
715 */
716 uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/
717 {
718 uint32_t data = 0xFFFFFFFF;
720 // If ROMLMAP is set, force system to access ROM
721 if (!state.romlmap)
722 address |= 0x800000;
724 // Check access permissions
725 ACCESS_CHECK_RD(address, 32);
727 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
728 // ROM access
729 return RD32(state.rom, address, ROM_SIZE - 1);
730 } else if (address <= 0x3fffff) {
731 // RAM access
732 uint32_t newAddr = mapAddr(address, false);
733 if (newAddr <= 0x1fffff) {
734 return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
735 } else {
736 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
737 return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
738 else
739 return 0xffffffff;
740 }
741 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
742 // I/O register space, zone A
743 switch (address & 0x0F0000) {
744 case 0x000000: // Map RAM access
745 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
746 return RD32(state.map, address, 0x7FF);
747 break;
748 case 0x020000: // Video RAM
749 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
750 return RD32(state.vram, address, 0x7FFF);
751 break;
752 default:
753 return IoRead(address, 32);
754 }
755 } else {
756 return IoRead(address, 32);
757 }
759 return data;
760 }/*}}}*/
762 /**
763 * @brief Read M68K memory, 16-bit
764 */
765 uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/
766 {
767 uint16_t data = 0xFFFF;
769 // If ROMLMAP is set, force system to access ROM
770 if (!state.romlmap)
771 address |= 0x800000;
773 // Check access permissions
774 ACCESS_CHECK_RD(address, 16);
776 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
777 // ROM access
778 data = RD16(state.rom, address, ROM_SIZE - 1);
779 } else if (address <= 0x3fffff) {
780 // RAM access
781 uint32_t newAddr = mapAddr(address, false);
782 if (newAddr <= 0x1fffff) {
783 return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
784 } else {
785 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
786 return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
787 else
788 return 0xffff;
789 }
790 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
791 // I/O register space, zone A
792 switch (address & 0x0F0000) {
793 case 0x000000: // Map RAM access
794 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
795 data = RD16(state.map, address, 0x7FF);
796 break;
797 case 0x020000: // Video RAM
798 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
799 data = RD16(state.vram, address, 0x7FFF);
800 break;
801 default:
802 data = IoRead(address, 16);
803 }
804 } else {
805 data = IoRead(address, 16);
806 }
808 return data;
809 }/*}}}*/
811 /**
812 * @brief Read M68K memory, 8-bit
813 */
814 uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/
815 {
816 uint8_t data = 0xFF;
818 // If ROMLMAP is set, force system to access ROM
819 if (!state.romlmap)
820 address |= 0x800000;
822 // Check access permissions
823 ACCESS_CHECK_RD(address, 8);
825 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
826 // ROM access
827 data = RD8(state.rom, address, ROM_SIZE - 1);
828 } else if (address <= 0x3fffff) {
829 // RAM access
830 uint32_t newAddr = mapAddr(address, false);
831 if (newAddr <= 0x1fffff) {
832 return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
833 } else {
834 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
835 return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
836 else
837 return 0xff;
838 }
839 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
840 // I/O register space, zone A
841 switch (address & 0x0F0000) {
842 case 0x000000: // Map RAM access
843 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
844 data = RD8(state.map, address, 0x7FF);
845 break;
846 case 0x020000: // Video RAM
847 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
848 data = RD8(state.vram, address, 0x7FFF);
849 break;
850 default:
851 data = IoRead(address, 8);
852 }
853 } else {
854 data = IoRead(address, 8);
855 }
857 return data;
858 }/*}}}*/
860 /**
861 * @brief Write M68K memory, 32-bit
862 */
863 void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/
864 {
865 // If ROMLMAP is set, force system to access ROM
866 if (!state.romlmap)
867 address |= 0x800000;
869 // Check access permissions
870 ACCESS_CHECK_WR(address, 32);
872 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
873 // ROM access
874 } else if (address <= 0x3FFFFF) {
875 // RAM access
876 uint32_t newAddr = mapAddr(address, true);
877 if (newAddr <= 0x1fffff)
878 WR32(state.base_ram, newAddr, state.base_ram_size - 1, value);
879 else
880 WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
881 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
882 // I/O register space, zone A
883 switch (address & 0x0F0000) {
884 case 0x000000: // Map RAM access
885 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X\n", address);
886 WR32(state.map, address, 0x7FF, value);
887 break;
888 case 0x020000: // Video RAM
889 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X\n", address);
890 WR32(state.vram, address, 0x7FFF, value);
891 break;
892 default:
893 IoWrite(address, value, 32);
894 }
895 } else {
896 IoWrite(address, value, 32);
897 }
898 }/*}}}*/
900 /**
901 * @brief Write M68K memory, 16-bit
902 */
903 void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/
904 {
905 // If ROMLMAP is set, force system to access ROM
906 if (!state.romlmap)
907 address |= 0x800000;
909 // Check access permissions
910 ACCESS_CHECK_WR(address, 16);
912 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
913 // ROM access
914 } else if (address <= 0x3FFFFF) {
915 // RAM access
916 uint32_t newAddr = mapAddr(address, true);
918 if (newAddr <= 0x1fffff)
919 WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
920 else
921 WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
922 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
923 // I/O register space, zone A
924 switch (address & 0x0F0000) {
925 case 0x000000: // Map RAM access
926 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
927 WR16(state.map, address, 0x7FF, value);
928 break;
929 case 0x020000: // Video RAM
930 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
931 WR16(state.vram, address, 0x7FFF, value);
932 break;
933 default:
934 IoWrite(address, value, 16);
935 }
936 } else {
937 IoWrite(address, value, 16);
938 }
939 }/*}}}*/
941 /**
942 * @brief Write M68K memory, 8-bit
943 */
944 void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/
945 {
946 // If ROMLMAP is set, force system to access ROM
947 if (!state.romlmap)
948 address |= 0x800000;
950 // Check access permissions
951 ACCESS_CHECK_WR(address, 8);
953 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
954 // ROM access (read only!)
955 } else if (address <= 0x3FFFFF) {
956 // RAM access
957 uint32_t newAddr = mapAddr(address, true);
958 if (newAddr <= 0x1fffff)
959 WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
960 else
961 WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
962 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
963 // I/O register space, zone A
964 switch (address & 0x0F0000) {
965 case 0x000000: // Map RAM access
966 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
967 WR8(state.map, address, 0x7FF, value);
968 break;
969 case 0x020000: // Video RAM
970 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
971 WR8(state.vram, address, 0x7FFF, value);
972 break;
973 default:
974 IoWrite(address, value, 8);
975 }
976 } else {
977 IoWrite(address, value, 8);
978 }
979 }/*}}}*/
982 // for the disassembler
983 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
984 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
985 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }