Wed, 02 Mar 2011 07:16:32 +0000
Add 60Hz timer tick patch from Andrew Warkentin <andreww591 gmail com>
... I have also attached a patch that adds the 60Hz timer interrupt (I'm not sure if it's totally correct, though, since the cursor blinks rather slowly).
Received-From: Andrew Warkentin <andreww591 gmail com>
Signed-Off-By: Philip Pemberton <philpem@philpem.me.uk>
1 #include <stdio.h>
2 #include <stdlib.h>
3 #include <stdint.h>
4 #include <stdbool.h>
5 #include <assert.h>
6 #include "musashi/m68k.h"
7 #include "state.h"
8 #include "memory.h"
10 /******************
11 * Memory mapping
12 ******************/
14 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
16 uint32_t mapAddr(uint32_t addr, bool writing)/*{{{*/
17 {
18 if (addr < 0x400000) {
19 // RAM access. Check against the Map RAM
20 // Start by getting the original page address
21 uint16_t page = (addr >> 12) & 0x3FF;
23 // Look it up in the map RAM and get the physical page address
24 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
26 // Update the Page Status bits
27 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
28 if (pagebits != 0) {
29 if (writing)
30 state.map[page*2] |= 0x60; // Page written to (dirty)
31 else
32 state.map[page*2] |= 0x40; // Page accessed but not written
33 }
35 // Return the address with the new physical page spliced in
36 return (new_page_addr << 12) + (addr & 0xFFF);
37 } else {
38 // I/O, VRAM or MapRAM space; no mapping is performed or required
39 // TODO: assert here?
40 return addr;
41 }
42 }/*}}}*/
44 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing)/*{{{*/
45 {
46 // Are we in Supervisor mode?
47 if (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000)
48 // Yes. We can do anything we like.
49 return MEM_ALLOWED;
51 // If we're here, then we must be in User mode.
52 // Check that the user didn't access memory outside of the RAM area
53 if (addr >= 0x400000)
54 return MEM_UIE;
56 // This leaves us with Page Fault checking. Get the page bits for this page.
57 uint16_t page = (addr >> 12) & 0x3FF;
58 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
60 // Check page is present
61 if ((pagebits & 0x03) == 0)
62 return MEM_PAGEFAULT;
64 // User attempt to access the kernel
65 // A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
66 if (((addr >> 19) & 0x0F) == 0)
67 return MEM_KERNEL;
69 // Check page is write enabled
70 if (writing && ((pagebits & 0x04) == 0))
71 return MEM_PAGE_NO_WE;
73 // Page access allowed.
74 return MEM_ALLOWED;
75 }/*}}}*/
77 #undef MAPRAM
80 /********************************************************
81 * m68k memory read/write support functions for Musashi
82 ********************************************************/
84 /**
85 * @brief Check memory access permissions for a write operation.
86 * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but
87 * gcc throws warnings when you have a return-with-value in a void
88 * function, even if the return-with-value is completely unreachable.
89 * Similarly it doesn't like it if you have a return without a value
90 * in a non-void function, even if it's impossible to ever reach the
91 * return-with-no-value. UGH!
92 */
93 /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
94 #define ACCESS_CHECK_WR(address, bits) \
95 do { \
96 bool fault = false; \
97 /* MEM_STATUS st; */ \
98 switch (checkMemoryAccess(address, true)) { \
99 case MEM_ALLOWED: \
100 /* Access allowed */ \
101 break; \
102 case MEM_PAGEFAULT: \
103 /* Page fault */ \
104 state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0); \
105 fault = true; \
106 break; \
107 case MEM_UIE: \
108 /* User access to memory above 4MB */ \
109 state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0); \
110 fault = true; \
111 break; \
112 case MEM_KERNEL: \
113 case MEM_PAGE_NO_WE: \
114 /* kernel access or page not write enabled */ \
115 /* FIXME: which regs need setting? */ \
116 fault = true; \
117 break; \
118 } \
119 \
120 if (fault) { \
121 if (bits >= 16) \
122 state.bsr0 = 0x7C00; \
123 else \
124 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
125 state.bsr0 |= (address >> 16); \
126 state.bsr1 = address & 0xffff; \
127 printf("ERR: BusError WR\n"); \
128 m68k_pulse_bus_error(); \
129 return; \
130 } \
131 } while (0)
132 /*}}}*/
134 /**
135 * @brief Check memory access permissions for a read operation.
136 * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but
137 * gcc throws warnings when you have a return-with-value in a void
138 * function, even if the return-with-value is completely unreachable.
139 * Similarly it doesn't like it if you have a return without a value
140 * in a non-void function, even if it's impossible to ever reach the
141 * return-with-no-value. UGH!
142 */
143 /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
144 #define ACCESS_CHECK_RD(address, bits) \
145 do { \
146 bool fault = false; \
147 /* MEM_STATUS st; */ \
148 switch (checkMemoryAccess(address, false)) { \
149 case MEM_ALLOWED: \
150 /* Access allowed */ \
151 break; \
152 case MEM_PAGEFAULT: \
153 /* Page fault */ \
154 state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0); \
155 fault = true; \
156 break; \
157 case MEM_UIE: \
158 /* User access to memory above 4MB */ \
159 state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0); \
160 fault = true; \
161 break; \
162 case MEM_KERNEL: \
163 case MEM_PAGE_NO_WE: \
164 /* kernel access or page not write enabled */ \
165 /* FIXME: which regs need setting? */ \
166 fault = true; \
167 break; \
168 } \
169 \
170 if (fault) { \
171 if (bits >= 16) \
172 state.bsr0 = 0x7C00; \
173 else \
174 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \
175 state.bsr0 |= (address >> 16); \
176 state.bsr1 = address & 0xffff; \
177 printf("ERR: BusError RD\n"); \
178 m68k_pulse_bus_error(); \
179 return 0xFFFFFFFF; \
180 } \
181 } while (0)
182 /*}}}*/
184 // Logging macros
185 #define LOG_NOT_HANDLED_R(bits) \
186 if (!handled) printf("unhandled read%02d, addr=0x%08X\n", bits, address);
188 #define LOG_NOT_HANDLED_W(bits) \
189 if (!handled) printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
191 /********************************************************
192 * I/O read/write functions
193 ********************************************************/
195 /**
196 * Issue a warning if a read operation is made with an invalid size
197 */
198 inline static void ENFORCE_SIZE(int bits, uint32_t address, bool read, int allowed, char *regname)
199 {
200 assert((bits == 8) || (bits == 16) || (bits == 32));
201 if ((bits & allowed) == 0) {
202 printf("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits);
203 }
204 }
206 inline static void ENFORCE_SIZE_R(int bits, uint32_t address, int allowed, char *regname)
207 {
208 ENFORCE_SIZE(bits, address, true, allowed, regname);
209 }
211 inline static void ENFORCE_SIZE_W(int bits, uint32_t address, int allowed, char *regname)
212 {
213 ENFORCE_SIZE(bits, address, false, allowed, regname);
214 }
216 void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/
217 {
218 bool handled = false;
220 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
221 // I/O register space, zone A
222 switch (address & 0x0F0000) {
223 case 0x010000: // General Status Register
224 if (bits == 16)
225 state.genstat = (data & 0xffff);
226 else if (bits == 8) {
227 if (address & 0)
228 state.genstat = data;
229 else
230 state.genstat = data << 8;
231 }
232 handled = true;
233 break;
234 case 0x030000: // Bus Status Register 0
235 break;
236 case 0x040000: // Bus Status Register 1
237 break;
238 case 0x050000: // Phone status
239 break;
240 case 0x060000: // DMA Count
241 ENFORCE_SIZE_W(bits, address, 16, "DMACOUNT");
242 state.dma_count = (data & 0x3FFF);
243 state.idmarw = ((data & 0x4000) == 0x4000);
244 state.dmaen = ((data & 0x8000) == 0x8000);
245 // This handles the "dummy DMA transfer" mentioned in the docs
246 // TODO: access check, peripheral access
247 if (!state.idmarw)
248 WR32(state.base_ram, mapAddr(address, true), state.base_ram_size - 1, 0xDEAD);
249 state.dma_count++;
250 handled = true;
251 break;
252 case 0x070000: // Line Printer Status Register
253 break;
254 case 0x080000: // Real Time Clock
255 break;
256 case 0x090000: // Phone registers
257 switch (address & 0x0FF000) {
258 case 0x090000: // Handset relay
259 case 0x098000:
260 break;
261 case 0x091000: // Line select 2
262 case 0x099000:
263 break;
264 case 0x092000: // Hook relay 1
265 case 0x09A000:
266 break;
267 case 0x093000: // Hook relay 2
268 case 0x09B000:
269 break;
270 case 0x094000: // Line 1 hold
271 case 0x09C000:
272 break;
273 case 0x095000: // Line 2 hold
274 case 0x09D000:
275 break;
276 case 0x096000: // Line 1 A-lead
277 case 0x09E000:
278 break;
279 case 0x097000: // Line 2 A-lead
280 case 0x09F000:
281 break;
282 }
283 break;
284 case 0x0A0000: // Miscellaneous Control Register
285 ENFORCE_SIZE_W(bits, address, 16, "MISCCON");
286 // TODO: handle the ctrl bits properly
287 // TODO: &0x8000 --> dismiss 60hz intr
288 if (data & 0x8000){
289 state.timer_enabled = 1;
290 }else{
291 state.timer_enabled = 0;
292 state.timer_asserted = 0;
293 }
294 state.dma_reading = (data & 0x4000);
295 if (state.leds != ((~data & 0xF00) >> 8)) {
296 state.leds = (~data & 0xF00) >> 8;
297 printf("LEDs: %s %s %s %s\n",
298 (state.leds & 8) ? "R" : "-",
299 (state.leds & 4) ? "G" : "-",
300 (state.leds & 2) ? "Y" : "-",
301 (state.leds & 1) ? "R" : "-");
302 }
303 handled = true;
304 break;
305 case 0x0B0000: // TM/DIALWR
306 break;
307 case 0x0C0000: // Clear Status Register
308 state.genstat = 0xFFFF;
309 state.bsr0 = 0xFFFF;
310 state.bsr1 = 0xFFFF;
311 handled = true;
312 break;
313 case 0x0D0000: // DMA Address Register
314 if (address & 0x004000) {
315 // A14 high -- set most significant bits
316 state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
317 } else {
318 // A14 low -- set least significant bits
319 state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
320 }
321 handled = true;
322 break;
323 case 0x0E0000: // Disk Control Register
324 ENFORCE_SIZE_W(bits, address, 16, "DISKCON");
325 // B7 = FDD controller reset
326 if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
327 // B6 = drive 0 select -- TODO
328 // B5 = motor enable -- TODO
329 // B4 = HDD controller reset -- TODO
330 // B3 = HDD0 select -- TODO
331 // B2,1,0 = HDD0 head select
332 handled = true;
333 break;
334 case 0x0F0000: // Line Printer Data Register
335 break;
336 }
337 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
338 // I/O register space, zone B
339 switch (address & 0xF00000) {
340 case 0xC00000: // Expansion slots
341 case 0xD00000:
342 switch (address & 0xFC0000) {
343 case 0xC00000: // Expansion slot 0
344 case 0xC40000: // Expansion slot 1
345 case 0xC80000: // Expansion slot 2
346 case 0xCC0000: // Expansion slot 3
347 case 0xD00000: // Expansion slot 4
348 case 0xD40000: // Expansion slot 5
349 case 0xD80000: // Expansion slot 6
350 case 0xDC0000: // Expansion slot 7
351 fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data);
352 handled = true;
353 break;
354 }
355 break;
356 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
357 case 0xF00000:
358 switch (address & 0x070000) {
359 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
360 break;
361 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
362 ENFORCE_SIZE_W(bits, address, 16, "FDC REGISTERS");
363 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data);
364 handled = true;
365 break;
366 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
367 break;
368 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
369 break;
370 case 0x040000: // [ef][4c]xxxx ==> General Control Register
371 switch (address & 0x077000) {
372 case 0x040000: // [ef][4c][08]xxx ==> EE
373 break;
374 case 0x041000: // [ef][4c][19]xxx ==> PIE
375 ENFORCE_SIZE_W(bits, address, 16, "PIE");
376 state.pie = ((data & 0x8000) == 0x8000);
377 handled = true;
378 break;
379 case 0x042000: // [ef][4c][2A]xxx ==> BP
380 break;
381 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
382 ENFORCE_SIZE_W(bits, address, 16, "ROMLMAP");
383 state.romlmap = ((data & 0x8000) == 0x8000);
384 handled = true;
385 break;
386 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
387 ENFORCE_SIZE_W(bits, address, 16, "L1 MODEM");
388 break;
389 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
390 ENFORCE_SIZE_W(bits, address, 16, "L2 MODEM");
391 break;
392 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
393 ENFORCE_SIZE_W(bits, address, 16, "D/N CONNECT");
394 break;
395 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
396 ENFORCE_SIZE_W(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO");
397 break;
398 }
399 case 0x050000: // [ef][5d]xxxx ==> 8274
400 break;
401 case 0x060000: // [ef][6e]xxxx ==> Control regs
402 switch (address & 0x07F000) {
403 default:
404 break;
405 }
406 break;
407 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
408 // TODO: figure out which sizes are valid (probably just 8 and 16)
409 // ENFORCE_SIZE_W(bits, address, 16, "KEYBOARD CONTROLLER");
410 if (bits == 8) {
411 printf("KBD WR %02X => %02X\n", (address >> 1) & 3, data);
412 keyboard_write(&state.kbd, (address >> 1) & 3, data);
413 handled = true;
414 } else if (bits == 16) {
415 printf("KBD WR %02X => %04X\n", (address >> 1) & 3, data);
416 keyboard_write(&state.kbd, (address >> 1) & 3, data >> 8);
417 handled = true;
418 }
419 break;
420 }
421 }
422 }
424 LOG_NOT_HANDLED_W(bits);
425 }/*}}}*/
427 uint32_t IoRead(uint32_t address, int bits)/*{{{*/
428 {
429 bool handled = false;
430 uint32_t data = 0xFFFFFFFF;
432 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
433 // I/O register space, zone A
434 switch (address & 0x0F0000) {
435 case 0x010000: // General Status Register
436 ENFORCE_SIZE_R(bits, address, 16, "GENSTAT");
437 return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
438 break;
439 case 0x030000: // Bus Status Register 0
440 ENFORCE_SIZE_R(bits, address, 16, "BSR0");
441 return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
442 break;
443 case 0x040000: // Bus Status Register 1
444 ENFORCE_SIZE_R(bits, address, 16, "BSR1");
445 return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
446 break;
447 case 0x050000: // Phone status
448 ENFORCE_SIZE_R(bits, address, 8 | 16, "PHONE STATUS");
449 break;
450 case 0x060000: // DMA Count
451 // TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
452 // Bit 14 is always unused, so leave it set
453 ENFORCE_SIZE_R(bits, address, 16, "DMACOUNT");
454 return (state.dma_count & 0x3fff) | 0xC000;
455 break;
456 case 0x070000: // Line Printer Status Register
457 data = 0x00120012; // no parity error, no line printer error, no irqs from FDD or HDD
458 data |= wd2797_get_irq(&state.fdc_ctx) ? 0x00080008 : 0;
459 return data;
460 break;
461 case 0x080000: // Real Time Clock
462 printf("READ NOTIMP: Realtime Clock\n");
463 break;
464 case 0x090000: // Phone registers
465 switch (address & 0x0FF000) {
466 case 0x090000: // Handset relay
467 case 0x098000:
468 break;
469 case 0x091000: // Line select 2
470 case 0x099000:
471 break;
472 case 0x092000: // Hook relay 1
473 case 0x09A000:
474 break;
475 case 0x093000: // Hook relay 2
476 case 0x09B000:
477 break;
478 case 0x094000: // Line 1 hold
479 case 0x09C000:
480 break;
481 case 0x095000: // Line 2 hold
482 case 0x09D000:
483 break;
484 case 0x096000: // Line 1 A-lead
485 case 0x09E000:
486 break;
487 case 0x097000: // Line 2 A-lead
488 case 0x09F000:
489 break;
490 }
491 break;
492 case 0x0A0000: // Miscellaneous Control Register -- write only!
493 handled = true;
494 break;
495 case 0x0B0000: // TM/DIALWR
496 break;
497 case 0x0C0000: // Clear Status Register -- write only!
498 handled = true;
499 break;
500 case 0x0D0000: // DMA Address Register
501 break;
502 case 0x0E0000: // Disk Control Register
503 break;
504 case 0x0F0000: // Line Printer Data Register
505 break;
506 }
507 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
508 // I/O register space, zone B
509 switch (address & 0xF00000) {
510 case 0xC00000: // Expansion slots
511 case 0xD00000:
512 switch (address & 0xFC0000) {
513 case 0xC00000: // Expansion slot 0
514 case 0xC40000: // Expansion slot 1
515 case 0xC80000: // Expansion slot 2
516 case 0xCC0000: // Expansion slot 3
517 case 0xD00000: // Expansion slot 4
518 case 0xD40000: // Expansion slot 5
519 case 0xD80000: // Expansion slot 6
520 case 0xDC0000: // Expansion slot 7
521 fprintf(stderr, "NOTE: RD%d from expansion card space, addr=0x%08X\n", bits, address);
522 handled = true;
523 break;
524 }
525 break;
526 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
527 case 0xF00000:
528 switch (address & 0x070000) {
529 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
530 break;
531 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
532 ENFORCE_SIZE_R(bits, address, 16, "FDC REGISTERS");
533 return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
534 break;
535 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
536 break;
537 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
538 break;
539 case 0x040000: // [ef][4c]xxxx ==> General Control Register
540 switch (address & 0x077000) {
541 case 0x040000: // [ef][4c][08]xxx ==> EE
542 case 0x041000: // [ef][4c][19]xxx ==> PIE
543 case 0x042000: // [ef][4c][2A]xxx ==> BP
544 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
545 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
546 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
547 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
548 // All write-only registers... TODO: bus error?
549 handled = true;
550 break;
551 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
552 break;
553 }
554 break;
555 case 0x050000: // [ef][5d]xxxx ==> 8274
556 break;
557 case 0x060000: // [ef][6e]xxxx ==> Control regs
558 switch (address & 0x07F000) {
559 default:
560 break;
561 }
562 break;
563 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
564 // TODO: figure out which sizes are valid (probably just 8 and 16)
565 //ENFORCE_SIZE_R(bits, address, 16, "KEYBOARD CONTROLLER");
566 {
567 if (bits == 8) {
568 return keyboard_read(&state.kbd, (address >> 1) & 3);
569 } else {
570 return keyboard_read(&state.kbd, (address >> 1) & 3) << 8;
571 }
572 return data;
573 }
574 break;
575 }
576 }
577 }
579 LOG_NOT_HANDLED_R(bits);
581 return data;
582 }/*}}}*/
585 /********************************************************
586 * m68k memory read/write support functions for Musashi
587 ********************************************************/
589 /**
590 * @brief Read M68K memory, 32-bit
591 */
592 uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/
593 {
594 uint32_t data = 0xFFFFFFFF;
596 // If ROMLMAP is set, force system to access ROM
597 if (!state.romlmap)
598 address |= 0x800000;
600 // Check access permissions
601 ACCESS_CHECK_RD(address, 32);
603 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
604 // ROM access
605 return RD32(state.rom, address, ROM_SIZE - 1);
606 } else if (address <= 0x3fffff) {
607 // RAM access
608 uint32_t newAddr = mapAddr(address, false);
609 if (newAddr <= 0x1fffff) {
610 return RD32(state.base_ram, newAddr, state.base_ram_size - 1);
611 } else {
612 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
613 return RD32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
614 else
615 return 0xffffffff;
616 }
617 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
618 // I/O register space, zone A
619 switch (address & 0x0F0000) {
620 case 0x000000: // Map RAM access
621 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
622 return RD32(state.map, address, 0x7FF);
623 break;
624 case 0x020000: // Video RAM
625 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
626 return RD32(state.vram, address, 0x7FFF);
627 break;
628 default:
629 return IoRead(address, 32);
630 }
631 } else {
632 return IoRead(address, 32);
633 }
635 return data;
636 }/*}}}*/
638 /**
639 * @brief Read M68K memory, 16-bit
640 */
641 uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/
642 {
643 uint16_t data = 0xFFFF;
645 // If ROMLMAP is set, force system to access ROM
646 if (!state.romlmap)
647 address |= 0x800000;
649 // Check access permissions
650 ACCESS_CHECK_RD(address, 16);
652 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
653 // ROM access
654 data = RD16(state.rom, address, ROM_SIZE - 1);
655 } else if (address <= 0x3fffff) {
656 // RAM access
657 uint32_t newAddr = mapAddr(address, false);
658 if (newAddr <= 0x1fffff) {
659 return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
660 } else {
661 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
662 return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
663 else
664 return 0xffff;
665 }
666 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
667 // I/O register space, zone A
668 switch (address & 0x0F0000) {
669 case 0x000000: // Map RAM access
670 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
671 data = RD16(state.map, address, 0x7FF);
672 break;
673 case 0x020000: // Video RAM
674 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
675 data = RD16(state.vram, address, 0x7FFF);
676 break;
677 default:
678 data = IoRead(address, 16);
679 }
680 } else {
681 data = IoRead(address, 16);
682 }
684 return data;
685 }/*}}}*/
687 /**
688 * @brief Read M68K memory, 8-bit
689 */
690 uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/
691 {
692 uint8_t data = 0xFF;
694 // If ROMLMAP is set, force system to access ROM
695 if (!state.romlmap)
696 address |= 0x800000;
698 // Check access permissions
699 ACCESS_CHECK_RD(address, 8);
701 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
702 // ROM access
703 data = RD8(state.rom, address, ROM_SIZE - 1);
704 } else if (address <= 0x3fffff) {
705 // RAM access
706 uint32_t newAddr = mapAddr(address, false);
707 if (newAddr <= 0x1fffff) {
708 return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
709 } else {
710 if (newAddr <= (state.exp_ram_size + 0x200000 - 1))
711 return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
712 else
713 return 0xff;
714 }
715 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
716 // I/O register space, zone A
717 switch (address & 0x0F0000) {
718 case 0x000000: // Map RAM access
719 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
720 data = RD8(state.map, address, 0x7FF);
721 break;
722 case 0x020000: // Video RAM
723 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
724 data = RD8(state.vram, address, 0x7FFF);
725 break;
726 default:
727 data = IoRead(address, 8);
728 }
729 } else {
730 data = IoRead(address, 8);
731 }
733 return data;
734 }/*}}}*/
736 /**
737 * @brief Write M68K memory, 32-bit
738 */
739 void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/
740 {
741 // If ROMLMAP is set, force system to access ROM
742 if (!state.romlmap)
743 address |= 0x800000;
745 // Check access permissions
746 ACCESS_CHECK_WR(address, 32);
748 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
749 // ROM access
750 } else if (address <= 0x3FFFFF) {
751 // RAM access
752 uint32_t newAddr = mapAddr(address, true);
753 if (newAddr <= 0x1fffff)
754 WR32(state.base_ram, newAddr, state.base_ram_size - 1, value);
755 else
756 WR32(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
757 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
758 // I/O register space, zone A
759 switch (address & 0x0F0000) {
760 case 0x000000: // Map RAM access
761 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
762 WR32(state.map, address, 0x7FF, value);
763 break;
764 case 0x020000: // Video RAM
765 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
766 WR32(state.vram, address, 0x7FFF, value);
767 break;
768 default:
769 IoWrite(address, value, 32);
770 }
771 } else {
772 IoWrite(address, value, 32);
773 }
774 }/*}}}*/
776 /**
777 * @brief Write M68K memory, 16-bit
778 */
779 void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/
780 {
781 // If ROMLMAP is set, force system to access ROM
782 if (!state.romlmap)
783 address |= 0x800000;
785 // Check access permissions
786 ACCESS_CHECK_WR(address, 16);
788 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
789 // ROM access
790 } else if (address <= 0x3FFFFF) {
791 // RAM access
792 uint32_t newAddr = mapAddr(address, true);
793 if (newAddr <= 0x1fffff)
794 WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
795 else
796 WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
797 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
798 // I/O register space, zone A
799 switch (address & 0x0F0000) {
800 case 0x000000: // Map RAM access
801 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
802 WR16(state.map, address, 0x7FF, value);
803 break;
804 case 0x020000: // Video RAM
805 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
806 WR16(state.vram, address, 0x7FFF, value);
807 break;
808 default:
809 IoWrite(address, value, 16);
810 }
811 } else {
812 IoWrite(address, value, 16);
813 }
814 }/*}}}*/
816 /**
817 * @brief Write M68K memory, 8-bit
818 */
819 void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/
820 {
821 // If ROMLMAP is set, force system to access ROM
822 if (!state.romlmap)
823 address |= 0x800000;
825 // Check access permissions
826 ACCESS_CHECK_WR(address, 8);
828 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
829 // ROM access (read only!)
830 } else if (address <= 0x3FFFFF) {
831 // RAM access
832 uint32_t newAddr = mapAddr(address, true);
833 if (newAddr <= 0x1fffff)
834 WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
835 else
836 WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
837 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
838 // I/O register space, zone A
839 switch (address & 0x0F0000) {
840 case 0x000000: // Map RAM access
841 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
842 WR8(state.map, address, 0x7FF, value);
843 break;
844 case 0x020000: // Video RAM
845 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
846 WR8(state.vram, address, 0x7FFF, value);
847 break;
848 default:
849 IoWrite(address, value, 8);
850 }
851 } else {
852 IoWrite(address, value, 8);
853 }
854 }/*}}}*/
857 // for the disassembler
858 uint32_t m68k_read_disassembler_32(uint32_t addr) { return m68k_read_memory_32(addr); }
859 uint32_t m68k_read_disassembler_16(uint32_t addr) { return m68k_read_memory_16(addr); }
860 uint32_t m68k_read_disassembler_8 (uint32_t addr) { return m68k_read_memory_8 (addr); }