Tue, 15 Nov 2011 10:12:37 +0000
[musashi] Fix handling of bus errors
Patch-Author: Andrew Warkentin <andreww591!gmail>
Patch-MessageID: <4EC200CE.2020304@gmail.com>
I have fixed the first page fault test failure in FreeBee (the page fault test now hangs rather than errors out, because it is trying to read from the hard drive to test DMA page faults).
There were actually two bugs (the first bug was masking the second one).
First, the ancient version of Musashi that you used is unable to properly resume from bus errors that happen in the middle of certain instructions (some instructions are fetched in stages, with the PC being advanced to each part of the instruction, so basically what happens is the CPU core attempts to read the memory location referenced by the first operand, the bus error occurs, causing the PC to jump to the exception vector, but the faulting instruction is still in the middle of being fetched, so the PC is then advanced past the beginning of the exception handler). I fixed this by delaying the jump to the bus error vector until after the faulting instruction finishes.
The second bug is simpler - you had the UDS and LDS bits in BSR0 inverted (they are supposed to be active low).
1 #ifndef _MEMORY_H
2 #define _MEMORY_H
4 /***********************************
5 * Array read/write utility macros
6 * "Don't Repeat Yourself" :)
7 ***********************************/
9 /// Array read, 32-bit
10 #define RD32(array, address, andmask) \
11 (((uint32_t)array[(address + 0) & (andmask)] << 24) | \
12 ((uint32_t)array[(address + 1) & (andmask)] << 16) | \
13 ((uint32_t)array[(address + 2) & (andmask)] << 8) | \
14 ((uint32_t)array[(address + 3) & (andmask)]))
16 /// Array read, 16-bit
17 #define RD16(array, address, andmask) \
18 (((uint32_t)array[(address + 0) & (andmask)] << 8) | \
19 ((uint32_t)array[(address + 1) & (andmask)]))
21 /// Array read, 8-bit
22 #define RD8(array, address, andmask) \
23 ((uint32_t)array[(address + 0) & (andmask)])
25 /// Array write, 32-bit
26 #define WR32(array, address, andmask, value) do { \
27 array[(address + 0) & (andmask)] = (value >> 24) & 0xff; \
28 array[(address + 1) & (andmask)] = (value >> 16) & 0xff; \
29 array[(address + 2) & (andmask)] = (value >> 8) & 0xff; \
30 array[(address + 3) & (andmask)] = value & 0xff; \
31 } while (0)
33 /// Array write, 16-bit
34 #define WR16(array, address, andmask, value) do { \
35 array[(address + 0) & (andmask)] = (value >> 8) & 0xff; \
36 array[(address + 1) & (andmask)] = value & 0xff; \
37 } while (0)
39 /// Array write, 8-bit
40 #define WR8(array, address, andmask, value) do { \
41 array[(address + 0) & (andmask)] = value & 0xff; \
42 } while (0)
44 /******************
45 * Memory mapping
46 ******************/
48 typedef enum {
49 MEM_ALLOWED = 0,
50 MEM_PAGEFAULT, // Page fault -- page not present
51 MEM_PAGE_NO_WE, // Page not write enabled
52 MEM_KERNEL, // User attempted to access kernel memory
53 MEM_UIE // User Nonmemory Location Access
54 } MEM_STATUS;
56 /**
57 * @brief Check memory access permissions for a given address.
58 * @param addr Address.
59 * @param writing true if writing to memory, false if reading.
60 * @return One of the MEM_STATUS constants, specifying whether the access is
61 * permitted, or what error occurred.
62 */
63 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing);
65 /**
66 * @brief Map a CPU memory address into physical memory space.
67 * @param addr Address.
68 * @param writing true if writing to memory, false if reading.
69 * @return Address, remapped into physical memory.
70 */
71 uint32_t mapAddr(uint32_t addr, bool writing);
73 #endif