Wed, 16 Jan 2013 00:34:11 +0000
[wd2010] use size_t for init filesize, make disc init more verbose
1 /* ======================================================================== */
2 /* ========================= LICENSING & COPYRIGHT ======================== */
3 /* ======================================================================== */
4 /*
5 * MUSASHI
6 * Version 3.3
7 *
8 * A portable Motorola M680x0 processor emulation engine.
9 * Copyright 1998-2001 Karl Stenerud. All rights reserved.
10 *
11 * This code may be freely used for non-commercial purposes as long as this
12 * copyright notice remains unaltered in the source code and any binary files
13 * containing this code in compiled form.
14 *
15 * All other lisencing terms must be negotiated with the author
16 * (Karl Stenerud).
17 *
18 * The latest version of this code can be obtained at:
19 * http://kstenerud.cjb.net
20 */
24 /* Input file for m68kmake
25 * -----------------------
26 *
27 * All sections begin with 80 X's in a row followed by an end-of-line
28 * sequence.
29 * After this, m68kmake will expect to find one of the following section
30 * identifiers:
31 * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes
32 * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes
33 * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable
34 * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable
35 * M68KMAKE_TABLE_BODY - the table itself
36 * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation
37 * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation
38 * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation
39 *
40 * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and
41 * M68KMAKE_TABLE_BODY must be second last in the file.
42 *
43 * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler
44 * primitives themselves. Each opcode handler begins with:
45 * M68KMAKE_OP(A, B, C, D)
46 *
47 * where A is the opcode handler name, B is the size of the operation,
48 * C denotes any special processing mode, and D denotes a specific
49 * addressing mode.
50 * For C and D where nothing is specified, use "."
51 *
52 * Example:
53 * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA
54 * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7
55 * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing
56 *
57 * All opcode handler primitives end with a closing curly brace "}" at column 1
58 *
59 * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler,
60 * and do not put a closing curly brace at column 1 unless it is
61 * marking the end of the handler!
62 *
63 * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx,
64 * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple
65 * opcode handlers to handle variations in the opcode handler.
66 * Note: M68KMAKE_CC will only be interpreted in condition code opcodes.
67 * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only
68 * be interpreted on instructions where the corresponding table entry
69 * specifies multiple effective addressing modes.
70 * Example:
71 * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4
72 *
73 * This table entry says that the clr.l opcde has 7 variations (A+-DXWL).
74 * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for
75 * 68000, 6 cycles for 68010, and 4 cycles for 68020.
76 */
78 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
79 M68KMAKE_PROTOTYPE_HEADER
81 #ifndef M68KOPS__HEADER
82 #define M68KOPS__HEADER
84 /* ======================================================================== */
85 /* ============================ OPCODE HANDLERS =========================== */
86 /* ======================================================================== */
90 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
91 M68KMAKE_PROTOTYPE_FOOTER
94 /* Build the opcode handler table */
95 void m68ki_build_opcode_table(void);
97 extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
98 extern unsigned char m68ki_cycles[][0x10000];
101 /* ======================================================================== */
102 /* ============================== END OF FILE ============================= */
103 /* ======================================================================== */
105 #endif /* M68KOPS__HEADER */
109 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
110 M68KMAKE_TABLE_HEADER
112 /* ======================================================================== */
113 /* ========================= OPCODE TABLE BUILDER ========================= */
114 /* ======================================================================== */
116 #include "m68kops.h"
118 #define NUM_CPU_TYPES 3
120 void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
121 unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */
123 /* This is used to generate the opcode handler jump table */
124 typedef struct
125 {
126 void (*opcode_handler)(void); /* handler function */
127 unsigned int mask; /* mask on opcode */
128 unsigned int match; /* what to match after masking */
129 unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */
130 } opcode_handler_struct;
133 /* Opcode handler table */
134 static opcode_handler_struct m68k_opcode_handler_table[] =
135 {
136 /* function mask match 000 010 020 */
140 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
141 M68KMAKE_TABLE_FOOTER
143 {0, 0, 0, {0, 0, 0}}
144 };
147 /* Build the opcode handler jump table */
148 void m68ki_build_opcode_table(void)
149 {
150 opcode_handler_struct *ostruct;
151 int instr;
152 int i;
153 int j;
154 int k;
156 for(i = 0; i < 0x10000; i++)
157 {
158 /* default to illegal */
159 m68ki_instruction_jump_table[i] = m68k_op_illegal;
160 for(k=0;k<NUM_CPU_TYPES;k++)
161 m68ki_cycles[k][i] = 0;
162 }
164 ostruct = m68k_opcode_handler_table;
165 while(ostruct->mask != 0xff00)
166 {
167 for(i = 0;i < 0x10000;i++)
168 {
169 if((i & ostruct->mask) == ostruct->match)
170 {
171 m68ki_instruction_jump_table[i] = ostruct->opcode_handler;
172 for(k=0;k<NUM_CPU_TYPES;k++)
173 m68ki_cycles[k][i] = ostruct->cycles[k];
174 }
175 }
176 ostruct++;
177 }
178 while(ostruct->mask == 0xff00)
179 {
180 for(i = 0;i <= 0xff;i++)
181 {
182 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
183 for(k=0;k<NUM_CPU_TYPES;k++)
184 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
185 }
186 ostruct++;
187 }
188 while(ostruct->mask == 0xf1f8)
189 {
190 for(i = 0;i < 8;i++)
191 {
192 for(j = 0;j < 8;j++)
193 {
194 instr = ostruct->match | (i << 9) | j;
195 m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;
196 for(k=0;k<NUM_CPU_TYPES;k++)
197 m68ki_cycles[k][instr] = ostruct->cycles[k];
198 if((instr & 0xf000) == 0xe000 && (!(instr & 0x20)))
199 m68ki_cycles[0][instr] = m68ki_cycles[1][instr] = ostruct->cycles[k] + ((((j-1)&7)+1)<<1);
200 }
201 }
202 ostruct++;
203 }
204 while(ostruct->mask == 0xfff0)
205 {
206 for(i = 0;i <= 0x0f;i++)
207 {
208 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
209 for(k=0;k<NUM_CPU_TYPES;k++)
210 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
211 }
212 ostruct++;
213 }
214 while(ostruct->mask == 0xf1ff)
215 {
216 for(i = 0;i <= 0x07;i++)
217 {
218 m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;
219 for(k=0;k<NUM_CPU_TYPES;k++)
220 m68ki_cycles[k][ostruct->match | (i << 9)] = ostruct->cycles[k];
221 }
222 ostruct++;
223 }
224 while(ostruct->mask == 0xfff8)
225 {
226 for(i = 0;i <= 0x07;i++)
227 {
228 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
229 for(k=0;k<NUM_CPU_TYPES;k++)
230 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
231 }
232 ostruct++;
233 }
234 while(ostruct->mask == 0xffff)
235 {
236 m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;
237 for(k=0;k<NUM_CPU_TYPES;k++)
238 m68ki_cycles[k][ostruct->match] = ostruct->cycles[k];
239 ostruct++;
240 }
241 }
244 /* ======================================================================== */
245 /* ============================== END OF FILE ============================= */
246 /* ======================================================================== */
250 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
251 M68KMAKE_OPCODE_HANDLER_HEADER
253 #include "m68kcpu.h"
255 /* ======================================================================== */
256 /* ========================= INSTRUCTION HANDLERS ========================= */
257 /* ======================================================================== */
261 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
262 M68KMAKE_OPCODE_HANDLER_FOOTER
264 /* ======================================================================== */
265 /* ============================== END OF FILE ============================= */
266 /* ======================================================================== */
270 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
271 M68KMAKE_TABLE_BODY
273 The following table is arranged as follows:
275 name: Opcode mnemonic
277 size: Operation size
279 spec proc: Special processing mode:
280 .: normal
281 s: static operand
282 r: register operand
283 rr: register to register
284 mm: memory to memory
285 er: effective address to register
286 re: register to effective address
287 dd: data register to data register
288 da: data register to address register
289 aa: address register to address register
290 cr: control register to register
291 rc: register to control register
292 toc: to condition code register
293 tos: to status register
294 tou: to user stack pointer
295 frc: from condition code register
296 frs: from status register
297 fru: from user stack pointer
298 * for move.x, the special processing mode is a specific
299 destination effective addressing mode.
301 spec ea: Specific effective addressing mode:
302 .: normal
303 i: immediate
304 d: data register
305 a: address register
306 ai: address register indirect
307 pi: address register indirect with postincrement
308 pd: address register indirect with predecrement
309 di: address register indirect with displacement
310 ix: address register indirect with index
311 aw: absolute word address
312 al: absolute long address
313 pcdi: program counter relative with displacement
314 pcix: program counter relative with index
315 a7: register specified in instruction is A7
316 ax7: register field X of instruction is A7
317 ay7: register field Y of instruction is A7
318 axy7: register fields X and Y of instruction are A7
320 bit pattern: Pattern to recognize this opcode. "." means don't care.
322 allowed ea: List of allowed addressing modes:
323 .: not present
324 A: address register indirect
325 +: ARI (address register indirect) with postincrement
326 -: ARI with predecrement
327 D: ARI with displacement
328 X: ARI with index
329 W: absolute word address
330 L: absolute long address
331 d: program counter indirect with displacement
332 x: program counter indirect with index
333 I: immediate
334 mode: CPU operating mode for each cpu type. U = user or supervisor,
335 S = supervisor only, "." = opcode not present.
337 cpu cycles: Base number of cycles required to execute this opcode on the
338 specified CPU type.
339 Use "." if CPU does not have this opcode.
343 spec spec allowed ea mode cpu cycles
344 name size proc ea bit pattern A+-DXWLdxI 0 1 2 000 010 020 comments
345 ====== ==== ==== ==== ================ ========== = = = === === === =============
346 M68KMAKE_TABLE_START
347 1010 0 . . 1010............ .......... U U U 4 4 4
348 1111 0 . . 1111............ .......... U U U 4 4 4
349 abcd 8 rr . 1100...100000... .......... U U U 6 6 4
350 abcd 8 mm ax7 1100111100001... .......... U U U 18 18 16
351 abcd 8 mm ay7 1100...100001111 .......... U U U 18 18 16
352 abcd 8 mm axy7 1100111100001111 .......... U U U 18 18 16
353 abcd 8 mm . 1100...100001... .......... U U U 18 18 16
354 add 8 er d 1101...000000... .......... U U U 4 4 2
355 add 8 er . 1101...000...... A+-DXWLdxI U U U 4 4 2
356 add 16 er d 1101...001000... .......... U U U 4 4 2
357 add 16 er a 1101...001001... .......... U U U 4 4 2
358 add 16 er . 1101...001...... A+-DXWLdxI U U U 4 4 2
359 add 32 er d 1101...010000... .......... U U U 6 6 2
360 add 32 er a 1101...010001... .......... U U U 6 6 2
361 add 32 er . 1101...010...... A+-DXWLdxI U U U 6 6 2
362 add 8 re . 1101...100...... A+-DXWL... U U U 8 8 4
363 add 16 re . 1101...101...... A+-DXWL... U U U 8 8 4
364 add 32 re . 1101...110...... A+-DXWL... U U U 12 12 4
365 adda 16 . d 1101...011000... .......... U U U 8 8 2
366 adda 16 . a 1101...011001... .......... U U U 8 8 2
367 adda 16 . . 1101...011...... A+-DXWLdxI U U U 8 8 2
368 adda 32 . d 1101...111000... .......... U U U 6 6 2
369 adda 32 . a 1101...111001... .......... U U U 6 6 2
370 adda 32 . . 1101...111...... A+-DXWLdxI U U U 6 6 2
371 addi 8 . d 0000011000000... .......... U U U 8 8 2
372 addi 8 . . 0000011000...... A+-DXWL... U U U 12 12 4
373 addi 16 . d 0000011001000... .......... U U U 8 8 2
374 addi 16 . . 0000011001...... A+-DXWL... U U U 12 12 4
375 addi 32 . d 0000011010000... .......... U U U 16 14 2
376 addi 32 . . 0000011010...... A+-DXWL... U U U 20 20 4
377 addq 8 . d 0101...000000... .......... U U U 4 4 2
378 addq 8 . . 0101...000...... A+-DXWL... U U U 8 8 4
379 addq 16 . d 0101...001000... .......... U U U 4 4 2
380 addq 16 . a 0101...001001... .......... U U U 4 4 2
381 addq 16 . . 0101...001...... A+-DXWL... U U U 8 8 4
382 addq 32 . d 0101...010000... .......... U U U 8 8 2
383 addq 32 . a 0101...010001... .......... U U U 8 8 2
384 addq 32 . . 0101...010...... A+-DXWL... U U U 12 12 4
385 addx 8 rr . 1101...100000... .......... U U U 4 4 2
386 addx 16 rr . 1101...101000... .......... U U U 4 4 2
387 addx 32 rr . 1101...110000... .......... U U U 8 6 2
388 addx 8 mm ax7 1101111100001... .......... U U U 18 18 12
389 addx 8 mm ay7 1101...100001111 .......... U U U 18 18 12
390 addx 8 mm axy7 1101111100001111 .......... U U U 18 18 12
391 addx 8 mm . 1101...100001... .......... U U U 18 18 12
392 addx 16 mm . 1101...101001... .......... U U U 18 18 12
393 addx 32 mm . 1101...110001... .......... U U U 30 30 12
394 and 8 er d 1100...000000... .......... U U U 4 4 2
395 and 8 er . 1100...000...... A+-DXWLdxI U U U 4 4 2
396 and 16 er d 1100...001000... .......... U U U 4 4 2
397 and 16 er . 1100...001...... A+-DXWLdxI U U U 4 4 2
398 and 32 er d 1100...010000... .......... U U U 6 6 2
399 and 32 er . 1100...010...... A+-DXWLdxI U U U 6 6 2
400 and 8 re . 1100...100...... A+-DXWL... U U U 8 8 4
401 and 16 re . 1100...101...... A+-DXWL... U U U 8 8 4
402 and 32 re . 1100...110...... A+-DXWL... U U U 12 12 4
403 andi 16 toc . 0000001000111100 .......... U U U 20 16 12
404 andi 16 tos . 0000001001111100 .......... S S S 20 16 12
405 andi 8 . d 0000001000000... .......... U U U 8 8 2
406 andi 8 . . 0000001000...... A+-DXWL... U U U 12 12 4
407 andi 16 . d 0000001001000... .......... U U U 8 8 2
408 andi 16 . . 0000001001...... A+-DXWL... U U U 12 12 4
409 andi 32 . d 0000001010000... .......... U U U 14 14 2
410 andi 32 . . 0000001010...... A+-DXWL... U U U 20 20 4
411 asr 8 s . 1110...000000... .......... U U U 6 6 6
412 asr 16 s . 1110...001000... .......... U U U 6 6 6
413 asr 32 s . 1110...010000... .......... U U U 8 8 6
414 asr 8 r . 1110...000100... .......... U U U 6 6 6
415 asr 16 r . 1110...001100... .......... U U U 6 6 6
416 asr 32 r . 1110...010100... .......... U U U 8 8 6
417 asr 16 . . 1110000011...... A+-DXWL... U U U 8 8 5
418 asl 8 s . 1110...100000... .......... U U U 6 6 8
419 asl 16 s . 1110...101000... .......... U U U 6 6 8
420 asl 32 s . 1110...110000... .......... U U U 8 8 8
421 asl 8 r . 1110...100100... .......... U U U 6 6 8
422 asl 16 r . 1110...101100... .......... U U U 6 6 8
423 asl 32 r . 1110...110100... .......... U U U 8 8 8
424 asl 16 . . 1110000111...... A+-DXWL... U U U 8 8 6
425 bcc 8 . . 0110............ .......... U U U 8 8 6
426 bcc 16 . . 0110....00000000 .......... U U U 10 10 6
427 bcc 32 . . 0110....11111111 .......... . . U . . 6
428 bchg 8 r . 0000...101...... A+-DXWL... U U U 8 8 4
429 bchg 32 r d 0000...101000... .......... U U U 8 8 4
430 bchg 8 s . 0000100001...... A+-DXWL... U U U 12 12 4
431 bchg 32 s d 0000100001000... .......... U U U 12 12 4
432 bclr 8 r . 0000...110...... A+-DXWL... U U U 8 10 4
433 bclr 32 r d 0000...110000... .......... U U U 10 10 4
434 bclr 8 s . 0000100010...... A+-DXWL... U U U 12 12 4
435 bclr 32 s d 0000100010000... .......... U U U 14 14 4
436 bfchg 32 . d 1110101011000... .......... . . U . . 12 timing not quite correct
437 bfchg 32 . . 1110101011...... A..DXWL... . . U . . 20
438 bfclr 32 . d 1110110011000... .......... . . U . . 12
439 bfclr 32 . . 1110110011...... A..DXWL... . . U . . 20
440 bfexts 32 . d 1110101111000... .......... . . U . . 8
441 bfexts 32 . . 1110101111...... A..DXWLdx. . . U . . 15
442 bfextu 32 . d 1110100111000... .......... . . U . . 8
443 bfextu 32 . . 1110100111...... A..DXWLdx. . . U . . 15
444 bfffo 32 . d 1110110111000... .......... . . U . . 18
445 bfffo 32 . . 1110110111...... A..DXWLdx. . . U . . 28
446 bfins 32 . d 1110111111000... .......... . . U . . 10
447 bfins 32 . . 1110111111...... A..DXWL... . . U . . 17
448 bfset 32 . d 1110111011000... .......... . . U . . 12
449 bfset 32 . . 1110111011...... A..DXWL... . . U . . 20
450 bftst 32 . d 1110100011000... .......... . . U . . 6
451 bftst 32 . . 1110100011...... A..DXWLdx. . . U . . 13
452 bkpt 0 . . 0100100001001... .......... . U U . 10 10
453 bra 8 . . 01100000........ .......... U U U 10 10 10
454 bra 16 . . 0110000000000000 .......... U U U 10 10 10
455 bra 32 . . 0110000011111111 .......... U U U . . 10
456 bset 32 r d 0000...111000... .......... U U U 8 8 4
457 bset 8 r . 0000...111...... A+-DXWL... U U U 8 8 4
458 bset 8 s . 0000100011...... A+-DXWL... U U U 12 12 4
459 bset 32 s d 0000100011000... .......... U U U 12 12 4
460 bsr 8 . . 01100001........ .......... U U U 18 18 7
461 bsr 16 . . 0110000100000000 .......... U U U 18 18 7
462 bsr 32 . . 0110000111111111 .......... . . U . . 7
463 btst 8 r . 0000...100...... A+-DXWLdxI U U U 4 4 4
464 btst 32 r d 0000...100000... .......... U U U 6 6 4
465 btst 8 s . 0000100000...... A+-DXWLdx. U U U 8 8 4
466 btst 32 s d 0000100000000... .......... U U U 10 10 4
467 callm 32 . . 0000011011...... A..DXWLdx. . . U . . 60 not properly emulated
468 cas 8 . . 0000101011...... A+-DXWL... . . U . . 12
469 cas 16 . . 0000110011...... A+-DXWL... . . U . . 12
470 cas 32 . . 0000111011...... A+-DXWL... . . U . . 12
471 cas2 16 . . 0000110011111100 .......... . . U . . 12
472 cas2 32 . . 0000111011111100 .......... . . U . . 12
473 chk 16 . d 0100...110000... .......... U U U 10 8 8
474 chk 16 . . 0100...110...... A+-DXWLdxI U U U 10 8 8
475 chk 32 . d 0100...100000... .......... . . U . . 8
476 chk 32 . . 0100...100...... A+-DXWLdxI . . U . . 8
477 chk2cmp2 8 . . 0000000011...... A..DXWLdx. . . U . . 18
478 chk2cmp2 16 . . 0000001011...... A..DXWLdx. . . U . . 18
479 chk2cmp2 32 . . 0000010011...... A..DXWLdx. . . U . . 18
480 clr 8 . d 0100001000000... .......... U U U 4 4 2
481 clr 8 . . 0100001000...... A+-DXWL... U U U 8 4 4
482 clr 16 . d 0100001001000... .......... U U U 4 4 2
483 clr 16 . . 0100001001...... A+-DXWL... U U U 8 4 4
484 clr 32 . d 0100001010000... .......... U U U 6 6 2
485 clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4
486 cmp 8 . d 1011...000000... .......... U U U 4 4 2
487 cmp 8 . . 1011...000...... A+-DXWLdxI U U U 4 4 2
488 cmp 16 . d 1011...001000... .......... U U U 4 4 2
489 cmp 16 . a 1011...001001... .......... U U U 4 4 2
490 cmp 16 . . 1011...001...... A+-DXWLdxI U U U 4 4 2
491 cmp 32 . d 1011...010000... .......... U U U 6 6 2
492 cmp 32 . a 1011...010001... .......... U U U 6 6 2
493 cmp 32 . . 1011...010...... A+-DXWLdxI U U U 6 6 2
494 cmpa 16 . d 1011...011000... .......... U U U 6 6 4
495 cmpa 16 . a 1011...011001... .......... U U U 6 6 4
496 cmpa 16 . . 1011...011...... A+-DXWLdxI U U U 6 6 4
497 cmpa 32 . d 1011...111000... .......... U U U 6 6 4
498 cmpa 32 . a 1011...111001... .......... U U U 6 6 4
499 cmpa 32 . . 1011...111...... A+-DXWLdxI U U U 6 6 4
500 cmpi 8 . d 0000110000000... .......... U U U 8 8 2
501 cmpi 8 . . 0000110000...... A+-DXWL... U U U 8 8 2
502 cmpi 8 . pcdi 0000110000111010 .......... . . U . . 7
503 cmpi 8 . pcix 0000110000111011 .......... . . U . . 9
504 cmpi 16 . d 0000110001000... .......... U U U 8 8 2
505 cmpi 16 . . 0000110001...... A+-DXWL... U U U 8 8 2
506 cmpi 16 . pcdi 0000110001111010 .......... . . U . . 7
507 cmpi 16 . pcix 0000110001111011 .......... . . U . . 9
508 cmpi 32 . d 0000110010000... .......... U U U 14 12 2
509 cmpi 32 . . 0000110010...... A+-DXWL... U U U 12 12 2
510 cmpi 32 . pcdi 0000110010111010 .......... . . U . . 7
511 cmpi 32 . pcix 0000110010111011 .......... . . U . . 9
512 cmpm 8 . ax7 1011111100001... .......... U U U 12 12 9
513 cmpm 8 . ay7 1011...100001111 .......... U U U 12 12 9
514 cmpm 8 . axy7 1011111100001111 .......... U U U 12 12 9
515 cmpm 8 . . 1011...100001... .......... U U U 12 12 9
516 cmpm 16 . . 1011...101001... .......... U U U 12 12 9
517 cmpm 32 . . 1011...110001... .......... U U U 20 20 9
518 cpbcc 32 . . 1111...01....... .......... . . U . . 4 unemulated
519 cpdbcc 32 . . 1111...001001... .......... . . U . . 4 unemulated
520 cpgen 32 . . 1111...000...... .......... . . U . . 4 unemulated
521 cpscc 32 . . 1111...001...... .......... . . U . . 4 unemulated
522 cptrapcc 32 . . 1111...001111... .......... . . U . . 4 unemulated
523 dbt 16 . . 0101000011001... .......... U U U 12 12 6
524 dbf 16 . . 0101000111001... .......... U U U 14 14 6
525 dbcc 16 . . 0101....11001... .......... U U U 12 12 6
526 divs 16 . d 1000...111000... .......... U U U 158 122 56
527 divs 16 . . 1000...111...... A+-DXWLdxI U U U 158 122 56
528 divu 16 . d 1000...011000... .......... U U U 140 108 44
529 divu 16 . . 1000...011...... A+-DXWLdxI U U U 140 108 44
530 divl 32 . d 0100110001000... .......... . . U . . 84
531 divl 32 . . 0100110001...... A+-DXWLdxI . . U . . 84
532 eor 8 . d 1011...100000... .......... U U U 4 4 2
533 eor 8 . . 1011...100...... A+-DXWL... U U U 8 8 4
534 eor 16 . d 1011...101000... .......... U U U 4 4 2
535 eor 16 . . 1011...101...... A+-DXWL... U U U 8 8 4
536 eor 32 . d 1011...110000... .......... U U U 8 6 2
537 eor 32 . . 1011...110...... A+-DXWL... U U U 12 12 4
538 eori 16 toc . 0000101000111100 .......... U U U 20 16 12
539 eori 16 tos . 0000101001111100 .......... S S S 20 16 12
540 eori 8 . d 0000101000000... .......... U U U 8 8 2
541 eori 8 . . 0000101000...... A+-DXWL... U U U 12 12 4
542 eori 16 . d 0000101001000... .......... U U U 8 8 2
543 eori 16 . . 0000101001...... A+-DXWL... U U U 12 12 4
544 eori 32 . d 0000101010000... .......... U U U 16 14 2
545 eori 32 . . 0000101010...... A+-DXWL... U U U 20 20 4
546 exg 32 dd . 1100...101000... .......... U U U 6 6 2
547 exg 32 aa . 1100...101001... .......... U U U 6 6 2
548 exg 32 da . 1100...110001... .......... U U U 6 6 2
549 ext 16 . . 0100100010000... .......... U U U 4 4 4
550 ext 32 . . 0100100011000... .......... U U U 4 4 4
551 extb 32 . . 0100100111000... .......... . . U . . 4
552 illegal 0 . . 0100101011111100 .......... U U U 4 4 4
553 jmp 32 . . 0100111011...... A..DXWLdx. U U U 4 4 0
554 jsr 32 . . 0100111010...... A..DXWLdx. U U U 12 12 0
555 lea 32 . . 0100...111...... A..DXWLdx. U U U 0 0 2
556 link 16 . a7 0100111001010111 .......... U U U 16 16 5
557 link 16 . . 0100111001010... .......... U U U 16 16 5
558 link 32 . a7 0100100000001111 .......... . . U . . 6
559 link 32 . . 0100100000001... .......... . . U . . 6
560 lsr 8 s . 1110...000001... .......... U U U 6 6 4
561 lsr 16 s . 1110...001001... .......... U U U 6 6 4
562 lsr 32 s . 1110...010001... .......... U U U 8 8 4
563 lsr 8 r . 1110...000101... .......... U U U 6 6 6
564 lsr 16 r . 1110...001101... .......... U U U 6 6 6
565 lsr 32 r . 1110...010101... .......... U U U 8 8 6
566 lsr 16 . . 1110001011...... A+-DXWL... U U U 8 8 5
567 lsl 8 s . 1110...100001... .......... U U U 6 6 4
568 lsl 16 s . 1110...101001... .......... U U U 6 6 4
569 lsl 32 s . 1110...110001... .......... U U U 8 8 4
570 lsl 8 r . 1110...100101... .......... U U U 6 6 6
571 lsl 16 r . 1110...101101... .......... U U U 6 6 6
572 lsl 32 r . 1110...110101... .......... U U U 8 8 6
573 lsl 16 . . 1110001111...... A+-DXWL... U U U 8 8 5
574 move 8 d d 0001...000000... .......... U U U 4 4 2
575 move 8 d . 0001...000...... A+-DXWLdxI U U U 4 4 2
576 move 8 ai d 0001...010000... .......... U U U 8 8 4
577 move 8 ai . 0001...010...... A+-DXWLdxI U U U 8 8 4
578 move 8 pi d 0001...011000... .......... U U U 8 8 4
579 move 8 pi . 0001...011...... A+-DXWLdxI U U U 8 8 4
580 move 8 pi7 d 0001111011000... .......... U U U 8 8 4
581 move 8 pi7 . 0001111011...... A+-DXWLdxI U U U 8 8 4
582 move 8 pd d 0001...100000... .......... U U U 8 8 5
583 move 8 pd . 0001...100...... A+-DXWLdxI U U U 8 8 5
584 move 8 pd7 d 0001111100000... .......... U U U 8 8 5
585 move 8 pd7 . 0001111100...... A+-DXWLdxI U U U 8 8 5
586 move 8 di d 0001...101000... .......... U U U 12 12 5
587 move 8 di . 0001...101...... A+-DXWLdxI U U U 12 12 5
588 move 8 ix d 0001...110000... .......... U U U 14 14 7
589 move 8 ix . 0001...110...... A+-DXWLdxI U U U 14 14 7
590 move 8 aw d 0001000111000... .......... U U U 12 12 4
591 move 8 aw . 0001000111...... A+-DXWLdxI U U U 12 12 4
592 move 8 al d 0001001111000... .......... U U U 16 16 6
593 move 8 al . 0001001111...... A+-DXWLdxI U U U 16 16 6
594 move 16 d d 0011...000000... .......... U U U 4 4 2
595 move 16 d a 0011...000001... .......... U U U 4 4 2
596 move 16 d . 0011...000...... A+-DXWLdxI U U U 4 4 2
597 move 16 ai d 0011...010000... .......... U U U 8 8 4
598 move 16 ai a 0011...010001... .......... U U U 8 8 4
599 move 16 ai . 0011...010...... A+-DXWLdxI U U U 8 8 4
600 move 16 pi d 0011...011000... .......... U U U 8 8 4
601 move 16 pi a 0011...011001... .......... U U U 8 8 4
602 move 16 pi . 0011...011...... A+-DXWLdxI U U U 8 8 4
603 move 16 pd d 0011...100000... .......... U U U 8 8 5
604 move 16 pd a 0011...100001... .......... U U U 8 8 5
605 move 16 pd . 0011...100...... A+-DXWLdxI U U U 8 8 5
606 move 16 di d 0011...101000... .......... U U U 12 12 5
607 move 16 di a 0011...101001... .......... U U U 12 12 5
608 move 16 di . 0011...101...... A+-DXWLdxI U U U 12 12 5
609 move 16 ix d 0011...110000... .......... U U U 14 14 7
610 move 16 ix a 0011...110001... .......... U U U 14 14 7
611 move 16 ix . 0011...110...... A+-DXWLdxI U U U 14 14 7
612 move 16 aw d 0011000111000... .......... U U U 12 12 4
613 move 16 aw a 0011000111001... .......... U U U 12 12 4
614 move 16 aw . 0011000111...... A+-DXWLdxI U U U 12 12 4
615 move 16 al d 0011001111000... .......... U U U 16 16 6
616 move 16 al a 0011001111001... .......... U U U 16 16 6
617 move 16 al . 0011001111...... A+-DXWLdxI U U U 16 16 6
618 move 32 d d 0010...000000... .......... U U U 4 4 2
619 move 32 d a 0010...000001... .......... U U U 4 4 2
620 move 32 d . 0010...000...... A+-DXWLdxI U U U 4 4 2
621 move 32 ai d 0010...010000... .......... U U U 12 12 4
622 move 32 ai a 0010...010001... .......... U U U 12 12 4
623 move 32 ai . 0010...010...... A+-DXWLdxI U U U 12 12 4
624 move 32 pi d 0010...011000... .......... U U U 12 12 4
625 move 32 pi a 0010...011001... .......... U U U 12 12 4
626 move 32 pi . 0010...011...... A+-DXWLdxI U U U 12 12 4
627 move 32 pd d 0010...100000... .......... U U U 12 14 5
628 move 32 pd a 0010...100001... .......... U U U 12 14 5
629 move 32 pd . 0010...100...... A+-DXWLdxI U U U 12 14 5
630 move 32 di d 0010...101000... .......... U U U 16 16 5
631 move 32 di a 0010...101001... .......... U U U 16 16 5
632 move 32 di . 0010...101...... A+-DXWLdxI U U U 16 16 5
633 move 32 ix d 0010...110000... .......... U U U 18 18 7
634 move 32 ix a 0010...110001... .......... U U U 18 18 7
635 move 32 ix . 0010...110...... A+-DXWLdxI U U U 18 18 7
636 move 32 aw d 0010000111000... .......... U U U 16 16 4
637 move 32 aw a 0010000111001... .......... U U U 16 16 4
638 move 32 aw . 0010000111...... A+-DXWLdxI U U U 16 16 4
639 move 32 al d 0010001111000... .......... U U U 20 20 6
640 move 32 al a 0010001111001... .......... U U U 20 20 6
641 move 32 al . 0010001111...... A+-DXWLdxI U U U 20 20 6
642 movea 16 . d 0011...001000... .......... U U U 4 4 2
643 movea 16 . a 0011...001001... .......... U U U 4 4 2
644 movea 16 . . 0011...001...... A+-DXWLdxI U U U 4 4 2
645 movea 32 . d 0010...001000... .......... U U U 4 4 2
646 movea 32 . a 0010...001001... .......... U U U 4 4 2
647 movea 32 . . 0010...001...... A+-DXWLdxI U U U 4 4 2
648 move 16 frc d 0100001011000... .......... . U U . 4 4
649 move 16 frc . 0100001011...... A+-DXWL... . U U . 8 4
650 move 16 toc d 0100010011000... .......... U U U 12 12 4
651 move 16 toc . 0100010011...... A+-DXWLdxI U U U 12 12 4
652 move 16 frs d 0100000011000... .......... U S S 6 4 8 U only for 000
653 move 16 frs . 0100000011...... A+-DXWL... U S S 8 8 8 U only for 000
654 move 16 tos d 0100011011000... .......... S S S 12 12 8
655 move 16 tos . 0100011011...... A+-DXWLdxI S S S 12 12 8
656 move 32 fru . 0100111001101... .......... S S S 4 6 2
657 move 32 tou . 0100111001100... .......... S S S 4 6 2
658 movec 32 cr . 0100111001111010 .......... . S S . 12 6
659 movec 32 rc . 0100111001111011 .......... . S S . 10 12
660 movem 16 re pd 0100100010100... .......... U U U 8 8 4
661 movem 16 re . 0100100010...... A..DXWL... U U U 8 8 4
662 movem 32 re pd 0100100011100... .......... U U U 8 8 4
663 movem 32 re . 0100100011...... A..DXWL... U U U 8 8 4
664 movem 16 er pi 0100110010011... .......... U U U 12 12 8
665 movem 16 er . 0100110010...... A..DXWLdx. U U U 12 12 8
666 movem 32 er pi 0100110011011... .......... U U U 12 12 8
667 movem 32 er . 0100110011...... A..DXWLdx. U U U 12 12 8
668 movep 16 er . 0000...100001... .......... U U U 16 16 12
669 movep 32 er . 0000...101001... .......... U U U 24 24 18
670 movep 16 re . 0000...110001... .......... U U U 16 16 11
671 movep 32 re . 0000...111001... .......... U U U 24 24 17
672 moveq 32 . . 0111...0........ .......... U U U 4 4 2
673 moves 8 . . 0000111000...... A+-DXWL... . S S . 14 5
674 moves 16 . . 0000111001...... A+-DXWL... . S S . 14 5
675 moves 32 . . 0000111010...... A+-DXWL... . S S . 16 5
676 muls 16 . d 1100...111000... .......... U U U 54 32 27
677 muls 16 . . 1100...111...... A+-DXWLdxI U U U 54 32 27
678 mulu 16 . d 1100...011000... .......... U U U 54 30 27
679 mulu 16 . . 1100...011...... A+-DXWLdxI U U U 54 30 27
680 mull 32 . d 0100110000000... .......... . . U . . 43
681 mull 32 . . 0100110000...... A+-DXWLdxI . . U . . 43
682 nbcd 8 . d 0100100000000... .......... U U U 6 6 6
683 nbcd 8 . . 0100100000...... A+-DXWL... U U U 8 8 6
684 neg 8 . d 0100010000000... .......... U U U 4 4 2
685 neg 8 . . 0100010000...... A+-DXWL... U U U 8 8 4
686 neg 16 . d 0100010001000... .......... U U U 4 4 2
687 neg 16 . . 0100010001...... A+-DXWL... U U U 8 8 4
688 neg 32 . d 0100010010000... .......... U U U 6 6 2
689 neg 32 . . 0100010010...... A+-DXWL... U U U 12 12 4
690 negx 8 . d 0100000000000... .......... U U U 4 4 2
691 negx 8 . . 0100000000...... A+-DXWL... U U U 8 8 4
692 negx 16 . d 0100000001000... .......... U U U 4 4 2
693 negx 16 . . 0100000001...... A+-DXWL... U U U 8 8 4
694 negx 32 . d 0100000010000... .......... U U U 6 6 2
695 negx 32 . . 0100000010...... A+-DXWL... U U U 12 12 4
696 nop 0 . . 0100111001110001 .......... U U U 4 4 2
697 not 8 . d 0100011000000... .......... U U U 4 4 2
698 not 8 . . 0100011000...... A+-DXWL... U U U 8 8 4
699 not 16 . d 0100011001000... .......... U U U 4 4 2
700 not 16 . . 0100011001...... A+-DXWL... U U U 8 8 4
701 not 32 . d 0100011010000... .......... U U U 6 6 2
702 not 32 . . 0100011010...... A+-DXWL... U U U 12 12 4
703 or 8 er d 1000...000000... .......... U U U 4 4 2
704 or 8 er . 1000...000...... A+-DXWLdxI U U U 4 4 2
705 or 16 er d 1000...001000... .......... U U U 4 4 2
706 or 16 er . 1000...001...... A+-DXWLdxI U U U 4 4 2
707 or 32 er d 1000...010000... .......... U U U 6 6 2
708 or 32 er . 1000...010...... A+-DXWLdxI U U U 6 6 2
709 or 8 re . 1000...100...... A+-DXWL... U U U 8 8 4
710 or 16 re . 1000...101...... A+-DXWL... U U U 8 8 4
711 or 32 re . 1000...110...... A+-DXWL... U U U 12 12 4
712 ori 16 toc . 0000000000111100 .......... U U U 20 16 12
713 ori 16 tos . 0000000001111100 .......... S S S 20 16 12
714 ori 8 . d 0000000000000... .......... U U U 8 8 2
715 ori 8 . . 0000000000...... A+-DXWL... U U U 12 12 4
716 ori 16 . d 0000000001000... .......... U U U 8 8 2
717 ori 16 . . 0000000001...... A+-DXWL... U U U 12 12 4
718 ori 32 . d 0000000010000... .......... U U U 16 14 2
719 ori 32 . . 0000000010...... A+-DXWL... U U U 20 20 4
720 pack 16 rr . 1000...101000... .......... . . U . . 6
721 pack 16 mm ax7 1000111101001... .......... . . U . . 13
722 pack 16 mm ay7 1000...101001111 .......... . . U . . 13
723 pack 16 mm axy7 1000111101001111 .......... . . U . . 13
724 pack 16 mm . 1000...101001... .......... . . U . . 13
725 pea 32 . . 0100100001...... A..DXWLdx. U U U 6 6 5
726 reset 0 . . 0100111001110000 .......... S S S 0 0 0
727 ror 8 s . 1110...000011... .......... U U U 6 6 8
728 ror 16 s . 1110...001011... .......... U U U 6 6 8
729 ror 32 s . 1110...010011... .......... U U U 8 8 8
730 ror 8 r . 1110...000111... .......... U U U 6 6 8
731 ror 16 r . 1110...001111... .......... U U U 6 6 8
732 ror 32 r . 1110...010111... .......... U U U 8 8 8
733 ror 16 . . 1110011011...... A+-DXWL... U U U 8 8 7
734 rol 8 s . 1110...100011... .......... U U U 6 6 8
735 rol 16 s . 1110...101011... .......... U U U 6 6 8
736 rol 32 s . 1110...110011... .......... U U U 8 8 8
737 rol 8 r . 1110...100111... .......... U U U 6 6 8
738 rol 16 r . 1110...101111... .......... U U U 6 6 8
739 rol 32 r . 1110...110111... .......... U U U 8 8 8
740 rol 16 . . 1110011111...... A+-DXWL... U U U 8 8 7
741 roxr 8 s . 1110...000010... .......... U U U 6 6 12
742 roxr 16 s . 1110...001010... .......... U U U 6 6 12
743 roxr 32 s . 1110...010010... .......... U U U 8 8 12
744 roxr 8 r . 1110...000110... .......... U U U 6 6 12
745 roxr 16 r . 1110...001110... .......... U U U 6 6 12
746 roxr 32 r . 1110...010110... .......... U U U 8 8 12
747 roxr 16 . . 1110010011...... A+-DXWL... U U U 8 8 5
748 roxl 8 s . 1110...100010... .......... U U U 6 6 12
749 roxl 16 s . 1110...101010... .......... U U U 6 6 12
750 roxl 32 s . 1110...110010... .......... U U U 8 8 12
751 roxl 8 r . 1110...100110... .......... U U U 6 6 12
752 roxl 16 r . 1110...101110... .......... U U U 6 6 12
753 roxl 32 r . 1110...110110... .......... U U U 8 8 12
754 roxl 16 . . 1110010111...... A+-DXWL... U U U 8 8 5
755 rtd 32 . . 0100111001110100 .......... . U U . 16 10
756 rte 32 . . 0100111001110011 .......... S S S 20 24 20 bus fault not emulated
757 rtm 32 . . 000001101100.... .......... . . U . . 19 not properly emulated
758 rtr 32 . . 0100111001110111 .......... U U U 20 20 14
759 rts 32 . . 0100111001110101 .......... U U U 16 16 10
760 sbcd 8 rr . 1000...100000... .......... U U U 6 6 4
761 sbcd 8 mm ax7 1000111100001... .......... U U U 18 18 16
762 sbcd 8 mm ay7 1000...100001111 .......... U U U 18 18 16
763 sbcd 8 mm axy7 1000111100001111 .......... U U U 18 18 16
764 sbcd 8 mm . 1000...100001... .......... U U U 18 18 16
765 st 8 . d 0101000011000... .......... U U U 6 4 4
766 st 8 . . 0101000011...... A+-DXWL... U U U 8 8 6
767 sf 8 . d 0101000111000... .......... U U U 4 4 4
768 sf 8 . . 0101000111...... A+-DXWL... U U U 8 8 6
769 scc 8 . d 0101....11000... .......... U U U 4 4 4
770 scc 8 . . 0101....11...... A+-DXWL... U U U 8 8 6
771 stop 0 . . 0100111001110010 .......... S S S 4 4 8
772 sub 8 er d 1001...000000... .......... U U U 4 4 2
773 sub 8 er . 1001...000...... A+-DXWLdxI U U U 4 4 2
774 sub 16 er d 1001...001000... .......... U U U 4 4 2
775 sub 16 er a 1001...001001... .......... U U U 4 4 2
776 sub 16 er . 1001...001...... A+-DXWLdxI U U U 4 4 2
777 sub 32 er d 1001...010000... .......... U U U 6 6 2
778 sub 32 er a 1001...010001... .......... U U U 6 6 2
779 sub 32 er . 1001...010...... A+-DXWLdxI U U U 6 6 2
780 sub 8 re . 1001...100...... A+-DXWL... U U U 8 8 4
781 sub 16 re . 1001...101...... A+-DXWL... U U U 8 8 4
782 sub 32 re . 1001...110...... A+-DXWL... U U U 12 12 4
783 suba 16 . d 1001...011000... .......... U U U 8 8 2
784 suba 16 . a 1001...011001... .......... U U U 8 8 2
785 suba 16 . . 1001...011...... A+-DXWLdxI U U U 8 8 2
786 suba 32 . d 1001...111000... .......... U U U 6 6 2
787 suba 32 . a 1001...111001... .......... U U U 6 6 2
788 suba 32 . . 1001...111...... A+-DXWLdxI U U U 6 6 2
789 subi 8 . d 0000010000000... .......... U U U 8 8 2
790 subi 8 . . 0000010000...... A+-DXWL... U U U 12 12 4
791 subi 16 . d 0000010001000... .......... U U U 8 8 2
792 subi 16 . . 0000010001...... A+-DXWL... U U U 12 12 4
793 subi 32 . d 0000010010000... .......... U U U 16 14 2
794 subi 32 . . 0000010010...... A+-DXWL... U U U 20 20 4
795 subq 8 . d 0101...100000... .......... U U U 4 4 2
796 subq 8 . . 0101...100...... A+-DXWL... U U U 8 8 4
797 subq 16 . d 0101...101000... .......... U U U 4 4 2
798 subq 16 . a 0101...101001... .......... U U U 8 4 2
799 subq 16 . . 0101...101...... A+-DXWL... U U U 8 8 4
800 subq 32 . d 0101...110000... .......... U U U 8 8 2
801 subq 32 . a 0101...110001... .......... U U U 8 8 2
802 subq 32 . . 0101...110...... A+-DXWL... U U U 12 12 4
803 subx 8 rr . 1001...100000... .......... U U U 4 4 2
804 subx 16 rr . 1001...101000... .......... U U U 4 4 2
805 subx 32 rr . 1001...110000... .......... U U U 8 6 2
806 subx 8 mm ax7 1001111100001... .......... U U U 18 18 12
807 subx 8 mm ay7 1001...100001111 .......... U U U 18 18 12
808 subx 8 mm axy7 1001111100001111 .......... U U U 18 18 12
809 subx 8 mm . 1001...100001... .......... U U U 18 18 12
810 subx 16 mm . 1001...101001... .......... U U U 18 18 12
811 subx 32 mm . 1001...110001... .......... U U U 30 30 12
812 swap 32 . . 0100100001000... .......... U U U 4 4 4
813 tas 8 . d 0100101011000... .......... U U U 4 4 4
814 tas 8 . . 0100101011...... A+-DXWL... U U U 14 14 12
815 trap 0 . . 010011100100.... .......... U U U 4 4 4
816 trapt 0 . . 0101000011111100 .......... . . U . . 4
817 trapt 16 . . 0101000011111010 .......... . . U . . 6
818 trapt 32 . . 0101000011111011 .......... . . U . . 8
819 trapf 0 . . 0101000111111100 .......... . . U . . 4
820 trapf 16 . . 0101000111111010 .......... . . U . . 6
821 trapf 32 . . 0101000111111011 .......... . . U . . 8
822 trapcc 0 . . 0101....11111100 .......... . . U . . 4
823 trapcc 16 . . 0101....11111010 .......... . . U . . 6
824 trapcc 32 . . 0101....11111011 .......... . . U . . 8
825 trapv 0 . . 0100111001110110 .......... U U U 4 4 4
826 tst 8 . d 0100101000000... .......... U U U 4 4 2
827 tst 8 . . 0100101000...... A+-DXWL... U U U 4 4 2
828 tst 8 . pcdi 0100101000111010 .......... . . U . . 7
829 tst 8 . pcix 0100101000111011 .......... . . U . . 9
830 tst 8 . i 0100101000111100 .......... . . U . . 6
831 tst 16 . d 0100101001000... .......... U U U 4 4 2
832 tst 16 . a 0100101001001... .......... . . U . . 2
833 tst 16 . . 0100101001...... A+-DXWL... U U U 4 4 2
834 tst 16 . pcdi 0100101001111010 .......... . . U . . 7
835 tst 16 . pcix 0100101001111011 .......... . . U . . 9
836 tst 16 . i 0100101001111100 .......... . . U . . 6
837 tst 32 . d 0100101010000... .......... U U U 4 4 2
838 tst 32 . a 0100101010001... .......... . . U . . 2
839 tst 32 . . 0100101010...... A+-DXWL... U U U 4 4 2
840 tst 32 . pcdi 0100101010111010 .......... . . U . . 7
841 tst 32 . pcix 0100101010111011 .......... . . U . . 9
842 tst 32 . i 0100101010111100 .......... . . U . . 6
843 unlk 32 . a7 0100111001011111 .......... U U U 12 12 6
844 unlk 32 . . 0100111001011... .......... U U U 12 12 6
845 unpk 16 rr . 1000...110000... .......... . . U . . 8
846 unpk 16 mm ax7 1000111110001... .......... . . U . . 13
847 unpk 16 mm ay7 1000...110001111 .......... . . U . . 13
848 unpk 16 mm axy7 1000111110001111 .......... . . U . . 13
849 unpk 16 mm . 1000...110001... .......... . . U . . 13
853 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
854 M68KMAKE_OPCODE_HANDLER_BODY
856 M68KMAKE_OP(1010, 0, ., .)
857 {
858 m68ki_exception_1010();
859 }
862 M68KMAKE_OP(1111, 0, ., .)
863 {
864 m68ki_exception_1111();
865 }
868 M68KMAKE_OP(abcd, 8, rr, .)
869 {
870 uint* r_dst = &DX;
871 uint src = DY;
872 uint dst = *r_dst;
873 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
875 if(res > 9)
876 res += 6;
877 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
878 FLAG_X = FLAG_C = (res > 0x99) << 8;
879 if(FLAG_C)
880 res -= 0xa0;
882 FLAG_N = NFLAG_8(res); /* officially undefined */
884 res = MASK_OUT_ABOVE_8(res);
885 FLAG_Z |= res;
887 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
888 }
891 M68KMAKE_OP(abcd, 8, mm, ax7)
892 {
893 uint src = OPER_AY_PD_8();
894 uint ea = EA_A7_PD_8();
895 uint dst = m68ki_read_8(ea);
896 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
898 if(res > 9)
899 res += 6;
900 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
901 FLAG_X = FLAG_C = (res > 0x99) << 8;
902 if(FLAG_C)
903 res -= 0xa0;
905 FLAG_N = NFLAG_8(res); /* officially undefined */
907 res = MASK_OUT_ABOVE_8(res);
908 FLAG_Z |= res;
910 m68ki_write_8(ea, res);
911 }
914 M68KMAKE_OP(abcd, 8, mm, ay7)
915 {
916 uint src = OPER_A7_PD_8();
917 uint ea = EA_AX_PD_8();
918 uint dst = m68ki_read_8(ea);
919 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
921 if(res > 9)
922 res += 6;
923 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
924 FLAG_X = FLAG_C = (res > 0x99) << 8;
925 if(FLAG_C)
926 res -= 0xa0;
928 FLAG_N = NFLAG_8(res); /* officially undefined */
930 res = MASK_OUT_ABOVE_8(res);
931 FLAG_Z |= res;
933 m68ki_write_8(ea, res);
934 }
937 M68KMAKE_OP(abcd, 8, mm, axy7)
938 {
939 uint src = OPER_A7_PD_8();
940 uint ea = EA_A7_PD_8();
941 uint dst = m68ki_read_8(ea);
942 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
944 if(res > 9)
945 res += 6;
946 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
947 FLAG_X = FLAG_C = (res > 0x99) << 8;
948 if(FLAG_C)
949 res -= 0xa0;
951 FLAG_N = NFLAG_8(res); /* officially undefined */
953 res = MASK_OUT_ABOVE_8(res);
954 FLAG_Z |= res;
956 m68ki_write_8(ea, res);
957 }
960 M68KMAKE_OP(abcd, 8, mm, .)
961 {
962 uint src = OPER_AY_PD_8();
963 uint ea = EA_AX_PD_8();
964 uint dst = m68ki_read_8(ea);
965 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
967 if(res > 9)
968 res += 6;
969 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
970 FLAG_X = FLAG_C = (res > 0x99) << 8;
971 if(FLAG_C)
972 res -= 0xa0;
974 FLAG_N = NFLAG_8(res); /* officially undefined */
976 res = MASK_OUT_ABOVE_8(res);
977 FLAG_Z |= res;
979 m68ki_write_8(ea, res);
980 }
983 M68KMAKE_OP(add, 8, er, d)
984 {
985 uint* r_dst = &DX;
986 uint src = MASK_OUT_ABOVE_8(DY);
987 uint dst = MASK_OUT_ABOVE_8(*r_dst);
988 uint res = src + dst;
990 FLAG_N = NFLAG_8(res);
991 FLAG_V = VFLAG_ADD_8(src, dst, res);
992 FLAG_X = FLAG_C = CFLAG_8(res);
993 FLAG_Z = MASK_OUT_ABOVE_8(res);
995 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
996 }
999 M68KMAKE_OP(add, 8, er, .)
1000 {
1001 uint* r_dst = &DX;
1002 uint src = M68KMAKE_GET_OPER_AY_8;
1003 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1004 uint res = src + dst;
1006 FLAG_N = NFLAG_8(res);
1007 FLAG_V = VFLAG_ADD_8(src, dst, res);
1008 FLAG_X = FLAG_C = CFLAG_8(res);
1009 FLAG_Z = MASK_OUT_ABOVE_8(res);
1011 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1012 }
1015 M68KMAKE_OP(add, 16, er, d)
1016 {
1017 uint* r_dst = &DX;
1018 uint src = MASK_OUT_ABOVE_16(DY);
1019 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1020 uint res = src + dst;
1022 FLAG_N = NFLAG_16(res);
1023 FLAG_V = VFLAG_ADD_16(src, dst, res);
1024 FLAG_X = FLAG_C = CFLAG_16(res);
1025 FLAG_Z = MASK_OUT_ABOVE_16(res);
1027 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1028 }
1031 M68KMAKE_OP(add, 16, er, a)
1032 {
1033 uint* r_dst = &DX;
1034 uint src = MASK_OUT_ABOVE_16(AY);
1035 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1036 uint res = src + dst;
1038 FLAG_N = NFLAG_16(res);
1039 FLAG_V = VFLAG_ADD_16(src, dst, res);
1040 FLAG_X = FLAG_C = CFLAG_16(res);
1041 FLAG_Z = MASK_OUT_ABOVE_16(res);
1043 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1044 }
1047 M68KMAKE_OP(add, 16, er, .)
1048 {
1049 uint* r_dst = &DX;
1050 uint src = M68KMAKE_GET_OPER_AY_16;
1051 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1052 uint res = src + dst;
1054 FLAG_N = NFLAG_16(res);
1055 FLAG_V = VFLAG_ADD_16(src, dst, res);
1056 FLAG_X = FLAG_C = CFLAG_16(res);
1057 FLAG_Z = MASK_OUT_ABOVE_16(res);
1059 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1060 }
1063 M68KMAKE_OP(add, 32, er, d)
1064 {
1065 uint* r_dst = &DX;
1066 uint src = DY;
1067 uint dst = *r_dst;
1068 uint res = src + dst;
1070 FLAG_N = NFLAG_32(res);
1071 FLAG_V = VFLAG_ADD_32(src, dst, res);
1072 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1073 FLAG_Z = MASK_OUT_ABOVE_32(res);
1075 *r_dst = FLAG_Z;
1076 }
1079 M68KMAKE_OP(add, 32, er, a)
1080 {
1081 uint* r_dst = &DX;
1082 uint src = AY;
1083 uint dst = *r_dst;
1084 uint res = src + dst;
1086 FLAG_N = NFLAG_32(res);
1087 FLAG_V = VFLAG_ADD_32(src, dst, res);
1088 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1089 FLAG_Z = MASK_OUT_ABOVE_32(res);
1091 *r_dst = FLAG_Z;
1092 }
1095 M68KMAKE_OP(add, 32, er, .)
1096 {
1097 uint* r_dst = &DX;
1098 uint src = M68KMAKE_GET_OPER_AY_32;
1099 uint dst = *r_dst;
1100 uint res = src + dst;
1102 FLAG_N = NFLAG_32(res);
1103 FLAG_V = VFLAG_ADD_32(src, dst, res);
1104 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1105 FLAG_Z = MASK_OUT_ABOVE_32(res);
1107 *r_dst = FLAG_Z;
1108 }
1111 M68KMAKE_OP(add, 8, re, .)
1112 {
1113 uint ea = M68KMAKE_GET_EA_AY_8;
1114 uint src = MASK_OUT_ABOVE_8(DX);
1115 uint dst = m68ki_read_8(ea);
1116 uint res = src + dst;
1118 FLAG_N = NFLAG_8(res);
1119 FLAG_V = VFLAG_ADD_8(src, dst, res);
1120 FLAG_X = FLAG_C = CFLAG_8(res);
1121 FLAG_Z = MASK_OUT_ABOVE_8(res);
1123 m68ki_write_8(ea, FLAG_Z);
1124 }
1127 M68KMAKE_OP(add, 16, re, .)
1128 {
1129 uint ea = M68KMAKE_GET_EA_AY_16;
1130 uint src = MASK_OUT_ABOVE_16(DX);
1131 uint dst = m68ki_read_16(ea);
1132 uint res = src + dst;
1134 FLAG_N = NFLAG_16(res);
1135 FLAG_V = VFLAG_ADD_16(src, dst, res);
1136 FLAG_X = FLAG_C = CFLAG_16(res);
1137 FLAG_Z = MASK_OUT_ABOVE_16(res);
1139 m68ki_write_16(ea, FLAG_Z);
1140 }
1143 M68KMAKE_OP(add, 32, re, .)
1144 {
1145 uint ea = M68KMAKE_GET_EA_AY_32;
1146 uint src = DX;
1147 uint dst = m68ki_read_32(ea);
1148 uint res = src + dst;
1150 FLAG_N = NFLAG_32(res);
1151 FLAG_V = VFLAG_ADD_32(src, dst, res);
1152 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1153 FLAG_Z = MASK_OUT_ABOVE_32(res);
1155 m68ki_write_32(ea, FLAG_Z);
1156 }
1159 M68KMAKE_OP(adda, 16, ., d)
1160 {
1161 uint* r_dst = &AX;
1163 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));
1164 }
1167 M68KMAKE_OP(adda, 16, ., a)
1168 {
1169 uint* r_dst = &AX;
1171 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));
1172 }
1175 M68KMAKE_OP(adda, 16, ., .)
1176 {
1177 uint* r_dst = &AX;
1179 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(M68KMAKE_GET_OPER_AY_16));
1180 }
1183 M68KMAKE_OP(adda, 32, ., d)
1184 {
1185 uint* r_dst = &AX;
1187 *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);
1188 }
1191 M68KMAKE_OP(adda, 32, ., a)
1192 {
1193 uint* r_dst = &AX;
1195 *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);
1196 }
1199 M68KMAKE_OP(adda, 32, ., .)
1200 {
1201 uint* r_dst = &AX;
1203 *r_dst = MASK_OUT_ABOVE_32(*r_dst + M68KMAKE_GET_OPER_AY_32);
1204 }
1207 M68KMAKE_OP(addi, 8, ., d)
1208 {
1209 uint* r_dst = &DY;
1210 uint src = OPER_I_8();
1211 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1212 uint res = src + dst;
1214 FLAG_N = NFLAG_8(res);
1215 FLAG_V = VFLAG_ADD_8(src, dst, res);
1216 FLAG_X = FLAG_C = CFLAG_8(res);
1217 FLAG_Z = MASK_OUT_ABOVE_8(res);
1219 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1220 }
1223 M68KMAKE_OP(addi, 8, ., .)
1224 {
1225 uint src = OPER_I_8();
1226 uint ea = M68KMAKE_GET_EA_AY_8;
1227 uint dst = m68ki_read_8(ea);
1228 uint res = src + dst;
1230 FLAG_N = NFLAG_8(res);
1231 FLAG_V = VFLAG_ADD_8(src, dst, res);
1232 FLAG_X = FLAG_C = CFLAG_8(res);
1233 FLAG_Z = MASK_OUT_ABOVE_8(res);
1235 m68ki_write_8(ea, FLAG_Z);
1236 }
1239 M68KMAKE_OP(addi, 16, ., d)
1240 {
1241 uint* r_dst = &DY;
1242 uint src = OPER_I_16();
1243 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1244 uint res = src + dst;
1246 FLAG_N = NFLAG_16(res);
1247 FLAG_V = VFLAG_ADD_16(src, dst, res);
1248 FLAG_X = FLAG_C = CFLAG_16(res);
1249 FLAG_Z = MASK_OUT_ABOVE_16(res);
1251 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1252 }
1255 M68KMAKE_OP(addi, 16, ., .)
1256 {
1257 uint src = OPER_I_16();
1258 uint ea = M68KMAKE_GET_EA_AY_16;
1259 uint dst = m68ki_read_16(ea);
1260 uint res = src + dst;
1262 FLAG_N = NFLAG_16(res);
1263 FLAG_V = VFLAG_ADD_16(src, dst, res);
1264 FLAG_X = FLAG_C = CFLAG_16(res);
1265 FLAG_Z = MASK_OUT_ABOVE_16(res);
1267 m68ki_write_16(ea, FLAG_Z);
1268 }
1271 M68KMAKE_OP(addi, 32, ., d)
1272 {
1273 uint* r_dst = &DY;
1274 uint src = OPER_I_32();
1275 uint dst = *r_dst;
1276 uint res = src + dst;
1278 FLAG_N = NFLAG_32(res);
1279 FLAG_V = VFLAG_ADD_32(src, dst, res);
1280 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1281 FLAG_Z = MASK_OUT_ABOVE_32(res);
1283 *r_dst = FLAG_Z;
1284 }
1287 M68KMAKE_OP(addi, 32, ., .)
1288 {
1289 uint src = OPER_I_32();
1290 uint ea = M68KMAKE_GET_EA_AY_32;
1291 uint dst = m68ki_read_32(ea);
1292 uint res = src + dst;
1294 FLAG_N = NFLAG_32(res);
1295 FLAG_V = VFLAG_ADD_32(src, dst, res);
1296 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1297 FLAG_Z = MASK_OUT_ABOVE_32(res);
1299 m68ki_write_32(ea, FLAG_Z);
1300 }
1303 M68KMAKE_OP(addq, 8, ., d)
1304 {
1305 uint* r_dst = &DY;
1306 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1307 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1308 uint res = src + dst;
1310 FLAG_N = NFLAG_8(res);
1311 FLAG_V = VFLAG_ADD_8(src, dst, res);
1312 FLAG_X = FLAG_C = CFLAG_8(res);
1313 FLAG_Z = MASK_OUT_ABOVE_8(res);
1315 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
1316 }
1319 M68KMAKE_OP(addq, 8, ., .)
1320 {
1321 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1322 uint ea = M68KMAKE_GET_EA_AY_8;
1323 uint dst = m68ki_read_8(ea);
1324 uint res = src + dst;
1326 FLAG_N = NFLAG_8(res);
1327 FLAG_V = VFLAG_ADD_8(src, dst, res);
1328 FLAG_X = FLAG_C = CFLAG_8(res);
1329 FLAG_Z = MASK_OUT_ABOVE_8(res);
1331 m68ki_write_8(ea, FLAG_Z);
1332 }
1335 M68KMAKE_OP(addq, 16, ., d)
1336 {
1337 uint* r_dst = &DY;
1338 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1339 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1340 uint res = src + dst;
1342 FLAG_N = NFLAG_16(res);
1343 FLAG_V = VFLAG_ADD_16(src, dst, res);
1344 FLAG_X = FLAG_C = CFLAG_16(res);
1345 FLAG_Z = MASK_OUT_ABOVE_16(res);
1347 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
1348 }
1351 M68KMAKE_OP(addq, 16, ., a)
1352 {
1353 uint* r_dst = &AY;
1355 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
1356 }
1359 M68KMAKE_OP(addq, 16, ., .)
1360 {
1361 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1362 uint ea = M68KMAKE_GET_EA_AY_16;
1363 uint dst = m68ki_read_16(ea);
1364 uint res = src + dst;
1366 FLAG_N = NFLAG_16(res);
1367 FLAG_V = VFLAG_ADD_16(src, dst, res);
1368 FLAG_X = FLAG_C = CFLAG_16(res);
1369 FLAG_Z = MASK_OUT_ABOVE_16(res);
1371 m68ki_write_16(ea, FLAG_Z);
1372 }
1375 M68KMAKE_OP(addq, 32, ., d)
1376 {
1377 uint* r_dst = &DY;
1378 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1379 uint dst = *r_dst;
1380 uint res = src + dst;
1382 FLAG_N = NFLAG_32(res);
1383 FLAG_V = VFLAG_ADD_32(src, dst, res);
1384 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1385 FLAG_Z = MASK_OUT_ABOVE_32(res);
1387 *r_dst = FLAG_Z;
1388 }
1391 M68KMAKE_OP(addq, 32, ., a)
1392 {
1393 uint* r_dst = &AY;
1395 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
1396 }
1399 M68KMAKE_OP(addq, 32, ., .)
1400 {
1401 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
1402 uint ea = M68KMAKE_GET_EA_AY_32;
1403 uint dst = m68ki_read_32(ea);
1404 uint res = src + dst;
1407 FLAG_N = NFLAG_32(res);
1408 FLAG_V = VFLAG_ADD_32(src, dst, res);
1409 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1410 FLAG_Z = MASK_OUT_ABOVE_32(res);
1412 m68ki_write_32(ea, FLAG_Z);
1413 }
1416 M68KMAKE_OP(addx, 8, rr, .)
1417 {
1418 uint* r_dst = &DX;
1419 uint src = MASK_OUT_ABOVE_8(DY);
1420 uint dst = MASK_OUT_ABOVE_8(*r_dst);
1421 uint res = src + dst + XFLAG_AS_1();
1423 FLAG_N = NFLAG_8(res);
1424 FLAG_V = VFLAG_ADD_8(src, dst, res);
1425 FLAG_X = FLAG_C = CFLAG_8(res);
1427 res = MASK_OUT_ABOVE_8(res);
1428 FLAG_Z |= res;
1430 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
1431 }
1434 M68KMAKE_OP(addx, 16, rr, .)
1435 {
1436 uint* r_dst = &DX;
1437 uint src = MASK_OUT_ABOVE_16(DY);
1438 uint dst = MASK_OUT_ABOVE_16(*r_dst);
1439 uint res = src + dst + XFLAG_AS_1();
1441 FLAG_N = NFLAG_16(res);
1442 FLAG_V = VFLAG_ADD_16(src, dst, res);
1443 FLAG_X = FLAG_C = CFLAG_16(res);
1445 res = MASK_OUT_ABOVE_16(res);
1446 FLAG_Z |= res;
1448 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
1449 }
1452 M68KMAKE_OP(addx, 32, rr, .)
1453 {
1454 uint* r_dst = &DX;
1455 uint src = DY;
1456 uint dst = *r_dst;
1457 uint res = src + dst + XFLAG_AS_1();
1459 FLAG_N = NFLAG_32(res);
1460 FLAG_V = VFLAG_ADD_32(src, dst, res);
1461 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1463 res = MASK_OUT_ABOVE_32(res);
1464 FLAG_Z |= res;
1466 *r_dst = res;
1467 }
1470 M68KMAKE_OP(addx, 8, mm, ax7)
1471 {
1472 uint src = OPER_AY_PD_8();
1473 uint ea = EA_A7_PD_8();
1474 uint dst = m68ki_read_8(ea);
1475 uint res = src + dst + XFLAG_AS_1();
1477 FLAG_N = NFLAG_8(res);
1478 FLAG_V = VFLAG_ADD_8(src, dst, res);
1479 FLAG_X = FLAG_C = CFLAG_8(res);
1481 res = MASK_OUT_ABOVE_8(res);
1482 FLAG_Z |= res;
1484 m68ki_write_8(ea, res);
1485 }
1488 M68KMAKE_OP(addx, 8, mm, ay7)
1489 {
1490 uint src = OPER_A7_PD_8();
1491 uint ea = EA_AX_PD_8();
1492 uint dst = m68ki_read_8(ea);
1493 uint res = src + dst + XFLAG_AS_1();
1495 FLAG_N = NFLAG_8(res);
1496 FLAG_V = VFLAG_ADD_8(src, dst, res);
1497 FLAG_X = FLAG_C = CFLAG_8(res);
1499 res = MASK_OUT_ABOVE_8(res);
1500 FLAG_Z |= res;
1502 m68ki_write_8(ea, res);
1503 }
1506 M68KMAKE_OP(addx, 8, mm, axy7)
1507 {
1508 uint src = OPER_A7_PD_8();
1509 uint ea = EA_A7_PD_8();
1510 uint dst = m68ki_read_8(ea);
1511 uint res = src + dst + XFLAG_AS_1();
1513 FLAG_N = NFLAG_8(res);
1514 FLAG_V = VFLAG_ADD_8(src, dst, res);
1515 FLAG_X = FLAG_C = CFLAG_8(res);
1517 res = MASK_OUT_ABOVE_8(res);
1518 FLAG_Z |= res;
1520 m68ki_write_8(ea, res);
1521 }
1524 M68KMAKE_OP(addx, 8, mm, .)
1525 {
1526 uint src = OPER_AY_PD_8();
1527 uint ea = EA_AX_PD_8();
1528 uint dst = m68ki_read_8(ea);
1529 uint res = src + dst + XFLAG_AS_1();
1531 FLAG_N = NFLAG_8(res);
1532 FLAG_V = VFLAG_ADD_8(src, dst, res);
1533 FLAG_X = FLAG_C = CFLAG_8(res);
1535 res = MASK_OUT_ABOVE_8(res);
1536 FLAG_Z |= res;
1538 m68ki_write_8(ea, res);
1539 }
1542 M68KMAKE_OP(addx, 16, mm, .)
1543 {
1544 uint src = OPER_AY_PD_16();
1545 uint ea = EA_AX_PD_16();
1546 uint dst = m68ki_read_16(ea);
1547 uint res = src + dst + XFLAG_AS_1();
1549 FLAG_N = NFLAG_16(res);
1550 FLAG_V = VFLAG_ADD_16(src, dst, res);
1551 FLAG_X = FLAG_C = CFLAG_16(res);
1553 res = MASK_OUT_ABOVE_16(res);
1554 FLAG_Z |= res;
1556 m68ki_write_16(ea, res);
1557 }
1560 M68KMAKE_OP(addx, 32, mm, .)
1561 {
1562 uint src = OPER_AY_PD_32();
1563 uint ea = EA_AX_PD_32();
1564 uint dst = m68ki_read_32(ea);
1565 uint res = src + dst + XFLAG_AS_1();
1567 FLAG_N = NFLAG_32(res);
1568 FLAG_V = VFLAG_ADD_32(src, dst, res);
1569 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
1571 res = MASK_OUT_ABOVE_32(res);
1572 FLAG_Z |= res;
1574 m68ki_write_32(ea, res);
1575 }
1578 M68KMAKE_OP(and, 8, er, d)
1579 {
1580 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));
1582 FLAG_N = NFLAG_8(FLAG_Z);
1583 FLAG_C = CFLAG_CLEAR;
1584 FLAG_V = VFLAG_CLEAR;
1585 }
1588 M68KMAKE_OP(and, 8, er, .)
1589 {
1590 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00));
1592 FLAG_N = NFLAG_8(FLAG_Z);
1593 FLAG_C = CFLAG_CLEAR;
1594 FLAG_V = VFLAG_CLEAR;
1595 }
1598 M68KMAKE_OP(and, 16, er, d)
1599 {
1600 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));
1602 FLAG_N = NFLAG_16(FLAG_Z);
1603 FLAG_C = CFLAG_CLEAR;
1604 FLAG_V = VFLAG_CLEAR;
1605 }
1608 M68KMAKE_OP(and, 16, er, .)
1609 {
1610 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000));
1612 FLAG_N = NFLAG_16(FLAG_Z);
1613 FLAG_C = CFLAG_CLEAR;
1614 FLAG_V = VFLAG_CLEAR;
1615 }
1618 M68KMAKE_OP(and, 32, er, d)
1619 {
1620 FLAG_Z = DX &= DY;
1622 FLAG_N = NFLAG_32(FLAG_Z);
1623 FLAG_C = CFLAG_CLEAR;
1624 FLAG_V = VFLAG_CLEAR;
1625 }
1628 M68KMAKE_OP(and, 32, er, .)
1629 {
1630 FLAG_Z = DX &= M68KMAKE_GET_OPER_AY_32;
1632 FLAG_N = NFLAG_32(FLAG_Z);
1633 FLAG_C = CFLAG_CLEAR;
1634 FLAG_V = VFLAG_CLEAR;
1635 }
1638 M68KMAKE_OP(and, 8, re, .)
1639 {
1640 uint ea = M68KMAKE_GET_EA_AY_8;
1641 uint res = DX & m68ki_read_8(ea);
1643 FLAG_N = NFLAG_8(res);
1644 FLAG_C = CFLAG_CLEAR;
1645 FLAG_V = VFLAG_CLEAR;
1646 FLAG_Z = MASK_OUT_ABOVE_8(res);
1648 m68ki_write_8(ea, FLAG_Z);
1649 }
1652 M68KMAKE_OP(and, 16, re, .)
1653 {
1654 uint ea = M68KMAKE_GET_EA_AY_16;
1655 uint res = DX & m68ki_read_16(ea);
1657 FLAG_N = NFLAG_16(res);
1658 FLAG_C = CFLAG_CLEAR;
1659 FLAG_V = VFLAG_CLEAR;
1660 FLAG_Z = MASK_OUT_ABOVE_16(res);
1662 m68ki_write_16(ea, FLAG_Z);
1663 }
1666 M68KMAKE_OP(and, 32, re, .)
1667 {
1668 uint ea = M68KMAKE_GET_EA_AY_32;
1669 uint res = DX & m68ki_read_32(ea);
1671 FLAG_N = NFLAG_32(res);
1672 FLAG_Z = res;
1673 FLAG_C = CFLAG_CLEAR;
1674 FLAG_V = VFLAG_CLEAR;
1676 m68ki_write_32(ea, res);
1677 }
1680 M68KMAKE_OP(andi, 8, ., d)
1681 {
1682 FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));
1684 FLAG_N = NFLAG_8(FLAG_Z);
1685 FLAG_C = CFLAG_CLEAR;
1686 FLAG_V = VFLAG_CLEAR;
1687 }
1690 M68KMAKE_OP(andi, 8, ., .)
1691 {
1692 uint src = OPER_I_8();
1693 uint ea = M68KMAKE_GET_EA_AY_8;
1694 uint res = src & m68ki_read_8(ea);
1696 FLAG_N = NFLAG_8(res);
1697 FLAG_Z = res;
1698 FLAG_C = CFLAG_CLEAR;
1699 FLAG_V = VFLAG_CLEAR;
1701 m68ki_write_8(ea, res);
1702 }
1705 M68KMAKE_OP(andi, 16, ., d)
1706 {
1707 FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));
1709 FLAG_N = NFLAG_16(FLAG_Z);
1710 FLAG_C = CFLAG_CLEAR;
1711 FLAG_V = VFLAG_CLEAR;
1712 }
1715 M68KMAKE_OP(andi, 16, ., .)
1716 {
1717 uint src = OPER_I_16();
1718 uint ea = M68KMAKE_GET_EA_AY_16;
1719 uint res = src & m68ki_read_16(ea);
1721 FLAG_N = NFLAG_16(res);
1722 FLAG_Z = res;
1723 FLAG_C = CFLAG_CLEAR;
1724 FLAG_V = VFLAG_CLEAR;
1726 m68ki_write_16(ea, res);
1727 }
1730 M68KMAKE_OP(andi, 32, ., d)
1731 {
1732 FLAG_Z = DY &= (OPER_I_32());
1734 FLAG_N = NFLAG_32(FLAG_Z);
1735 FLAG_C = CFLAG_CLEAR;
1736 FLAG_V = VFLAG_CLEAR;
1737 }
1740 M68KMAKE_OP(andi, 32, ., .)
1741 {
1742 uint src = OPER_I_32();
1743 uint ea = M68KMAKE_GET_EA_AY_32;
1744 uint res = src & m68ki_read_32(ea);
1746 FLAG_N = NFLAG_32(res);
1747 FLAG_Z = res;
1748 FLAG_C = CFLAG_CLEAR;
1749 FLAG_V = VFLAG_CLEAR;
1751 m68ki_write_32(ea, res);
1752 }
1755 M68KMAKE_OP(andi, 16, toc, .)
1756 {
1757 m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16());
1758 }
1761 M68KMAKE_OP(andi, 16, tos, .)
1762 {
1763 if(FLAG_S)
1764 {
1765 uint src = OPER_I_16();
1766 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
1767 m68ki_set_sr(m68ki_get_sr() & src);
1768 return;
1769 }
1770 m68ki_exception_privilege_violation();
1771 }
1774 M68KMAKE_OP(asr, 8, s, .)
1775 {
1776 uint* r_dst = &DY;
1777 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
1778 uint src = MASK_OUT_ABOVE_8(*r_dst);
1779 uint res = src >> shift;
1781 if(GET_MSB_8(src))
1782 res |= m68ki_shift_8_table[shift];
1784 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
1786 FLAG_N = NFLAG_8(res);
1787 FLAG_Z = res;
1788 FLAG_V = VFLAG_CLEAR;
1789 FLAG_X = FLAG_C = src << (9-shift);
1790 }
1793 M68KMAKE_OP(asr, 16, s, .)
1794 {
1795 uint* r_dst = &DY;
1796 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
1797 uint src = MASK_OUT_ABOVE_16(*r_dst);
1798 uint res = src >> shift;
1800 if(GET_MSB_16(src))
1801 res |= m68ki_shift_16_table[shift];
1803 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
1805 FLAG_N = NFLAG_16(res);
1806 FLAG_Z = res;
1807 FLAG_V = VFLAG_CLEAR;
1808 FLAG_X = FLAG_C = src << (9-shift);
1809 }
1812 M68KMAKE_OP(asr, 32, s, .)
1813 {
1814 uint* r_dst = &DY;
1815 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
1816 uint src = *r_dst;
1817 uint res = src >> shift;
1819 if(GET_MSB_32(src))
1820 res |= m68ki_shift_32_table[shift];
1822 *r_dst = res;
1824 FLAG_N = NFLAG_32(res);
1825 FLAG_Z = res;
1826 FLAG_V = VFLAG_CLEAR;
1827 FLAG_X = FLAG_C = src << (9-shift);
1828 }
1831 M68KMAKE_OP(asr, 8, r, .)
1832 {
1833 uint* r_dst = &DY;
1834 uint shift = DX & 0x3f;
1835 uint src = MASK_OUT_ABOVE_8(*r_dst);
1836 uint res = src >> shift;
1838 if(shift != 0)
1839 {
1840 USE_CYCLES(shift<<CYC_SHIFT);
1842 if(shift < 8)
1843 {
1844 if(GET_MSB_8(src))
1845 res |= m68ki_shift_8_table[shift];
1847 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
1849 FLAG_X = FLAG_C = src << (9-shift);
1850 FLAG_N = NFLAG_8(res);
1851 FLAG_Z = res;
1852 FLAG_V = VFLAG_CLEAR;
1853 return;
1854 }
1856 if(GET_MSB_8(src))
1857 {
1858 *r_dst |= 0xff;
1859 FLAG_C = CFLAG_SET;
1860 FLAG_X = XFLAG_SET;
1861 FLAG_N = NFLAG_SET;
1862 FLAG_Z = ZFLAG_CLEAR;
1863 FLAG_V = VFLAG_CLEAR;
1864 return;
1865 }
1867 *r_dst &= 0xffffff00;
1868 FLAG_C = CFLAG_CLEAR;
1869 FLAG_X = XFLAG_CLEAR;
1870 FLAG_N = NFLAG_CLEAR;
1871 FLAG_Z = ZFLAG_SET;
1872 FLAG_V = VFLAG_CLEAR;
1873 return;
1874 }
1876 FLAG_C = CFLAG_CLEAR;
1877 FLAG_N = NFLAG_8(src);
1878 FLAG_Z = src;
1879 FLAG_V = VFLAG_CLEAR;
1880 }
1883 M68KMAKE_OP(asr, 16, r, .)
1884 {
1885 uint* r_dst = &DY;
1886 uint shift = DX & 0x3f;
1887 uint src = MASK_OUT_ABOVE_16(*r_dst);
1888 uint res = src >> shift;
1890 if(shift != 0)
1891 {
1892 USE_CYCLES(shift<<CYC_SHIFT);
1894 if(shift < 16)
1895 {
1896 if(GET_MSB_16(src))
1897 res |= m68ki_shift_16_table[shift];
1899 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
1901 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
1902 FLAG_N = NFLAG_16(res);
1903 FLAG_Z = res;
1904 FLAG_V = VFLAG_CLEAR;
1905 return;
1906 }
1908 if(GET_MSB_16(src))
1909 {
1910 *r_dst |= 0xffff;
1911 FLAG_C = CFLAG_SET;
1912 FLAG_X = XFLAG_SET;
1913 FLAG_N = NFLAG_SET;
1914 FLAG_Z = ZFLAG_CLEAR;
1915 FLAG_V = VFLAG_CLEAR;
1916 return;
1917 }
1919 *r_dst &= 0xffff0000;
1920 FLAG_C = CFLAG_CLEAR;
1921 FLAG_X = XFLAG_CLEAR;
1922 FLAG_N = NFLAG_CLEAR;
1923 FLAG_Z = ZFLAG_SET;
1924 FLAG_V = VFLAG_CLEAR;
1925 return;
1926 }
1928 FLAG_C = CFLAG_CLEAR;
1929 FLAG_N = NFLAG_16(src);
1930 FLAG_Z = src;
1931 FLAG_V = VFLAG_CLEAR;
1932 }
1935 M68KMAKE_OP(asr, 32, r, .)
1936 {
1937 uint* r_dst = &DY;
1938 uint shift = DX & 0x3f;
1939 uint src = *r_dst;
1940 uint res = src >> shift;
1942 if(shift != 0)
1943 {
1944 USE_CYCLES(shift<<CYC_SHIFT);
1946 if(shift < 32)
1947 {
1948 if(GET_MSB_32(src))
1949 res |= m68ki_shift_32_table[shift];
1951 *r_dst = res;
1953 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
1954 FLAG_N = NFLAG_32(res);
1955 FLAG_Z = res;
1956 FLAG_V = VFLAG_CLEAR;
1957 return;
1958 }
1960 if(GET_MSB_32(src))
1961 {
1962 *r_dst = 0xffffffff;
1963 FLAG_C = CFLAG_SET;
1964 FLAG_X = XFLAG_SET;
1965 FLAG_N = NFLAG_SET;
1966 FLAG_Z = ZFLAG_CLEAR;
1967 FLAG_V = VFLAG_CLEAR;
1968 return;
1969 }
1971 *r_dst = 0;
1972 FLAG_C = CFLAG_CLEAR;
1973 FLAG_X = XFLAG_CLEAR;
1974 FLAG_N = NFLAG_CLEAR;
1975 FLAG_Z = ZFLAG_SET;
1976 FLAG_V = VFLAG_CLEAR;
1977 return;
1978 }
1980 FLAG_C = CFLAG_CLEAR;
1981 FLAG_N = NFLAG_32(src);
1982 FLAG_Z = src;
1983 FLAG_V = VFLAG_CLEAR;
1984 }
1987 M68KMAKE_OP(asr, 16, ., .)
1988 {
1989 uint ea = M68KMAKE_GET_EA_AY_16;
1990 uint src = m68ki_read_16(ea);
1991 uint res = src >> 1;
1993 if(GET_MSB_16(src))
1994 res |= 0x8000;
1996 m68ki_write_16(ea, res);
1998 FLAG_N = NFLAG_16(res);
1999 FLAG_Z = res;
2000 FLAG_V = VFLAG_CLEAR;
2001 FLAG_C = FLAG_X = src << 8;
2002 }
2005 M68KMAKE_OP(asl, 8, s, .)
2006 {
2007 uint* r_dst = &DY;
2008 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
2009 uint src = MASK_OUT_ABOVE_8(*r_dst);
2010 uint res = MASK_OUT_ABOVE_8(src << shift);
2012 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
2014 FLAG_X = FLAG_C = src << shift;
2015 FLAG_N = NFLAG_8(res);
2016 FLAG_Z = res;
2017 src &= m68ki_shift_8_table[shift + 1];
2018 FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;
2019 }
2022 M68KMAKE_OP(asl, 16, s, .)
2023 {
2024 uint* r_dst = &DY;
2025 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
2026 uint src = MASK_OUT_ABOVE_16(*r_dst);
2027 uint res = MASK_OUT_ABOVE_16(src << shift);
2029 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
2031 FLAG_N = NFLAG_16(res);
2032 FLAG_Z = res;
2033 FLAG_X = FLAG_C = src >> (8-shift);
2034 src &= m68ki_shift_16_table[shift + 1];
2035 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
2036 }
2039 M68KMAKE_OP(asl, 32, s, .)
2040 {
2041 uint* r_dst = &DY;
2042 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
2043 uint src = *r_dst;
2044 uint res = MASK_OUT_ABOVE_32(src << shift);
2046 *r_dst = res;
2048 FLAG_N = NFLAG_32(res);
2049 FLAG_Z = res;
2050 FLAG_X = FLAG_C = src >> (24-shift);
2051 src &= m68ki_shift_32_table[shift + 1];
2052 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
2053 }
2056 M68KMAKE_OP(asl, 8, r, .)
2057 {
2058 uint* r_dst = &DY;
2059 uint shift = DX & 0x3f;
2060 uint src = MASK_OUT_ABOVE_8(*r_dst);
2061 uint res = MASK_OUT_ABOVE_8(src << shift);
2063 if(shift != 0)
2064 {
2065 USE_CYCLES(shift<<CYC_SHIFT);
2067 if(shift < 8)
2068 {
2069 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
2070 FLAG_X = FLAG_C = src << shift;
2071 FLAG_N = NFLAG_8(res);
2072 FLAG_Z = res;
2073 src &= m68ki_shift_8_table[shift + 1];
2074 FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;
2075 return;
2076 }
2078 *r_dst &= 0xffffff00;
2079 FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;
2080 FLAG_N = NFLAG_CLEAR;
2081 FLAG_Z = ZFLAG_SET;
2082 FLAG_V = (!(src == 0))<<7;
2083 return;
2084 }
2086 FLAG_C = CFLAG_CLEAR;
2087 FLAG_N = NFLAG_8(src);
2088 FLAG_Z = src;
2089 FLAG_V = VFLAG_CLEAR;
2090 }
2093 M68KMAKE_OP(asl, 16, r, .)
2094 {
2095 uint* r_dst = &DY;
2096 uint shift = DX & 0x3f;
2097 uint src = MASK_OUT_ABOVE_16(*r_dst);
2098 uint res = MASK_OUT_ABOVE_16(src << shift);
2100 if(shift != 0)
2101 {
2102 USE_CYCLES(shift<<CYC_SHIFT);
2104 if(shift < 16)
2105 {
2106 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
2107 FLAG_X = FLAG_C = (src << shift) >> 8;
2108 FLAG_N = NFLAG_16(res);
2109 FLAG_Z = res;
2110 src &= m68ki_shift_16_table[shift + 1];
2111 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
2112 return;
2113 }
2115 *r_dst &= 0xffff0000;
2116 FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;
2117 FLAG_N = NFLAG_CLEAR;
2118 FLAG_Z = ZFLAG_SET;
2119 FLAG_V = (!(src == 0))<<7;
2120 return;
2121 }
2123 FLAG_C = CFLAG_CLEAR;
2124 FLAG_N = NFLAG_16(src);
2125 FLAG_Z = src;
2126 FLAG_V = VFLAG_CLEAR;
2127 }
2130 M68KMAKE_OP(asl, 32, r, .)
2131 {
2132 uint* r_dst = &DY;
2133 uint shift = DX & 0x3f;
2134 uint src = *r_dst;
2135 uint res = MASK_OUT_ABOVE_32(src << shift);
2137 if(shift != 0)
2138 {
2139 USE_CYCLES(shift<<CYC_SHIFT);
2141 if(shift < 32)
2142 {
2143 *r_dst = res;
2144 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
2145 FLAG_N = NFLAG_32(res);
2146 FLAG_Z = res;
2147 src &= m68ki_shift_32_table[shift + 1];
2148 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
2149 return;
2150 }
2152 *r_dst = 0;
2153 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
2154 FLAG_N = NFLAG_CLEAR;
2155 FLAG_Z = ZFLAG_SET;
2156 FLAG_V = (!(src == 0))<<7;
2157 return;
2158 }
2160 FLAG_C = CFLAG_CLEAR;
2161 FLAG_N = NFLAG_32(src);
2162 FLAG_Z = src;
2163 FLAG_V = VFLAG_CLEAR;
2164 }
2167 M68KMAKE_OP(asl, 16, ., .)
2168 {
2169 uint ea = M68KMAKE_GET_EA_AY_16;
2170 uint src = m68ki_read_16(ea);
2171 uint res = MASK_OUT_ABOVE_16(src << 1);
2173 m68ki_write_16(ea, res);
2175 FLAG_N = NFLAG_16(res);
2176 FLAG_Z = res;
2177 FLAG_X = FLAG_C = src >> 7;
2178 src &= 0xc000;
2179 FLAG_V = (!(src == 0 || src == 0xc000))<<7;
2180 }
2183 M68KMAKE_OP(bcc, 8, ., .)
2184 {
2185 if(M68KMAKE_CC)
2186 {
2187 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2188 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
2189 return;
2190 }
2191 USE_CYCLES(CYC_BCC_NOTAKE_B);
2192 }
2195 M68KMAKE_OP(bcc, 16, ., .)
2196 {
2197 if(M68KMAKE_CC)
2198 {
2199 uint offset = OPER_I_16();
2200 REG_PC -= 2;
2201 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2202 m68ki_branch_16(offset);
2203 return;
2204 }
2205 REG_PC += 2;
2206 USE_CYCLES(CYC_BCC_NOTAKE_W);
2207 }
2210 M68KMAKE_OP(bcc, 32, ., .)
2211 {
2212 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2213 {
2214 if(M68KMAKE_CC)
2215 {
2216 uint offset = OPER_I_32();
2217 REG_PC -= 4;
2218 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
2219 m68ki_branch_32(offset);
2220 return;
2221 }
2222 REG_PC += 4;
2223 return;
2224 }
2225 m68ki_exception_illegal();
2226 }
2229 M68KMAKE_OP(bchg, 32, r, d)
2230 {
2231 uint* r_dst = &DY;
2232 uint mask = 1 << (DX & 0x1f);
2234 FLAG_Z = *r_dst & mask;
2235 *r_dst ^= mask;
2236 }
2239 M68KMAKE_OP(bchg, 8, r, .)
2240 {
2241 uint ea = M68KMAKE_GET_EA_AY_8;
2242 uint src = m68ki_read_8(ea);
2243 uint mask = 1 << (DX & 7);
2245 FLAG_Z = src & mask;
2246 m68ki_write_8(ea, src ^ mask);
2247 }
2250 M68KMAKE_OP(bchg, 32, s, d)
2251 {
2252 uint* r_dst = &DY;
2253 uint mask = 1 << (OPER_I_8() & 0x1f);
2255 FLAG_Z = *r_dst & mask;
2256 *r_dst ^= mask;
2257 }
2260 M68KMAKE_OP(bchg, 8, s, .)
2261 {
2262 uint mask = 1 << (OPER_I_8() & 7);
2263 uint ea = M68KMAKE_GET_EA_AY_8;
2264 uint src = m68ki_read_8(ea);
2266 FLAG_Z = src & mask;
2267 m68ki_write_8(ea, src ^ mask);
2268 }
2271 M68KMAKE_OP(bclr, 32, r, d)
2272 {
2273 uint* r_dst = &DY;
2274 uint mask = 1 << (DX & 0x1f);
2276 FLAG_Z = *r_dst & mask;
2277 *r_dst &= ~mask;
2278 }
2281 M68KMAKE_OP(bclr, 8, r, .)
2282 {
2283 uint ea = M68KMAKE_GET_EA_AY_8;
2284 uint src = m68ki_read_8(ea);
2285 uint mask = 1 << (DX & 7);
2287 FLAG_Z = src & mask;
2288 m68ki_write_8(ea, src & ~mask);
2289 }
2292 M68KMAKE_OP(bclr, 32, s, d)
2293 {
2294 uint* r_dst = &DY;
2295 uint mask = 1 << (OPER_I_8() & 0x1f);
2297 FLAG_Z = *r_dst & mask;
2298 *r_dst &= ~mask;
2299 }
2302 M68KMAKE_OP(bclr, 8, s, .)
2303 {
2304 uint mask = 1 << (OPER_I_8() & 7);
2305 uint ea = M68KMAKE_GET_EA_AY_8;
2306 uint src = m68ki_read_8(ea);
2308 FLAG_Z = src & mask;
2309 m68ki_write_8(ea, src & ~mask);
2310 }
2313 M68KMAKE_OP(bfchg, 32, ., d)
2314 {
2315 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2316 {
2317 uint word2 = OPER_I_16();
2318 uint offset = (word2>>6)&31;
2319 uint width = word2;
2320 uint* data = &DY;
2321 uint64 mask;
2324 if(BIT_B(word2))
2325 offset = REG_D[offset&7];
2326 if(BIT_5(word2))
2327 width = REG_D[width&7];
2329 offset &= 31;
2330 width = ((width-1) & 31) + 1;
2332 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2333 mask = ROR_32(mask, offset);
2335 FLAG_N = NFLAG_32(*data<<offset);
2336 FLAG_Z = *data & mask;
2337 FLAG_V = VFLAG_CLEAR;
2338 FLAG_C = CFLAG_CLEAR;
2340 *data ^= mask;
2342 return;
2343 }
2344 m68ki_exception_illegal();
2345 }
2348 M68KMAKE_OP(bfchg, 32, ., .)
2349 {
2350 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2351 {
2352 uint word2 = OPER_I_16();
2353 sint offset = (word2>>6)&31;
2354 uint width = word2;
2355 uint mask_base;
2356 uint data_long;
2357 uint mask_long;
2358 uint data_byte = 0;
2359 uint mask_byte = 0;
2360 uint ea = M68KMAKE_GET_EA_AY_8;
2363 if(BIT_B(word2))
2364 offset = MAKE_INT_32(REG_D[offset&7]);
2365 if(BIT_5(word2))
2366 width = REG_D[width&7];
2368 /* Offset is signed so we have to use ugly math =( */
2369 ea += offset / 8;
2370 offset %= 8;
2371 if(offset < 0)
2372 {
2373 offset += 8;
2374 ea--;
2375 }
2376 width = ((width-1) & 31) + 1;
2378 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2379 mask_long = mask_base >> offset;
2381 data_long = m68ki_read_32(ea);
2382 FLAG_N = NFLAG_32(data_long << offset);
2383 FLAG_Z = data_long & mask_long;
2384 FLAG_V = VFLAG_CLEAR;
2385 FLAG_C = CFLAG_CLEAR;
2387 m68ki_write_32(ea, data_long ^ mask_long);
2389 if((width + offset) > 32)
2390 {
2391 mask_byte = MASK_OUT_ABOVE_8(mask_base);
2392 data_byte = m68ki_read_8(ea+4);
2393 FLAG_Z |= (data_byte & mask_byte);
2394 m68ki_write_8(ea+4, data_byte ^ mask_byte);
2395 }
2396 return;
2397 }
2398 m68ki_exception_illegal();
2399 }
2402 M68KMAKE_OP(bfclr, 32, ., d)
2403 {
2404 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2405 {
2406 uint word2 = OPER_I_16();
2407 uint offset = (word2>>6)&31;
2408 uint width = word2;
2409 uint* data = &DY;
2410 uint64 mask;
2413 if(BIT_B(word2))
2414 offset = REG_D[offset&7];
2415 if(BIT_5(word2))
2416 width = REG_D[width&7];
2419 offset &= 31;
2420 width = ((width-1) & 31) + 1;
2423 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2424 mask = ROR_32(mask, offset);
2426 FLAG_N = NFLAG_32(*data<<offset);
2427 FLAG_Z = *data & mask;
2428 FLAG_V = VFLAG_CLEAR;
2429 FLAG_C = CFLAG_CLEAR;
2431 *data &= ~mask;
2433 return;
2434 }
2435 m68ki_exception_illegal();
2436 }
2439 M68KMAKE_OP(bfclr, 32, ., .)
2440 {
2441 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2442 {
2443 uint word2 = OPER_I_16();
2444 sint offset = (word2>>6)&31;
2445 uint width = word2;
2446 uint mask_base;
2447 uint data_long;
2448 uint mask_long;
2449 uint data_byte = 0;
2450 uint mask_byte = 0;
2451 uint ea = M68KMAKE_GET_EA_AY_8;
2454 if(BIT_B(word2))
2455 offset = MAKE_INT_32(REG_D[offset&7]);
2456 if(BIT_5(word2))
2457 width = REG_D[width&7];
2459 /* Offset is signed so we have to use ugly math =( */
2460 ea += offset / 8;
2461 offset %= 8;
2462 if(offset < 0)
2463 {
2464 offset += 8;
2465 ea--;
2466 }
2467 width = ((width-1) & 31) + 1;
2469 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2470 mask_long = mask_base >> offset;
2472 data_long = m68ki_read_32(ea);
2473 FLAG_N = NFLAG_32(data_long << offset);
2474 FLAG_Z = data_long & mask_long;
2475 FLAG_V = VFLAG_CLEAR;
2476 FLAG_C = CFLAG_CLEAR;
2478 m68ki_write_32(ea, data_long & ~mask_long);
2480 if((width + offset) > 32)
2481 {
2482 mask_byte = MASK_OUT_ABOVE_8(mask_base);
2483 data_byte = m68ki_read_8(ea+4);
2484 FLAG_Z |= (data_byte & mask_byte);
2485 m68ki_write_8(ea+4, data_byte & ~mask_byte);
2486 }
2487 return;
2488 }
2489 m68ki_exception_illegal();
2490 }
2493 M68KMAKE_OP(bfexts, 32, ., d)
2494 {
2495 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2496 {
2497 uint word2 = OPER_I_16();
2498 uint offset = (word2>>6)&31;
2499 uint width = word2;
2500 uint64 data = DY;
2503 if(BIT_B(word2))
2504 offset = REG_D[offset&7];
2505 if(BIT_5(word2))
2506 width = REG_D[width&7];
2508 offset &= 31;
2509 width = ((width-1) & 31) + 1;
2511 data = ROL_32(data, offset);
2512 FLAG_N = NFLAG_32(data);
2513 data = MAKE_INT_32(data) >> (32 - width);
2515 FLAG_Z = data;
2516 FLAG_V = VFLAG_CLEAR;
2517 FLAG_C = CFLAG_CLEAR;
2519 REG_D[(word2>>12)&7] = data;
2521 return;
2522 }
2523 m68ki_exception_illegal();
2524 }
2527 M68KMAKE_OP(bfexts, 32, ., .)
2528 {
2529 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2530 {
2531 uint word2 = OPER_I_16();
2532 sint offset = (word2>>6)&31;
2533 uint width = word2;
2534 uint data;
2535 uint ea = M68KMAKE_GET_EA_AY_8;
2538 if(BIT_B(word2))
2539 offset = MAKE_INT_32(REG_D[offset&7]);
2540 if(BIT_5(word2))
2541 width = REG_D[width&7];
2543 /* Offset is signed so we have to use ugly math =( */
2544 ea += offset / 8;
2545 offset %= 8;
2546 if(offset < 0)
2547 {
2548 offset += 8;
2549 ea--;
2550 }
2551 width = ((width-1) & 31) + 1;
2553 data = m68ki_read_32(ea);
2555 data = MASK_OUT_ABOVE_32(data<<offset);
2557 if((offset+width) > 32)
2558 data |= (m68ki_read_8(ea+4) << offset) >> 8;
2560 FLAG_N = NFLAG_32(data);
2561 data = MAKE_INT_32(data) >> (32 - width);
2563 FLAG_Z = data;
2564 FLAG_V = VFLAG_CLEAR;
2565 FLAG_C = CFLAG_CLEAR;
2567 REG_D[(word2 >> 12) & 7] = data;
2569 return;
2570 }
2571 m68ki_exception_illegal();
2572 }
2575 M68KMAKE_OP(bfextu, 32, ., d)
2576 {
2577 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2578 {
2579 uint word2 = OPER_I_16();
2580 uint offset = (word2>>6)&31;
2581 uint width = word2;
2582 uint64 data = DY;
2585 if(BIT_B(word2))
2586 offset = REG_D[offset&7];
2587 if(BIT_5(word2))
2588 width = REG_D[width&7];
2590 offset &= 31;
2591 width = ((width-1) & 31) + 1;
2593 data = ROL_32(data, offset);
2594 FLAG_N = NFLAG_32(data);
2595 data >>= 32 - width;
2597 FLAG_Z = data;
2598 FLAG_V = VFLAG_CLEAR;
2599 FLAG_C = CFLAG_CLEAR;
2601 REG_D[(word2>>12)&7] = data;
2603 return;
2604 }
2605 m68ki_exception_illegal();
2606 }
2609 M68KMAKE_OP(bfextu, 32, ., .)
2610 {
2611 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2612 {
2613 uint word2 = OPER_I_16();
2614 sint offset = (word2>>6)&31;
2615 uint width = word2;
2616 uint data;
2617 uint ea = M68KMAKE_GET_EA_AY_8;
2620 if(BIT_B(word2))
2621 offset = MAKE_INT_32(REG_D[offset&7]);
2622 if(BIT_5(word2))
2623 width = REG_D[width&7];
2625 /* Offset is signed so we have to use ugly math =( */
2626 ea += offset / 8;
2627 offset %= 8;
2628 if(offset < 0)
2629 {
2630 offset += 8;
2631 ea--;
2632 }
2633 width = ((width-1) & 31) + 1;
2635 data = m68ki_read_32(ea);
2636 data = MASK_OUT_ABOVE_32(data<<offset);
2638 if((offset+width) > 32)
2639 data |= (m68ki_read_8(ea+4) << offset) >> 8;
2641 FLAG_N = NFLAG_32(data);
2642 data >>= (32 - width);
2644 FLAG_Z = data;
2645 FLAG_V = VFLAG_CLEAR;
2646 FLAG_C = CFLAG_CLEAR;
2648 REG_D[(word2 >> 12) & 7] = data;
2650 return;
2651 }
2652 m68ki_exception_illegal();
2653 }
2656 M68KMAKE_OP(bfffo, 32, ., d)
2657 {
2658 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2659 {
2660 uint word2 = OPER_I_16();
2661 uint offset = (word2>>6)&31;
2662 uint width = word2;
2663 uint64 data = DY;
2664 uint bit;
2667 if(BIT_B(word2))
2668 offset = REG_D[offset&7];
2669 if(BIT_5(word2))
2670 width = REG_D[width&7];
2672 offset &= 31;
2673 width = ((width-1) & 31) + 1;
2675 data = ROL_32(data, offset);
2676 FLAG_N = NFLAG_32(data);
2677 data >>= 32 - width;
2679 FLAG_Z = data;
2680 FLAG_V = VFLAG_CLEAR;
2681 FLAG_C = CFLAG_CLEAR;
2683 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
2684 offset++;
2686 REG_D[(word2>>12)&7] = offset;
2688 return;
2689 }
2690 m68ki_exception_illegal();
2691 }
2694 M68KMAKE_OP(bfffo, 32, ., .)
2695 {
2696 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2697 {
2698 uint word2 = OPER_I_16();
2699 sint offset = (word2>>6)&31;
2700 sint local_offset;
2701 uint width = word2;
2702 uint data;
2703 uint bit;
2704 uint ea = M68KMAKE_GET_EA_AY_8;
2707 if(BIT_B(word2))
2708 offset = MAKE_INT_32(REG_D[offset&7]);
2709 if(BIT_5(word2))
2710 width = REG_D[width&7];
2712 /* Offset is signed so we have to use ugly math =( */
2713 ea += offset / 8;
2714 local_offset = offset % 8;
2715 if(local_offset < 0)
2716 {
2717 local_offset += 8;
2718 ea--;
2719 }
2720 width = ((width-1) & 31) + 1;
2722 data = m68ki_read_32(ea);
2723 data = MASK_OUT_ABOVE_32(data<<local_offset);
2725 if((local_offset+width) > 32)
2726 data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
2728 FLAG_N = NFLAG_32(data);
2729 data >>= (32 - width);
2731 FLAG_Z = data;
2732 FLAG_V = VFLAG_CLEAR;
2733 FLAG_C = CFLAG_CLEAR;
2735 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
2736 offset++;
2738 REG_D[(word2>>12)&7] = offset;
2740 return;
2741 }
2742 m68ki_exception_illegal();
2743 }
2746 M68KMAKE_OP(bfins, 32, ., d)
2747 {
2748 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2749 {
2750 uint word2 = OPER_I_16();
2751 uint offset = (word2>>6)&31;
2752 uint width = word2;
2753 uint* data = &DY;
2754 uint64 mask;
2755 uint64 insert = REG_D[(word2>>12)&7];
2758 if(BIT_B(word2))
2759 offset = REG_D[offset&7];
2760 if(BIT_5(word2))
2761 width = REG_D[width&7];
2764 offset &= 31;
2765 width = ((width-1) & 31) + 1;
2768 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2769 mask = ROR_32(mask, offset);
2771 insert = MASK_OUT_ABOVE_32(insert << (32 - width));
2772 FLAG_N = NFLAG_32(insert);
2773 FLAG_Z = insert;
2774 insert = ROR_32(insert, offset);
2776 FLAG_V = VFLAG_CLEAR;
2777 FLAG_C = CFLAG_CLEAR;
2779 *data &= ~mask;
2780 *data |= insert;
2782 return;
2783 }
2784 m68ki_exception_illegal();
2785 }
2788 M68KMAKE_OP(bfins, 32, ., .)
2789 {
2790 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2791 {
2792 uint word2 = OPER_I_16();
2793 sint offset = (word2>>6)&31;
2794 uint width = word2;
2795 uint insert_base = REG_D[(word2>>12)&7];
2796 uint insert_long;
2797 uint insert_byte;
2798 uint mask_base;
2799 uint data_long;
2800 uint mask_long;
2801 uint data_byte = 0;
2802 uint mask_byte = 0;
2803 uint ea = M68KMAKE_GET_EA_AY_8;
2806 if(BIT_B(word2))
2807 offset = MAKE_INT_32(REG_D[offset&7]);
2808 if(BIT_5(word2))
2809 width = REG_D[width&7];
2811 /* Offset is signed so we have to use ugly math =( */
2812 ea += offset / 8;
2813 offset %= 8;
2814 if(offset < 0)
2815 {
2816 offset += 8;
2817 ea--;
2818 }
2819 width = ((width-1) & 31) + 1;
2821 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2822 mask_long = mask_base >> offset;
2824 insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
2825 FLAG_N = NFLAG_32(insert_base);
2826 FLAG_Z = insert_base;
2827 insert_long = insert_base >> offset;
2829 data_long = m68ki_read_32(ea);
2830 FLAG_V = VFLAG_CLEAR;
2831 FLAG_C = CFLAG_CLEAR;
2833 m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
2835 if((width + offset) > 32)
2836 {
2837 mask_byte = MASK_OUT_ABOVE_8(mask_base);
2838 insert_byte = MASK_OUT_ABOVE_8(insert_base);
2839 data_byte = m68ki_read_8(ea+4);
2840 FLAG_Z |= (data_byte & mask_byte);
2841 m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
2842 }
2843 return;
2844 }
2845 m68ki_exception_illegal();
2846 }
2849 M68KMAKE_OP(bfset, 32, ., d)
2850 {
2851 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2852 {
2853 uint word2 = OPER_I_16();
2854 uint offset = (word2>>6)&31;
2855 uint width = word2;
2856 uint* data = &DY;
2857 uint64 mask;
2860 if(BIT_B(word2))
2861 offset = REG_D[offset&7];
2862 if(BIT_5(word2))
2863 width = REG_D[width&7];
2866 offset &= 31;
2867 width = ((width-1) & 31) + 1;
2870 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2871 mask = ROR_32(mask, offset);
2873 FLAG_N = NFLAG_32(*data<<offset);
2874 FLAG_Z = *data & mask;
2875 FLAG_V = VFLAG_CLEAR;
2876 FLAG_C = CFLAG_CLEAR;
2878 *data |= mask;
2880 return;
2881 }
2882 m68ki_exception_illegal();
2883 }
2886 M68KMAKE_OP(bfset, 32, ., .)
2887 {
2888 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2889 {
2890 uint word2 = OPER_I_16();
2891 sint offset = (word2>>6)&31;
2892 uint width = word2;
2893 uint mask_base;
2894 uint data_long;
2895 uint mask_long;
2896 uint data_byte = 0;
2897 uint mask_byte = 0;
2898 uint ea = M68KMAKE_GET_EA_AY_8;
2901 if(BIT_B(word2))
2902 offset = MAKE_INT_32(REG_D[offset&7]);
2903 if(BIT_5(word2))
2904 width = REG_D[width&7];
2906 /* Offset is signed so we have to use ugly math =( */
2907 ea += offset / 8;
2908 offset %= 8;
2909 if(offset < 0)
2910 {
2911 offset += 8;
2912 ea--;
2913 }
2914 width = ((width-1) & 31) + 1;
2917 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2918 mask_long = mask_base >> offset;
2920 data_long = m68ki_read_32(ea);
2921 FLAG_N = NFLAG_32(data_long << offset);
2922 FLAG_Z = data_long & mask_long;
2923 FLAG_V = VFLAG_CLEAR;
2924 FLAG_C = CFLAG_CLEAR;
2926 m68ki_write_32(ea, data_long | mask_long);
2928 if((width + offset) > 32)
2929 {
2930 mask_byte = MASK_OUT_ABOVE_8(mask_base);
2931 data_byte = m68ki_read_8(ea+4);
2932 FLAG_Z |= (data_byte & mask_byte);
2933 m68ki_write_8(ea+4, data_byte | mask_byte);
2934 }
2935 return;
2936 }
2937 m68ki_exception_illegal();
2938 }
2941 M68KMAKE_OP(bftst, 32, ., d)
2942 {
2943 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2944 {
2945 uint word2 = OPER_I_16();
2946 uint offset = (word2>>6)&31;
2947 uint width = word2;
2948 uint* data = &DY;
2949 uint64 mask;
2952 if(BIT_B(word2))
2953 offset = REG_D[offset&7];
2954 if(BIT_5(word2))
2955 width = REG_D[width&7];
2958 offset &= 31;
2959 width = ((width-1) & 31) + 1;
2962 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
2963 mask = ROR_32(mask, offset);
2965 FLAG_N = NFLAG_32(*data<<offset);
2966 FLAG_Z = *data & mask;
2967 FLAG_V = VFLAG_CLEAR;
2968 FLAG_C = CFLAG_CLEAR;
2970 return;
2971 }
2972 m68ki_exception_illegal();
2973 }
2976 M68KMAKE_OP(bftst, 32, ., .)
2977 {
2978 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
2979 {
2980 uint word2 = OPER_I_16();
2981 sint offset = (word2>>6)&31;
2982 uint width = word2;
2983 uint mask_base;
2984 uint data_long;
2985 uint mask_long;
2986 uint data_byte = 0;
2987 uint mask_byte = 0;
2988 uint ea = M68KMAKE_GET_EA_AY_8;
2990 if(BIT_B(word2))
2991 offset = MAKE_INT_32(REG_D[offset&7]);
2992 if(BIT_5(word2))
2993 width = REG_D[width&7];
2995 /* Offset is signed so we have to use ugly math =( */
2996 ea += offset / 8;
2997 offset %= 8;
2998 if(offset < 0)
2999 {
3000 offset += 8;
3001 ea--;
3002 }
3003 width = ((width-1) & 31) + 1;
3006 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
3007 mask_long = mask_base >> offset;
3009 data_long = m68ki_read_32(ea);
3010 FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
3011 FLAG_Z = data_long & mask_long;
3012 FLAG_V = VFLAG_CLEAR;
3013 FLAG_C = CFLAG_CLEAR;
3015 if((width + offset) > 32)
3016 {
3017 mask_byte = MASK_OUT_ABOVE_8(mask_base);
3018 data_byte = m68ki_read_8(ea+4);
3019 FLAG_Z |= (data_byte & mask_byte);
3020 }
3021 return;
3022 }
3023 m68ki_exception_illegal();
3024 }
3027 M68KMAKE_OP(bkpt, 0, ., .)
3028 {
3029 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
3030 {
3031 m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */
3032 }
3033 m68ki_exception_illegal();
3034 }
3037 M68KMAKE_OP(bra, 8, ., .)
3038 {
3039 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3040 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
3041 if(REG_PC == REG_PPC)
3042 USE_ALL_CYCLES();
3043 }
3046 M68KMAKE_OP(bra, 16, ., .)
3047 {
3048 uint offset = OPER_I_16();
3049 REG_PC -= 2;
3050 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3051 m68ki_branch_16(offset);
3052 if(REG_PC == REG_PPC)
3053 USE_ALL_CYCLES();
3054 }
3057 M68KMAKE_OP(bra, 32, ., .)
3058 {
3059 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3060 {
3061 uint offset = OPER_I_32();
3062 REG_PC -= 4;
3063 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3064 m68ki_branch_32(offset);
3065 if(REG_PC == REG_PPC)
3066 USE_ALL_CYCLES();
3067 return;
3068 }
3069 m68ki_exception_illegal();
3070 }
3073 M68KMAKE_OP(bset, 32, r, d)
3074 {
3075 uint* r_dst = &DY;
3076 uint mask = 1 << (DX & 0x1f);
3078 FLAG_Z = *r_dst & mask;
3079 *r_dst |= mask;
3080 }
3083 M68KMAKE_OP(bset, 8, r, .)
3084 {
3085 uint ea = M68KMAKE_GET_EA_AY_8;
3086 uint src = m68ki_read_8(ea);
3087 uint mask = 1 << (DX & 7);
3089 FLAG_Z = src & mask;
3090 m68ki_write_8(ea, src | mask);
3091 }
3094 M68KMAKE_OP(bset, 32, s, d)
3095 {
3096 uint* r_dst = &DY;
3097 uint mask = 1 << (OPER_I_8() & 0x1f);
3099 FLAG_Z = *r_dst & mask;
3100 *r_dst |= mask;
3101 }
3104 M68KMAKE_OP(bset, 8, s, .)
3105 {
3106 uint mask = 1 << (OPER_I_8() & 7);
3107 uint ea = M68KMAKE_GET_EA_AY_8;
3108 uint src = m68ki_read_8(ea);
3110 FLAG_Z = src & mask;
3111 m68ki_write_8(ea, src | mask);
3112 }
3115 M68KMAKE_OP(bsr, 8, ., .)
3116 {
3117 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3118 m68ki_push_32(REG_PC);
3119 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
3120 }
3123 M68KMAKE_OP(bsr, 16, ., .)
3124 {
3125 uint offset = OPER_I_16();
3126 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3127 m68ki_push_32(REG_PC);
3128 REG_PC -= 2;
3129 m68ki_branch_16(offset);
3130 }
3133 M68KMAKE_OP(bsr, 32, ., .)
3134 {
3135 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3136 {
3137 uint offset = OPER_I_32();
3138 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3139 m68ki_push_32(REG_PC);
3140 REG_PC -= 4;
3141 m68ki_branch_32(offset);
3142 return;
3143 }
3144 m68ki_exception_illegal();
3145 }
3148 M68KMAKE_OP(btst, 32, r, d)
3149 {
3150 FLAG_Z = DY & (1 << (DX & 0x1f));
3151 }
3154 M68KMAKE_OP(btst, 8, r, .)
3155 {
3156 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7));
3157 }
3160 M68KMAKE_OP(btst, 32, s, d)
3161 {
3162 FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));
3163 }
3166 M68KMAKE_OP(btst, 8, s, .)
3167 {
3168 uint bit = OPER_I_8() & 7;
3170 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit);
3171 }
3174 M68KMAKE_OP(callm, 32, ., .)
3175 {
3176 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
3177 {
3178 uint ea = M68KMAKE_GET_EA_AY_32;
3180 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3181 REG_PC += 2;
3182 (void)ea; /* just to avoid an 'unused variable' warning */
3183 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
3184 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
3185 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
3186 return;
3187 }
3188 m68ki_exception_illegal();
3189 }
3192 M68KMAKE_OP(cas, 8, ., .)
3193 {
3194 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3195 {
3196 uint word2 = OPER_I_16();
3197 uint ea = M68KMAKE_GET_EA_AY_8;
3198 uint dest = m68ki_read_8(ea);
3199 uint* compare = ®_D[word2 & 7];
3200 uint res = dest - MASK_OUT_ABOVE_8(*compare);
3202 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3203 FLAG_N = NFLAG_8(res);
3204 FLAG_Z = MASK_OUT_ABOVE_8(res);
3205 FLAG_V = VFLAG_SUB_8(*compare, dest, res);
3206 FLAG_C = CFLAG_8(res);
3208 if(COND_NE())
3209 *compare = MASK_OUT_BELOW_8(*compare) | dest;
3210 else
3211 {
3212 USE_CYCLES(3);
3213 m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
3214 }
3215 return;
3216 }
3217 m68ki_exception_illegal();
3218 }
3221 M68KMAKE_OP(cas, 16, ., .)
3222 {
3223 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3224 {
3225 uint word2 = OPER_I_16();
3226 uint ea = M68KMAKE_GET_EA_AY_16;
3227 uint dest = m68ki_read_16(ea);
3228 uint* compare = ®_D[word2 & 7];
3229 uint res = dest - MASK_OUT_ABOVE_16(*compare);
3231 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3232 FLAG_N = NFLAG_16(res);
3233 FLAG_Z = MASK_OUT_ABOVE_16(res);
3234 FLAG_V = VFLAG_SUB_16(*compare, dest, res);
3235 FLAG_C = CFLAG_16(res);
3237 if(COND_NE())
3238 *compare = MASK_OUT_BELOW_16(*compare) | dest;
3239 else
3240 {
3241 USE_CYCLES(3);
3242 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
3243 }
3244 return;
3245 }
3246 m68ki_exception_illegal();
3247 }
3250 M68KMAKE_OP(cas, 32, ., .)
3251 {
3252 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3253 {
3254 uint word2 = OPER_I_16();
3255 uint ea = M68KMAKE_GET_EA_AY_32;
3256 uint dest = m68ki_read_32(ea);
3257 uint* compare = ®_D[word2 & 7];
3258 uint res = dest - *compare;
3260 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3261 FLAG_N = NFLAG_32(res);
3262 FLAG_Z = MASK_OUT_ABOVE_32(res);
3263 FLAG_V = VFLAG_SUB_32(*compare, dest, res);
3264 FLAG_C = CFLAG_SUB_32(*compare, dest, res);
3266 if(COND_NE())
3267 *compare = dest;
3268 else
3269 {
3270 USE_CYCLES(3);
3271 m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
3272 }
3273 return;
3274 }
3275 m68ki_exception_illegal();
3276 }
3279 M68KMAKE_OP(cas2, 16, ., .)
3280 {
3281 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3282 {
3283 uint word2 = OPER_I_32();
3284 uint* compare1 = ®_D[(word2 >> 16) & 7];
3285 uint ea1 = REG_DA[(word2 >> 28) & 15];
3286 uint dest1 = m68ki_read_16(ea1);
3287 uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);
3288 uint* compare2 = ®_D[word2 & 7];
3289 uint ea2 = REG_DA[(word2 >> 12) & 15];
3290 uint dest2 = m68ki_read_16(ea2);
3291 uint res2;
3293 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3294 FLAG_N = NFLAG_16(res1);
3295 FLAG_Z = MASK_OUT_ABOVE_16(res1);
3296 FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1);
3297 FLAG_C = CFLAG_16(res1);
3299 if(COND_EQ())
3300 {
3301 res2 = dest2 - MASK_OUT_ABOVE_16(*compare2);
3303 FLAG_N = NFLAG_16(res2);
3304 FLAG_Z = MASK_OUT_ABOVE_16(res2);
3305 FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2);
3306 FLAG_C = CFLAG_16(res2);
3308 if(COND_EQ())
3309 {
3310 USE_CYCLES(3);
3311 m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]);
3312 m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]);
3313 return;
3314 }
3315 }
3316 *compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1;
3317 *compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;
3318 return;
3319 }
3320 m68ki_exception_illegal();
3321 }
3324 M68KMAKE_OP(cas2, 32, ., .)
3325 {
3326 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3327 {
3328 uint word2 = OPER_I_32();
3329 uint* compare1 = ®_D[(word2 >> 16) & 7];
3330 uint ea1 = REG_DA[(word2 >> 28) & 15];
3331 uint dest1 = m68ki_read_32(ea1);
3332 uint res1 = dest1 - *compare1;
3333 uint* compare2 = ®_D[word2 & 7];
3334 uint ea2 = REG_DA[(word2 >> 12) & 15];
3335 uint dest2 = m68ki_read_32(ea2);
3336 uint res2;
3338 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
3339 FLAG_N = NFLAG_32(res1);
3340 FLAG_Z = MASK_OUT_ABOVE_32(res1);
3341 FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1);
3342 FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1);
3344 if(COND_EQ())
3345 {
3346 res2 = dest2 - *compare2;
3348 FLAG_N = NFLAG_32(res2);
3349 FLAG_Z = MASK_OUT_ABOVE_32(res2);
3350 FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2);
3351 FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2);
3353 if(COND_EQ())
3354 {
3355 USE_CYCLES(3);
3356 m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]);
3357 m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]);
3358 return;
3359 }
3360 }
3361 *compare1 = dest1;
3362 *compare2 = dest2;
3363 return;
3364 }
3365 m68ki_exception_illegal();
3366 }
3369 M68KMAKE_OP(chk, 16, ., d)
3370 {
3371 sint src = MAKE_INT_16(DX);
3372 sint bound = MAKE_INT_16(DY);
3374 if(src >= 0 && src <= bound)
3375 {
3376 return;
3377 }
3378 FLAG_N = (src < 0)<<7;
3379 m68ki_exception_trap(EXCEPTION_CHK);
3380 }
3383 M68KMAKE_OP(chk, 16, ., .)
3384 {
3385 sint src = MAKE_INT_16(DX);
3386 sint bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
3388 if(src >= 0 && src <= bound)
3389 {
3390 return;
3391 }
3392 FLAG_N = (src < 0)<<7;
3393 m68ki_exception_trap(EXCEPTION_CHK);
3394 }
3397 M68KMAKE_OP(chk, 32, ., d)
3398 {
3399 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3400 {
3401 sint src = MAKE_INT_32(DX);
3402 sint bound = MAKE_INT_32(DY);
3404 if(src >= 0 && src <= bound)
3405 {
3406 return;
3407 }
3408 FLAG_N = (src < 0)<<7;
3409 m68ki_exception_trap(EXCEPTION_CHK);
3410 return;
3411 }
3412 m68ki_exception_illegal();
3413 }
3416 M68KMAKE_OP(chk, 32, ., .)
3417 {
3418 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3419 {
3420 sint src = MAKE_INT_32(DX);
3421 sint bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32);
3423 if(src >= 0 && src <= bound)
3424 {
3425 return;
3426 }
3427 FLAG_N = (src < 0)<<7;
3428 m68ki_exception_trap(EXCEPTION_CHK);
3429 return;
3430 }
3431 m68ki_exception_illegal();
3432 }
3435 M68KMAKE_OP(chk2cmp2, 8, ., .)
3436 {
3437 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3438 {
3439 uint word2 = OPER_I_16();
3440 uint compare = REG_DA[(word2 >> 12) & 15];
3441 uint ea = M68KMAKE_GET_EA_AY_8;
3442 uint lower_bound = m68ki_read_8(ea);
3443 uint upper_bound = m68ki_read_8(ea + 1);
3445 if(!BIT_F(word2))
3446 compare = MAKE_INT_8(compare);
3448 FLAG_C = compare - lower_bound;
3449 FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C);
3450 if(COND_CS())
3451 {
3452 if(BIT_B(word2))
3453 m68ki_exception_trap(EXCEPTION_CHK);
3454 return;
3455 }
3457 FLAG_C = upper_bound - compare;
3458 FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C);
3459 if(COND_CS() && BIT_B(word2))
3460 m68ki_exception_trap(EXCEPTION_CHK);
3462 return;
3463 }
3464 m68ki_exception_illegal();
3465 }
3468 M68KMAKE_OP(chk2cmp2, 16, ., .)
3469 {
3470 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3471 {
3472 uint word2 = OPER_I_16();
3473 uint compare = REG_DA[(word2 >> 12) & 15];
3474 uint ea = M68KMAKE_GET_EA_AY_16;
3475 uint lower_bound = m68ki_read_16(ea);
3476 uint upper_bound = m68ki_read_16(ea + 1);
3478 if(!BIT_F(word2))
3479 compare = MAKE_INT_16(compare);
3481 FLAG_C = compare - lower_bound;
3482 FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C);
3483 FLAG_C = CFLAG_16(FLAG_C);
3484 if(COND_CS())
3485 {
3486 if(BIT_B(word2))
3487 m68ki_exception_trap(EXCEPTION_CHK);
3488 return;
3489 }
3491 FLAG_C = upper_bound - compare;
3492 FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C);
3493 FLAG_C = CFLAG_16(FLAG_C);
3494 if(COND_CS() && BIT_B(word2))
3495 m68ki_exception_trap(EXCEPTION_CHK);
3497 return;
3498 }
3499 m68ki_exception_illegal();
3500 }
3503 M68KMAKE_OP(chk2cmp2, 32, ., .)
3504 {
3505 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3506 {
3507 uint word2 = OPER_I_16();
3508 uint compare = REG_DA[(word2 >> 12) & 15];
3509 uint ea = M68KMAKE_GET_EA_AY_32;
3510 uint lower_bound = m68ki_read_32(ea);
3511 uint upper_bound = m68ki_read_32(ea + 1);
3513 FLAG_C = compare - lower_bound;
3514 FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C);
3515 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
3516 if(COND_CS())
3517 {
3518 if(BIT_B(word2))
3519 m68ki_exception_trap(EXCEPTION_CHK);
3520 return;
3521 }
3523 FLAG_C = upper_bound - compare;
3524 FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C);
3525 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
3526 if(COND_CS() && BIT_B(word2))
3527 m68ki_exception_trap(EXCEPTION_CHK);
3529 return;
3530 }
3531 m68ki_exception_illegal();
3532 }
3535 M68KMAKE_OP(clr, 8, ., d)
3536 {
3537 DY &= 0xffffff00;
3539 FLAG_N = NFLAG_CLEAR;
3540 FLAG_V = VFLAG_CLEAR;
3541 FLAG_C = CFLAG_CLEAR;
3542 FLAG_Z = ZFLAG_SET;
3543 }
3546 M68KMAKE_OP(clr, 8, ., .)
3547 {
3548 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
3550 FLAG_N = NFLAG_CLEAR;
3551 FLAG_V = VFLAG_CLEAR;
3552 FLAG_C = CFLAG_CLEAR;
3553 FLAG_Z = ZFLAG_SET;
3554 }
3557 M68KMAKE_OP(clr, 16, ., d)
3558 {
3559 DY &= 0xffff0000;
3561 FLAG_N = NFLAG_CLEAR;
3562 FLAG_V = VFLAG_CLEAR;
3563 FLAG_C = CFLAG_CLEAR;
3564 FLAG_Z = ZFLAG_SET;
3565 }
3568 M68KMAKE_OP(clr, 16, ., .)
3569 {
3570 m68ki_write_16(M68KMAKE_GET_EA_AY_16, 0);
3572 FLAG_N = NFLAG_CLEAR;
3573 FLAG_V = VFLAG_CLEAR;
3574 FLAG_C = CFLAG_CLEAR;
3575 FLAG_Z = ZFLAG_SET;
3576 }
3579 M68KMAKE_OP(clr, 32, ., d)
3580 {
3581 DY = 0;
3583 FLAG_N = NFLAG_CLEAR;
3584 FLAG_V = VFLAG_CLEAR;
3585 FLAG_C = CFLAG_CLEAR;
3586 FLAG_Z = ZFLAG_SET;
3587 }
3590 M68KMAKE_OP(clr, 32, ., .)
3591 {
3592 m68ki_write_32(M68KMAKE_GET_EA_AY_32, 0);
3594 FLAG_N = NFLAG_CLEAR;
3595 FLAG_V = VFLAG_CLEAR;
3596 FLAG_C = CFLAG_CLEAR;
3597 FLAG_Z = ZFLAG_SET;
3598 }
3601 M68KMAKE_OP(cmp, 8, ., d)
3602 {
3603 uint src = MASK_OUT_ABOVE_8(DY);
3604 uint dst = MASK_OUT_ABOVE_8(DX);
3605 uint res = dst - src;
3607 FLAG_N = NFLAG_8(res);
3608 FLAG_Z = MASK_OUT_ABOVE_8(res);
3609 FLAG_V = VFLAG_SUB_8(src, dst, res);
3610 FLAG_C = CFLAG_8(res);
3611 }
3614 M68KMAKE_OP(cmp, 8, ., .)
3615 {
3616 uint src = M68KMAKE_GET_OPER_AY_8;
3617 uint dst = MASK_OUT_ABOVE_8(DX);
3618 uint res = dst - src;
3620 FLAG_N = NFLAG_8(res);
3621 FLAG_Z = MASK_OUT_ABOVE_8(res);
3622 FLAG_V = VFLAG_SUB_8(src, dst, res);
3623 FLAG_C = CFLAG_8(res);
3624 }
3627 M68KMAKE_OP(cmp, 16, ., d)
3628 {
3629 uint src = MASK_OUT_ABOVE_16(DY);
3630 uint dst = MASK_OUT_ABOVE_16(DX);
3631 uint res = dst - src;
3633 FLAG_N = NFLAG_16(res);
3634 FLAG_Z = MASK_OUT_ABOVE_16(res);
3635 FLAG_V = VFLAG_SUB_16(src, dst, res);
3636 FLAG_C = CFLAG_16(res);
3637 }
3640 M68KMAKE_OP(cmp, 16, ., a)
3641 {
3642 uint src = MASK_OUT_ABOVE_16(AY);
3643 uint dst = MASK_OUT_ABOVE_16(DX);
3644 uint res = dst - src;
3646 FLAG_N = NFLAG_16(res);
3647 FLAG_Z = MASK_OUT_ABOVE_16(res);
3648 FLAG_V = VFLAG_SUB_16(src, dst, res);
3649 FLAG_C = CFLAG_16(res);
3650 }
3653 M68KMAKE_OP(cmp, 16, ., .)
3654 {
3655 uint src = M68KMAKE_GET_OPER_AY_16;
3656 uint dst = MASK_OUT_ABOVE_16(DX);
3657 uint res = dst - src;
3659 FLAG_N = NFLAG_16(res);
3660 FLAG_Z = MASK_OUT_ABOVE_16(res);
3661 FLAG_V = VFLAG_SUB_16(src, dst, res);
3662 FLAG_C = CFLAG_16(res);
3663 }
3666 M68KMAKE_OP(cmp, 32, ., d)
3667 {
3668 uint src = DY;
3669 uint dst = DX;
3670 uint res = dst - src;
3672 FLAG_N = NFLAG_32(res);
3673 FLAG_Z = MASK_OUT_ABOVE_32(res);
3674 FLAG_V = VFLAG_SUB_32(src, dst, res);
3675 FLAG_C = CFLAG_SUB_32(src, dst, res);
3676 }
3679 M68KMAKE_OP(cmp, 32, ., a)
3680 {
3681 uint src = AY;
3682 uint dst = DX;
3683 uint res = dst - src;
3685 FLAG_N = NFLAG_32(res);
3686 FLAG_Z = MASK_OUT_ABOVE_32(res);
3687 FLAG_V = VFLAG_SUB_32(src, dst, res);
3688 FLAG_C = CFLAG_SUB_32(src, dst, res);
3689 }
3692 M68KMAKE_OP(cmp, 32, ., .)
3693 {
3694 uint src = M68KMAKE_GET_OPER_AY_32;
3695 uint dst = DX;
3696 uint res = dst - src;
3698 FLAG_N = NFLAG_32(res);
3699 FLAG_Z = MASK_OUT_ABOVE_32(res);
3700 FLAG_V = VFLAG_SUB_32(src, dst, res);
3701 FLAG_C = CFLAG_SUB_32(src, dst, res);
3702 }
3705 M68KMAKE_OP(cmpa, 16, ., d)
3706 {
3707 uint src = MAKE_INT_16(DY);
3708 uint dst = AX;
3709 uint res = dst - src;
3711 FLAG_N = NFLAG_32(res);
3712 FLAG_Z = MASK_OUT_ABOVE_32(res);
3713 FLAG_V = VFLAG_SUB_32(src, dst, res);
3714 FLAG_C = CFLAG_SUB_32(src, dst, res);
3715 }
3718 M68KMAKE_OP(cmpa, 16, ., a)
3719 {
3720 uint src = MAKE_INT_16(AY);
3721 uint dst = AX;
3722 uint res = dst - src;
3724 FLAG_N = NFLAG_32(res);
3725 FLAG_Z = MASK_OUT_ABOVE_32(res);
3726 FLAG_V = VFLAG_SUB_32(src, dst, res);
3727 FLAG_C = CFLAG_SUB_32(src, dst, res);
3728 }
3731 M68KMAKE_OP(cmpa, 16, ., .)
3732 {
3733 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
3734 uint dst = AX;
3735 uint res = dst - src;
3737 FLAG_N = NFLAG_32(res);
3738 FLAG_Z = MASK_OUT_ABOVE_32(res);
3739 FLAG_V = VFLAG_SUB_32(src, dst, res);
3740 FLAG_C = CFLAG_SUB_32(src, dst, res);
3741 }
3744 M68KMAKE_OP(cmpa, 32, ., d)
3745 {
3746 uint src = DY;
3747 uint dst = AX;
3748 uint res = dst - src;
3750 FLAG_N = NFLAG_32(res);
3751 FLAG_Z = MASK_OUT_ABOVE_32(res);
3752 FLAG_V = VFLAG_SUB_32(src, dst, res);
3753 FLAG_C = CFLAG_SUB_32(src, dst, res);
3754 }
3757 M68KMAKE_OP(cmpa, 32, ., a)
3758 {
3759 uint src = AY;
3760 uint dst = AX;
3761 uint res = dst - src;
3763 FLAG_N = NFLAG_32(res);
3764 FLAG_Z = MASK_OUT_ABOVE_32(res);
3765 FLAG_V = VFLAG_SUB_32(src, dst, res);
3766 FLAG_C = CFLAG_SUB_32(src, dst, res);
3767 }
3770 M68KMAKE_OP(cmpa, 32, ., .)
3771 {
3772 uint src = M68KMAKE_GET_OPER_AY_32;
3773 uint dst = AX;
3774 uint res = dst - src;
3776 FLAG_N = NFLAG_32(res);
3777 FLAG_Z = MASK_OUT_ABOVE_32(res);
3778 FLAG_V = VFLAG_SUB_32(src, dst, res);
3779 FLAG_C = CFLAG_SUB_32(src, dst, res);
3780 }
3783 M68KMAKE_OP(cmpi, 8, ., d)
3784 {
3785 uint src = OPER_I_8();
3786 uint dst = MASK_OUT_ABOVE_8(DY);
3787 uint res = dst - src;
3789 FLAG_N = NFLAG_8(res);
3790 FLAG_Z = MASK_OUT_ABOVE_8(res);
3791 FLAG_V = VFLAG_SUB_8(src, dst, res);
3792 FLAG_C = CFLAG_8(res);
3793 }
3796 M68KMAKE_OP(cmpi, 8, ., .)
3797 {
3798 uint src = OPER_I_8();
3799 uint dst = M68KMAKE_GET_OPER_AY_8;
3800 uint res = dst - src;
3802 FLAG_N = NFLAG_8(res);
3803 FLAG_Z = MASK_OUT_ABOVE_8(res);
3804 FLAG_V = VFLAG_SUB_8(src, dst, res);
3805 FLAG_C = CFLAG_8(res);
3806 }
3809 M68KMAKE_OP(cmpi, 8, ., pcdi)
3810 {
3811 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3812 {
3813 uint src = OPER_I_8();
3814 uint dst = OPER_PCDI_8();
3815 uint res = dst - src;
3817 FLAG_N = NFLAG_8(res);
3818 FLAG_Z = MASK_OUT_ABOVE_8(res);
3819 FLAG_V = VFLAG_SUB_8(src, dst, res);
3820 FLAG_C = CFLAG_8(res);
3821 return;
3822 }
3823 m68ki_exception_illegal();
3824 }
3827 M68KMAKE_OP(cmpi, 8, ., pcix)
3828 {
3829 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3830 {
3831 uint src = OPER_I_8();
3832 uint dst = OPER_PCIX_8();
3833 uint res = dst - src;
3835 FLAG_N = NFLAG_8(res);
3836 FLAG_Z = MASK_OUT_ABOVE_8(res);
3837 FLAG_V = VFLAG_SUB_8(src, dst, res);
3838 FLAG_C = CFLAG_8(res);
3839 return;
3840 }
3841 m68ki_exception_illegal();
3842 }
3845 M68KMAKE_OP(cmpi, 16, ., d)
3846 {
3847 uint src = OPER_I_16();
3848 uint dst = MASK_OUT_ABOVE_16(DY);
3849 uint res = dst - src;
3851 FLAG_N = NFLAG_16(res);
3852 FLAG_Z = MASK_OUT_ABOVE_16(res);
3853 FLAG_V = VFLAG_SUB_16(src, dst, res);
3854 FLAG_C = CFLAG_16(res);
3855 }
3858 M68KMAKE_OP(cmpi, 16, ., .)
3859 {
3860 uint src = OPER_I_16();
3861 uint dst = M68KMAKE_GET_OPER_AY_16;
3862 uint res = dst - src;
3864 FLAG_N = NFLAG_16(res);
3865 FLAG_Z = MASK_OUT_ABOVE_16(res);
3866 FLAG_V = VFLAG_SUB_16(src, dst, res);
3867 FLAG_C = CFLAG_16(res);
3868 }
3871 M68KMAKE_OP(cmpi, 16, ., pcdi)
3872 {
3873 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3874 {
3875 uint src = OPER_I_16();
3876 uint dst = OPER_PCDI_16();
3877 uint res = dst - src;
3879 FLAG_N = NFLAG_16(res);
3880 FLAG_Z = MASK_OUT_ABOVE_16(res);
3881 FLAG_V = VFLAG_SUB_16(src, dst, res);
3882 FLAG_C = CFLAG_16(res);
3883 return;
3884 }
3885 m68ki_exception_illegal();
3886 }
3889 M68KMAKE_OP(cmpi, 16, ., pcix)
3890 {
3891 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3892 {
3893 uint src = OPER_I_16();
3894 uint dst = OPER_PCIX_16();
3895 uint res = dst - src;
3897 FLAG_N = NFLAG_16(res);
3898 FLAG_Z = MASK_OUT_ABOVE_16(res);
3899 FLAG_V = VFLAG_SUB_16(src, dst, res);
3900 FLAG_C = CFLAG_16(res);
3901 return;
3902 }
3903 m68ki_exception_illegal();
3904 }
3907 M68KMAKE_OP(cmpi, 32, ., d)
3908 {
3909 uint src = OPER_I_32();
3910 uint dst = DY;
3911 uint res = dst - src;
3913 FLAG_N = NFLAG_32(res);
3914 FLAG_Z = MASK_OUT_ABOVE_32(res);
3915 FLAG_V = VFLAG_SUB_32(src, dst, res);
3916 FLAG_C = CFLAG_SUB_32(src, dst, res);
3917 }
3920 M68KMAKE_OP(cmpi, 32, ., .)
3921 {
3922 uint src = OPER_I_32();
3923 uint dst = M68KMAKE_GET_OPER_AY_32;
3924 uint res = dst - src;
3926 FLAG_N = NFLAG_32(res);
3927 FLAG_Z = MASK_OUT_ABOVE_32(res);
3928 FLAG_V = VFLAG_SUB_32(src, dst, res);
3929 FLAG_C = CFLAG_SUB_32(src, dst, res);
3930 }
3933 M68KMAKE_OP(cmpi, 32, ., pcdi)
3934 {
3935 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3936 {
3937 uint src = OPER_I_32();
3938 uint dst = OPER_PCDI_32();
3939 uint res = dst - src;
3941 FLAG_N = NFLAG_32(res);
3942 FLAG_Z = MASK_OUT_ABOVE_32(res);
3943 FLAG_V = VFLAG_SUB_32(src, dst, res);
3944 FLAG_C = CFLAG_SUB_32(src, dst, res);
3945 return;
3946 }
3947 m68ki_exception_illegal();
3948 }
3951 M68KMAKE_OP(cmpi, 32, ., pcix)
3952 {
3953 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
3954 {
3955 uint src = OPER_I_32();
3956 uint dst = OPER_PCIX_32();
3957 uint res = dst - src;
3959 FLAG_N = NFLAG_32(res);
3960 FLAG_Z = MASK_OUT_ABOVE_32(res);
3961 FLAG_V = VFLAG_SUB_32(src, dst, res);
3962 FLAG_C = CFLAG_SUB_32(src, dst, res);
3963 return;
3964 }
3965 m68ki_exception_illegal();
3966 }
3969 M68KMAKE_OP(cmpm, 8, ., ax7)
3970 {
3971 uint src = OPER_AY_PI_8();
3972 uint dst = OPER_A7_PI_8();
3973 uint res = dst - src;
3975 FLAG_N = NFLAG_8(res);
3976 FLAG_Z = MASK_OUT_ABOVE_8(res);
3977 FLAG_V = VFLAG_SUB_8(src, dst, res);
3978 FLAG_C = CFLAG_8(res);
3979 }
3982 M68KMAKE_OP(cmpm, 8, ., ay7)
3983 {
3984 uint src = OPER_A7_PI_8();
3985 uint dst = OPER_AX_PI_8();
3986 uint res = dst - src;
3988 FLAG_N = NFLAG_8(res);
3989 FLAG_Z = MASK_OUT_ABOVE_8(res);
3990 FLAG_V = VFLAG_SUB_8(src, dst, res);
3991 FLAG_C = CFLAG_8(res);
3992 }
3995 M68KMAKE_OP(cmpm, 8, ., axy7)
3996 {
3997 uint src = OPER_A7_PI_8();
3998 uint dst = OPER_A7_PI_8();
3999 uint res = dst - src;
4001 FLAG_N = NFLAG_8(res);
4002 FLAG_Z = MASK_OUT_ABOVE_8(res);
4003 FLAG_V = VFLAG_SUB_8(src, dst, res);
4004 FLAG_C = CFLAG_8(res);
4005 }
4008 M68KMAKE_OP(cmpm, 8, ., .)
4009 {
4010 uint src = OPER_AY_PI_8();
4011 uint dst = OPER_AX_PI_8();
4012 uint res = dst - src;
4014 FLAG_N = NFLAG_8(res);
4015 FLAG_Z = MASK_OUT_ABOVE_8(res);
4016 FLAG_V = VFLAG_SUB_8(src, dst, res);
4017 FLAG_C = CFLAG_8(res);
4018 }
4021 M68KMAKE_OP(cmpm, 16, ., .)
4022 {
4023 uint src = OPER_AY_PI_16();
4024 uint dst = OPER_AX_PI_16();
4025 uint res = dst - src;
4027 FLAG_N = NFLAG_16(res);
4028 FLAG_Z = MASK_OUT_ABOVE_16(res);
4029 FLAG_V = VFLAG_SUB_16(src, dst, res);
4030 FLAG_C = CFLAG_16(res);
4031 }
4034 M68KMAKE_OP(cmpm, 32, ., .)
4035 {
4036 uint src = OPER_AY_PI_32();
4037 uint dst = OPER_AX_PI_32();
4038 uint res = dst - src;
4040 FLAG_N = NFLAG_32(res);
4041 FLAG_Z = MASK_OUT_ABOVE_32(res);
4042 FLAG_V = VFLAG_SUB_32(src, dst, res);
4043 FLAG_C = CFLAG_SUB_32(src, dst, res);
4044 }
4047 M68KMAKE_OP(cpbcc, 32, ., .)
4048 {
4049 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4050 {
4051 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4052 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4053 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4054 return;
4055 }
4056 m68ki_exception_1111();
4057 }
4060 M68KMAKE_OP(cpdbcc, 32, ., .)
4061 {
4062 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4063 {
4064 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4065 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4066 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4067 return;
4068 }
4069 m68ki_exception_1111();
4070 }
4073 M68KMAKE_OP(cpgen, 32, ., .)
4074 {
4075 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4076 {
4077 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4078 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4079 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4080 return;
4081 }
4082 m68ki_exception_1111();
4083 }
4086 M68KMAKE_OP(cpscc, 32, ., .)
4087 {
4088 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4089 {
4090 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4091 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4092 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4093 return;
4094 }
4095 m68ki_exception_1111();
4096 }
4099 M68KMAKE_OP(cptrapcc, 32, ., .)
4100 {
4101 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4102 {
4103 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
4104 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
4105 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
4106 return;
4107 }
4108 m68ki_exception_1111();
4109 }
4112 M68KMAKE_OP(dbt, 16, ., .)
4113 {
4114 REG_PC += 2;
4115 }
4118 M68KMAKE_OP(dbf, 16, ., .)
4119 {
4120 uint* r_dst = &DY;
4121 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
4123 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
4124 if(res != 0xffff)
4125 {
4126 uint offset = OPER_I_16();
4127 REG_PC -= 2;
4128 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
4129 m68ki_branch_16(offset);
4130 return;
4131 }
4132 REG_PC += 2;
4133 }
4136 M68KMAKE_OP(dbcc, 16, ., .)
4137 {
4138 if(M68KMAKE_NOT_CC)
4139 {
4140 uint* r_dst = &DY;
4141 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
4143 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
4144 if(res != 0xffff)
4145 {
4146 uint offset = OPER_I_16();
4147 REG_PC -= 2;
4148 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
4149 m68ki_branch_16(offset);
4150 USE_CYCLES(CYC_DBCC_F_NOEXP);
4151 return;
4152 }
4153 REG_PC += 2;
4154 USE_CYCLES(CYC_DBCC_F_EXP);
4155 return;
4156 }
4157 REG_PC += 2;
4158 }
4161 M68KMAKE_OP(divs, 16, ., d)
4162 {
4163 uint* r_dst = &DX;
4164 sint src = MAKE_INT_16(DY);
4165 sint quotient;
4166 sint remainder;
4168 if(src != 0)
4169 {
4170 if((uint32)*r_dst == 0x80000000 && src == -1)
4171 {
4172 FLAG_Z = 0;
4173 FLAG_N = NFLAG_CLEAR;
4174 FLAG_V = VFLAG_CLEAR;
4175 FLAG_C = CFLAG_CLEAR;
4176 *r_dst = 0;
4177 return;
4178 }
4180 quotient = MAKE_INT_32(*r_dst) / src;
4181 remainder = MAKE_INT_32(*r_dst) % src;
4183 if(quotient == MAKE_INT_16(quotient))
4184 {
4185 FLAG_Z = quotient;
4186 FLAG_N = NFLAG_16(quotient);
4187 FLAG_V = VFLAG_CLEAR;
4188 FLAG_C = CFLAG_CLEAR;
4189 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4190 return;
4191 }
4192 FLAG_V = VFLAG_SET;
4193 return;
4194 }
4195 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4196 }
4199 M68KMAKE_OP(divs, 16, ., .)
4200 {
4201 uint* r_dst = &DX;
4202 sint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
4203 sint quotient;
4204 sint remainder;
4206 if(src != 0)
4207 {
4208 if((uint32)*r_dst == 0x80000000 && src == -1)
4209 {
4210 FLAG_Z = 0;
4211 FLAG_N = NFLAG_CLEAR;
4212 FLAG_V = VFLAG_CLEAR;
4213 FLAG_C = CFLAG_CLEAR;
4214 *r_dst = 0;
4215 return;
4216 }
4218 quotient = MAKE_INT_32(*r_dst) / src;
4219 remainder = MAKE_INT_32(*r_dst) % src;
4221 if(quotient == MAKE_INT_16(quotient))
4222 {
4223 FLAG_Z = quotient;
4224 FLAG_N = NFLAG_16(quotient);
4225 FLAG_V = VFLAG_CLEAR;
4226 FLAG_C = CFLAG_CLEAR;
4227 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4228 return;
4229 }
4230 FLAG_V = VFLAG_SET;
4231 return;
4232 }
4233 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4234 }
4237 M68KMAKE_OP(divu, 16, ., d)
4238 {
4239 uint* r_dst = &DX;
4240 uint src = MASK_OUT_ABOVE_16(DY);
4242 if(src != 0)
4243 {
4244 uint quotient = *r_dst / src;
4245 uint remainder = *r_dst % src;
4247 if(quotient < 0x10000)
4248 {
4249 FLAG_Z = quotient;
4250 FLAG_N = NFLAG_16(quotient);
4251 FLAG_V = VFLAG_CLEAR;
4252 FLAG_C = CFLAG_CLEAR;
4253 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4254 return;
4255 }
4256 FLAG_V = VFLAG_SET;
4257 return;
4258 }
4259 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4260 }
4263 M68KMAKE_OP(divu, 16, ., .)
4264 {
4265 uint* r_dst = &DX;
4266 uint src = M68KMAKE_GET_OPER_AY_16;
4268 if(src != 0)
4269 {
4270 uint quotient = *r_dst / src;
4271 uint remainder = *r_dst % src;
4273 if(quotient < 0x10000)
4274 {
4275 FLAG_Z = quotient;
4276 FLAG_N = NFLAG_16(quotient);
4277 FLAG_V = VFLAG_CLEAR;
4278 FLAG_C = CFLAG_CLEAR;
4279 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
4280 return;
4281 }
4282 FLAG_V = VFLAG_SET;
4283 return;
4284 }
4285 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4286 }
4289 M68KMAKE_OP(divl, 32, ., d)
4290 {
4291 #if M68K_USE_64_BIT
4293 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4294 {
4295 uint word2 = OPER_I_16();
4296 uint64 divisor = DY;
4297 uint64 dividend = 0;
4298 uint64 quotient = 0;
4299 uint64 remainder = 0;
4301 if(divisor != 0)
4302 {
4303 if(BIT_A(word2)) /* 64 bit */
4304 {
4305 dividend = REG_D[word2 & 7];
4306 dividend <<= 32;
4307 dividend |= REG_D[(word2 >> 12) & 7];
4309 if(BIT_B(word2)) /* signed */
4310 {
4311 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
4312 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
4313 if((sint64)quotient != (sint64)((sint32)quotient))
4314 {
4315 FLAG_V = VFLAG_SET;
4316 return;
4317 }
4318 }
4319 else /* unsigned */
4320 {
4321 quotient = dividend / divisor;
4322 if(quotient > 0xffffffff)
4323 {
4324 FLAG_V = VFLAG_SET;
4325 return;
4326 }
4327 remainder = dividend % divisor;
4328 }
4329 }
4330 else /* 32 bit */
4331 {
4332 dividend = REG_D[(word2 >> 12) & 7];
4333 if(BIT_B(word2)) /* signed */
4334 {
4335 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
4336 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
4337 }
4338 else /* unsigned */
4339 {
4340 quotient = dividend / divisor;
4341 remainder = dividend % divisor;
4342 }
4343 }
4345 REG_D[word2 & 7] = remainder;
4346 REG_D[(word2 >> 12) & 7] = quotient;
4348 FLAG_N = NFLAG_32(quotient);
4349 FLAG_Z = quotient;
4350 FLAG_V = VFLAG_CLEAR;
4351 FLAG_C = CFLAG_CLEAR;
4352 return;
4353 }
4354 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4355 return;
4356 }
4357 m68ki_exception_illegal();
4359 #else
4361 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4362 {
4363 uint word2 = OPER_I_16();
4364 uint divisor = DY;
4365 uint dividend_hi = REG_D[word2 & 7];
4366 uint dividend_lo = REG_D[(word2 >> 12) & 7];
4367 uint quotient = 0;
4368 uint remainder = 0;
4369 uint dividend_neg = 0;
4370 uint divisor_neg = 0;
4371 sint i;
4372 uint overflow;
4374 if(divisor != 0)
4375 {
4376 /* quad / long : long quotient, long remainder */
4377 if(BIT_A(word2))
4378 {
4379 if(BIT_B(word2)) /* signed */
4380 {
4381 /* special case in signed divide */
4382 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
4383 {
4384 REG_D[word2 & 7] = 0;
4385 REG_D[(word2 >> 12) & 7] = 0x80000000;
4387 FLAG_N = NFLAG_SET;
4388 FLAG_Z = ZFLAG_CLEAR;
4389 FLAG_V = VFLAG_CLEAR;
4390 FLAG_C = CFLAG_CLEAR;
4391 return;
4392 }
4393 if(GET_MSB_32(dividend_hi))
4394 {
4395 dividend_neg = 1;
4396 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
4397 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
4398 }
4399 if(GET_MSB_32(divisor))
4400 {
4401 divisor_neg = 1;
4402 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
4404 }
4405 }
4407 /* if the upper long is greater than the divisor, we're overflowing. */
4408 if(dividend_hi >= divisor)
4409 {
4410 FLAG_V = VFLAG_SET;
4411 return;
4412 }
4414 for(i = 31; i >= 0; i--)
4415 {
4416 quotient <<= 1;
4417 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
4418 if(remainder >= divisor)
4419 {
4420 remainder -= divisor;
4421 quotient++;
4422 }
4423 }
4424 for(i = 31; i >= 0; i--)
4425 {
4426 quotient <<= 1;
4427 overflow = GET_MSB_32(remainder);
4428 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
4429 if(remainder >= divisor || overflow)
4430 {
4431 remainder -= divisor;
4432 quotient++;
4433 }
4434 }
4436 if(BIT_B(word2)) /* signed */
4437 {
4438 if(quotient > 0x7fffffff)
4439 {
4440 FLAG_V = VFLAG_SET;
4441 return;
4442 }
4443 if(dividend_neg)
4444 {
4445 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
4446 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
4447 }
4448 if(divisor_neg)
4449 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
4450 }
4452 REG_D[word2 & 7] = remainder;
4453 REG_D[(word2 >> 12) & 7] = quotient;
4455 FLAG_N = NFLAG_32(quotient);
4456 FLAG_Z = quotient;
4457 FLAG_V = VFLAG_CLEAR;
4458 FLAG_C = CFLAG_CLEAR;
4459 return;
4460 }
4462 /* long / long: long quotient, maybe long remainder */
4463 if(BIT_B(word2)) /* signed */
4464 {
4465 /* Special case in divide */
4466 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
4467 {
4468 FLAG_N = NFLAG_SET;
4469 FLAG_Z = ZFLAG_CLEAR;
4470 FLAG_V = VFLAG_CLEAR;
4471 FLAG_C = CFLAG_CLEAR;
4472 REG_D[(word2 >> 12) & 7] = 0x80000000;
4473 REG_D[word2 & 7] = 0;
4474 return;
4475 }
4476 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
4477 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
4478 }
4479 else
4480 {
4481 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
4482 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
4483 }
4485 FLAG_N = NFLAG_32(quotient);
4486 FLAG_Z = quotient;
4487 FLAG_V = VFLAG_CLEAR;
4488 FLAG_C = CFLAG_CLEAR;
4489 return;
4490 }
4491 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4492 return;
4493 }
4494 m68ki_exception_illegal();
4496 #endif
4497 }
4500 M68KMAKE_OP(divl, 32, ., .)
4501 {
4502 #if M68K_USE_64_BIT
4504 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4505 {
4506 uint word2 = OPER_I_16();
4507 uint64 divisor = M68KMAKE_GET_OPER_AY_32;
4508 uint64 dividend = 0;
4509 uint64 quotient = 0;
4510 uint64 remainder = 0;
4512 if(divisor != 0)
4513 {
4514 if(BIT_A(word2)) /* 64 bit */
4515 {
4516 dividend = REG_D[word2 & 7];
4517 dividend <<= 32;
4518 dividend |= REG_D[(word2 >> 12) & 7];
4520 if(BIT_B(word2)) /* signed */
4521 {
4522 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
4523 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
4524 if((sint64)quotient != (sint64)((sint32)quotient))
4525 {
4526 FLAG_V = VFLAG_SET;
4527 return;
4528 }
4529 }
4530 else /* unsigned */
4531 {
4532 quotient = dividend / divisor;
4533 if(quotient > 0xffffffff)
4534 {
4535 FLAG_V = VFLAG_SET;
4536 return;
4537 }
4538 remainder = dividend % divisor;
4539 }
4540 }
4541 else /* 32 bit */
4542 {
4543 dividend = REG_D[(word2 >> 12) & 7];
4544 if(BIT_B(word2)) /* signed */
4545 {
4546 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
4547 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
4548 }
4549 else /* unsigned */
4550 {
4551 quotient = dividend / divisor;
4552 remainder = dividend % divisor;
4553 }
4554 }
4556 REG_D[word2 & 7] = remainder;
4557 REG_D[(word2 >> 12) & 7] = quotient;
4559 FLAG_N = NFLAG_32(quotient);
4560 FLAG_Z = quotient;
4561 FLAG_V = VFLAG_CLEAR;
4562 FLAG_C = CFLAG_CLEAR;
4563 return;
4564 }
4565 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4566 return;
4567 }
4568 m68ki_exception_illegal();
4570 #else
4572 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4573 {
4574 uint word2 = OPER_I_16();
4575 uint divisor = M68KMAKE_GET_OPER_AY_32;
4576 uint dividend_hi = REG_D[word2 & 7];
4577 uint dividend_lo = REG_D[(word2 >> 12) & 7];
4578 uint quotient = 0;
4579 uint remainder = 0;
4580 uint dividend_neg = 0;
4581 uint divisor_neg = 0;
4582 sint i;
4583 uint overflow;
4585 if(divisor != 0)
4586 {
4587 /* quad / long : long quotient, long remainder */
4588 if(BIT_A(word2))
4589 {
4590 if(BIT_B(word2)) /* signed */
4591 {
4592 /* special case in signed divide */
4593 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
4594 {
4595 REG_D[word2 & 7] = 0;
4596 REG_D[(word2 >> 12) & 7] = 0x80000000;
4598 FLAG_N = NFLAG_SET;
4599 FLAG_Z = ZFLAG_CLEAR;
4600 FLAG_V = VFLAG_CLEAR;
4601 FLAG_C = CFLAG_CLEAR;
4602 return;
4603 }
4604 if(GET_MSB_32(dividend_hi))
4605 {
4606 dividend_neg = 1;
4607 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
4608 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
4609 }
4610 if(GET_MSB_32(divisor))
4611 {
4612 divisor_neg = 1;
4613 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
4615 }
4616 }
4618 /* if the upper long is greater than the divisor, we're overflowing. */
4619 if(dividend_hi >= divisor)
4620 {
4621 FLAG_V = VFLAG_SET;
4622 return;
4623 }
4625 for(i = 31; i >= 0; i--)
4626 {
4627 quotient <<= 1;
4628 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
4629 if(remainder >= divisor)
4630 {
4631 remainder -= divisor;
4632 quotient++;
4633 }
4634 }
4635 for(i = 31; i >= 0; i--)
4636 {
4637 quotient <<= 1;
4638 overflow = GET_MSB_32(remainder);
4639 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
4640 if(remainder >= divisor || overflow)
4641 {
4642 remainder -= divisor;
4643 quotient++;
4644 }
4645 }
4647 if(BIT_B(word2)) /* signed */
4648 {
4649 if(quotient > 0x7fffffff)
4650 {
4651 FLAG_V = VFLAG_SET;
4652 return;
4653 }
4654 if(dividend_neg)
4655 {
4656 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
4657 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
4658 }
4659 if(divisor_neg)
4660 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
4661 }
4663 REG_D[word2 & 7] = remainder;
4664 REG_D[(word2 >> 12) & 7] = quotient;
4666 FLAG_N = NFLAG_32(quotient);
4667 FLAG_Z = quotient;
4668 FLAG_V = VFLAG_CLEAR;
4669 FLAG_C = CFLAG_CLEAR;
4670 return;
4671 }
4673 /* long / long: long quotient, maybe long remainder */
4674 if(BIT_B(word2)) /* signed */
4675 {
4676 /* Special case in divide */
4677 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
4678 {
4679 FLAG_N = NFLAG_SET;
4680 FLAG_Z = ZFLAG_CLEAR;
4681 FLAG_V = VFLAG_CLEAR;
4682 FLAG_C = CFLAG_CLEAR;
4683 REG_D[(word2 >> 12) & 7] = 0x80000000;
4684 REG_D[word2 & 7] = 0;
4685 return;
4686 }
4687 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
4688 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
4689 }
4690 else
4691 {
4692 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
4693 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
4694 }
4696 FLAG_N = NFLAG_32(quotient);
4697 FLAG_Z = quotient;
4698 FLAG_V = VFLAG_CLEAR;
4699 FLAG_C = CFLAG_CLEAR;
4700 return;
4701 }
4702 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
4703 return;
4704 }
4705 m68ki_exception_illegal();
4707 #endif
4708 }
4711 M68KMAKE_OP(eor, 8, ., d)
4712 {
4713 uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));
4715 FLAG_N = NFLAG_8(res);
4716 FLAG_Z = res;
4717 FLAG_C = CFLAG_CLEAR;
4718 FLAG_V = VFLAG_CLEAR;
4719 }
4722 M68KMAKE_OP(eor, 8, ., .)
4723 {
4724 uint ea = M68KMAKE_GET_EA_AY_8;
4725 uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
4727 m68ki_write_8(ea, res);
4729 FLAG_N = NFLAG_8(res);
4730 FLAG_Z = res;
4731 FLAG_C = CFLAG_CLEAR;
4732 FLAG_V = VFLAG_CLEAR;
4733 }
4736 M68KMAKE_OP(eor, 16, ., d)
4737 {
4738 uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));
4740 FLAG_N = NFLAG_16(res);
4741 FLAG_Z = res;
4742 FLAG_C = CFLAG_CLEAR;
4743 FLAG_V = VFLAG_CLEAR;
4744 }
4747 M68KMAKE_OP(eor, 16, ., .)
4748 {
4749 uint ea = M68KMAKE_GET_EA_AY_16;
4750 uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
4752 m68ki_write_16(ea, res);
4754 FLAG_N = NFLAG_16(res);
4755 FLAG_Z = res;
4756 FLAG_C = CFLAG_CLEAR;
4757 FLAG_V = VFLAG_CLEAR;
4758 }
4761 M68KMAKE_OP(eor, 32, ., d)
4762 {
4763 uint res = DY ^= DX;
4765 FLAG_N = NFLAG_32(res);
4766 FLAG_Z = res;
4767 FLAG_C = CFLAG_CLEAR;
4768 FLAG_V = VFLAG_CLEAR;
4769 }
4772 M68KMAKE_OP(eor, 32, ., .)
4773 {
4774 uint ea = M68KMAKE_GET_EA_AY_32;
4775 uint res = DX ^ m68ki_read_32(ea);
4777 m68ki_write_32(ea, res);
4779 FLAG_N = NFLAG_32(res);
4780 FLAG_Z = res;
4781 FLAG_C = CFLAG_CLEAR;
4782 FLAG_V = VFLAG_CLEAR;
4783 }
4786 M68KMAKE_OP(eori, 8, ., d)
4787 {
4788 uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());
4790 FLAG_N = NFLAG_8(res);
4791 FLAG_Z = res;
4792 FLAG_C = CFLAG_CLEAR;
4793 FLAG_V = VFLAG_CLEAR;
4794 }
4797 M68KMAKE_OP(eori, 8, ., .)
4798 {
4799 uint src = OPER_I_8();
4800 uint ea = M68KMAKE_GET_EA_AY_8;
4801 uint res = src ^ m68ki_read_8(ea);
4803 m68ki_write_8(ea, res);
4805 FLAG_N = NFLAG_8(res);
4806 FLAG_Z = res;
4807 FLAG_C = CFLAG_CLEAR;
4808 FLAG_V = VFLAG_CLEAR;
4809 }
4812 M68KMAKE_OP(eori, 16, ., d)
4813 {
4814 uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());
4816 FLAG_N = NFLAG_16(res);
4817 FLAG_Z = res;
4818 FLAG_C = CFLAG_CLEAR;
4819 FLAG_V = VFLAG_CLEAR;
4820 }
4823 M68KMAKE_OP(eori, 16, ., .)
4824 {
4825 uint src = OPER_I_16();
4826 uint ea = M68KMAKE_GET_EA_AY_16;
4827 uint res = src ^ m68ki_read_16(ea);
4829 m68ki_write_16(ea, res);
4831 FLAG_N = NFLAG_16(res);
4832 FLAG_Z = res;
4833 FLAG_C = CFLAG_CLEAR;
4834 FLAG_V = VFLAG_CLEAR;
4835 }
4838 M68KMAKE_OP(eori, 32, ., d)
4839 {
4840 uint res = DY ^= OPER_I_32();
4842 FLAG_N = NFLAG_32(res);
4843 FLAG_Z = res;
4844 FLAG_C = CFLAG_CLEAR;
4845 FLAG_V = VFLAG_CLEAR;
4846 }
4849 M68KMAKE_OP(eori, 32, ., .)
4850 {
4851 uint src = OPER_I_32();
4852 uint ea = M68KMAKE_GET_EA_AY_32;
4853 uint res = src ^ m68ki_read_32(ea);
4855 m68ki_write_32(ea, res);
4857 FLAG_N = NFLAG_32(res);
4858 FLAG_Z = res;
4859 FLAG_C = CFLAG_CLEAR;
4860 FLAG_V = VFLAG_CLEAR;
4861 }
4864 M68KMAKE_OP(eori, 16, toc, .)
4865 {
4866 m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16());
4867 }
4870 M68KMAKE_OP(eori, 16, tos, .)
4871 {
4872 if(FLAG_S)
4873 {
4874 uint src = OPER_I_16();
4875 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
4876 m68ki_set_sr(m68ki_get_sr() ^ src);
4877 return;
4878 }
4879 m68ki_exception_privilege_violation();
4880 }
4883 M68KMAKE_OP(exg, 32, dd, .)
4884 {
4885 uint* reg_a = &DX;
4886 uint* reg_b = &DY;
4887 uint tmp = *reg_a;
4888 *reg_a = *reg_b;
4889 *reg_b = tmp;
4890 }
4893 M68KMAKE_OP(exg, 32, aa, .)
4894 {
4895 uint* reg_a = &AX;
4896 uint* reg_b = &AY;
4897 uint tmp = *reg_a;
4898 *reg_a = *reg_b;
4899 *reg_b = tmp;
4900 }
4903 M68KMAKE_OP(exg, 32, da, .)
4904 {
4905 uint* reg_a = &DX;
4906 uint* reg_b = &AY;
4907 uint tmp = *reg_a;
4908 *reg_a = *reg_b;
4909 *reg_b = tmp;
4910 }
4913 M68KMAKE_OP(ext, 16, ., .)
4914 {
4915 uint* r_dst = &DY;
4917 *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);
4919 FLAG_N = NFLAG_16(*r_dst);
4920 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
4921 FLAG_V = VFLAG_CLEAR;
4922 FLAG_C = CFLAG_CLEAR;
4923 }
4926 M68KMAKE_OP(ext, 32, ., .)
4927 {
4928 uint* r_dst = &DY;
4930 *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);
4932 FLAG_N = NFLAG_32(*r_dst);
4933 FLAG_Z = *r_dst;
4934 FLAG_V = VFLAG_CLEAR;
4935 FLAG_C = CFLAG_CLEAR;
4936 }
4939 M68KMAKE_OP(extb, 32, ., .)
4940 {
4941 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
4942 {
4943 uint* r_dst = &DY;
4945 *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0);
4947 FLAG_N = NFLAG_32(*r_dst);
4948 FLAG_Z = *r_dst;
4949 FLAG_V = VFLAG_CLEAR;
4950 FLAG_C = CFLAG_CLEAR;
4951 return;
4952 }
4953 m68ki_exception_illegal();
4954 }
4957 M68KMAKE_OP(illegal, 0, ., .)
4958 {
4959 m68ki_exception_illegal();
4960 }
4962 M68KMAKE_OP(jmp, 32, ., .)
4963 {
4964 m68ki_jump(M68KMAKE_GET_EA_AY_32);
4965 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
4966 if(REG_PC == REG_PPC)
4967 USE_ALL_CYCLES();
4968 }
4971 M68KMAKE_OP(jsr, 32, ., .)
4972 {
4973 uint ea = M68KMAKE_GET_EA_AY_32;
4974 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
4975 m68ki_push_32(REG_PC);
4976 m68ki_jump(ea);
4977 }
4980 M68KMAKE_OP(lea, 32, ., .)
4981 {
4982 AX = M68KMAKE_GET_EA_AY_32;
4983 }
4986 M68KMAKE_OP(link, 16, ., a7)
4987 {
4988 REG_A[7] -= 4;
4989 m68ki_write_32(REG_A[7], REG_A[7]);
4990 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
4991 }
4994 M68KMAKE_OP(link, 16, ., .)
4995 {
4996 uint* r_dst = &AY;
4998 m68ki_push_32(*r_dst);
4999 *r_dst = REG_A[7];
5000 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
5001 }
5004 M68KMAKE_OP(link, 32, ., a7)
5005 {
5006 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
5007 {
5008 REG_A[7] -= 4;
5009 m68ki_write_32(REG_A[7], REG_A[7]);
5010 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
5011 return;
5012 }
5013 m68ki_exception_illegal();
5014 }
5017 M68KMAKE_OP(link, 32, ., .)
5018 {
5019 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
5020 {
5021 uint* r_dst = &AY;
5023 m68ki_push_32(*r_dst);
5024 *r_dst = REG_A[7];
5025 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
5026 return;
5027 }
5028 m68ki_exception_illegal();
5029 }
5032 M68KMAKE_OP(lsr, 8, s, .)
5033 {
5034 uint* r_dst = &DY;
5035 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5036 uint src = MASK_OUT_ABOVE_8(*r_dst);
5037 uint res = src >> shift;
5039 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5041 FLAG_N = NFLAG_CLEAR;
5042 FLAG_Z = res;
5043 FLAG_X = FLAG_C = src << (9-shift);
5044 FLAG_V = VFLAG_CLEAR;
5045 }
5048 M68KMAKE_OP(lsr, 16, s, .)
5049 {
5050 uint* r_dst = &DY;
5051 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5052 uint src = MASK_OUT_ABOVE_16(*r_dst);
5053 uint res = src >> shift;
5055 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5057 FLAG_N = NFLAG_CLEAR;
5058 FLAG_Z = res;
5059 FLAG_X = FLAG_C = src << (9-shift);
5060 FLAG_V = VFLAG_CLEAR;
5061 }
5064 M68KMAKE_OP(lsr, 32, s, .)
5065 {
5066 uint* r_dst = &DY;
5067 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5068 uint src = *r_dst;
5069 uint res = src >> shift;
5071 *r_dst = res;
5073 FLAG_N = NFLAG_CLEAR;
5074 FLAG_Z = res;
5075 FLAG_X = FLAG_C = src << (9-shift);
5076 FLAG_V = VFLAG_CLEAR;
5077 }
5080 M68KMAKE_OP(lsr, 8, r, .)
5081 {
5082 uint* r_dst = &DY;
5083 uint shift = DX & 0x3f;
5084 uint src = MASK_OUT_ABOVE_8(*r_dst);
5085 uint res = src >> shift;
5087 if(shift != 0)
5088 {
5089 USE_CYCLES(shift<<CYC_SHIFT);
5091 if(shift <= 8)
5092 {
5093 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5094 FLAG_X = FLAG_C = src << (9-shift);
5095 FLAG_N = NFLAG_CLEAR;
5096 FLAG_Z = res;
5097 FLAG_V = VFLAG_CLEAR;
5098 return;
5099 }
5101 *r_dst &= 0xffffff00;
5102 FLAG_X = XFLAG_CLEAR;
5103 FLAG_C = CFLAG_CLEAR;
5104 FLAG_N = NFLAG_CLEAR;
5105 FLAG_Z = ZFLAG_SET;
5106 FLAG_V = VFLAG_CLEAR;
5107 return;
5108 }
5110 FLAG_C = CFLAG_CLEAR;
5111 FLAG_N = NFLAG_8(src);
5112 FLAG_Z = src;
5113 FLAG_V = VFLAG_CLEAR;
5114 }
5117 M68KMAKE_OP(lsr, 16, r, .)
5118 {
5119 uint* r_dst = &DY;
5120 uint shift = DX & 0x3f;
5121 uint src = MASK_OUT_ABOVE_16(*r_dst);
5122 uint res = src >> shift;
5124 if(shift != 0)
5125 {
5126 USE_CYCLES(shift<<CYC_SHIFT);
5128 if(shift <= 16)
5129 {
5130 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5131 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
5132 FLAG_N = NFLAG_CLEAR;
5133 FLAG_Z = res;
5134 FLAG_V = VFLAG_CLEAR;
5135 return;
5136 }
5138 *r_dst &= 0xffff0000;
5139 FLAG_X = XFLAG_CLEAR;
5140 FLAG_C = CFLAG_CLEAR;
5141 FLAG_N = NFLAG_CLEAR;
5142 FLAG_Z = ZFLAG_SET;
5143 FLAG_V = VFLAG_CLEAR;
5144 return;
5145 }
5147 FLAG_C = CFLAG_CLEAR;
5148 FLAG_N = NFLAG_16(src);
5149 FLAG_Z = src;
5150 FLAG_V = VFLAG_CLEAR;
5151 }
5154 M68KMAKE_OP(lsr, 32, r, .)
5155 {
5156 uint* r_dst = &DY;
5157 uint shift = DX & 0x3f;
5158 uint src = *r_dst;
5159 uint res = src >> shift;
5161 if(shift != 0)
5162 {
5163 USE_CYCLES(shift<<CYC_SHIFT);
5165 if(shift < 32)
5166 {
5167 *r_dst = res;
5168 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
5169 FLAG_N = NFLAG_CLEAR;
5170 FLAG_Z = res;
5171 FLAG_V = VFLAG_CLEAR;
5172 return;
5173 }
5175 *r_dst = 0;
5176 FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);
5177 FLAG_N = NFLAG_CLEAR;
5178 FLAG_Z = ZFLAG_SET;
5179 FLAG_V = VFLAG_CLEAR;
5180 return;
5181 }
5183 FLAG_C = CFLAG_CLEAR;
5184 FLAG_N = NFLAG_32(src);
5185 FLAG_Z = src;
5186 FLAG_V = VFLAG_CLEAR;
5187 }
5190 M68KMAKE_OP(lsr, 16, ., .)
5191 {
5192 uint ea = M68KMAKE_GET_EA_AY_16;
5193 uint src = m68ki_read_16(ea);
5194 uint res = src >> 1;
5196 m68ki_write_16(ea, res);
5198 FLAG_N = NFLAG_CLEAR;
5199 FLAG_Z = res;
5200 FLAG_C = FLAG_X = src << 8;
5201 FLAG_V = VFLAG_CLEAR;
5202 }
5205 M68KMAKE_OP(lsl, 8, s, .)
5206 {
5207 uint* r_dst = &DY;
5208 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5209 uint src = MASK_OUT_ABOVE_8(*r_dst);
5210 uint res = MASK_OUT_ABOVE_8(src << shift);
5212 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5214 FLAG_N = NFLAG_8(res);
5215 FLAG_Z = res;
5216 FLAG_X = FLAG_C = src << shift;
5217 FLAG_V = VFLAG_CLEAR;
5218 }
5221 M68KMAKE_OP(lsl, 16, s, .)
5222 {
5223 uint* r_dst = &DY;
5224 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5225 uint src = MASK_OUT_ABOVE_16(*r_dst);
5226 uint res = MASK_OUT_ABOVE_16(src << shift);
5228 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5230 FLAG_N = NFLAG_16(res);
5231 FLAG_Z = res;
5232 FLAG_X = FLAG_C = src >> (8-shift);
5233 FLAG_V = VFLAG_CLEAR;
5234 }
5237 M68KMAKE_OP(lsl, 32, s, .)
5238 {
5239 uint* r_dst = &DY;
5240 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
5241 uint src = *r_dst;
5242 uint res = MASK_OUT_ABOVE_32(src << shift);
5244 *r_dst = res;
5246 FLAG_N = NFLAG_32(res);
5247 FLAG_Z = res;
5248 FLAG_X = FLAG_C = src >> (24-shift);
5249 FLAG_V = VFLAG_CLEAR;
5250 }
5253 M68KMAKE_OP(lsl, 8, r, .)
5254 {
5255 uint* r_dst = &DY;
5256 uint shift = DX & 0x3f;
5257 uint src = MASK_OUT_ABOVE_8(*r_dst);
5258 uint res = MASK_OUT_ABOVE_8(src << shift);
5260 if(shift != 0)
5261 {
5262 USE_CYCLES(shift<<CYC_SHIFT);
5264 if(shift <= 8)
5265 {
5266 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5267 FLAG_X = FLAG_C = src << shift;
5268 FLAG_N = NFLAG_8(res);
5269 FLAG_Z = res;
5270 FLAG_V = VFLAG_CLEAR;
5271 return;
5272 }
5274 *r_dst &= 0xffffff00;
5275 FLAG_X = XFLAG_CLEAR;
5276 FLAG_C = CFLAG_CLEAR;
5277 FLAG_N = NFLAG_CLEAR;
5278 FLAG_Z = ZFLAG_SET;
5279 FLAG_V = VFLAG_CLEAR;
5280 return;
5281 }
5283 FLAG_C = CFLAG_CLEAR;
5284 FLAG_N = NFLAG_8(src);
5285 FLAG_Z = src;
5286 FLAG_V = VFLAG_CLEAR;
5287 }
5290 M68KMAKE_OP(lsl, 16, r, .)
5291 {
5292 uint* r_dst = &DY;
5293 uint shift = DX & 0x3f;
5294 uint src = MASK_OUT_ABOVE_16(*r_dst);
5295 uint res = MASK_OUT_ABOVE_16(src << shift);
5297 if(shift != 0)
5298 {
5299 USE_CYCLES(shift<<CYC_SHIFT);
5301 if(shift <= 16)
5302 {
5303 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5304 FLAG_X = FLAG_C = (src << shift) >> 8;
5305 FLAG_N = NFLAG_16(res);
5306 FLAG_Z = res;
5307 FLAG_V = VFLAG_CLEAR;
5308 return;
5309 }
5311 *r_dst &= 0xffff0000;
5312 FLAG_X = XFLAG_CLEAR;
5313 FLAG_C = CFLAG_CLEAR;
5314 FLAG_N = NFLAG_CLEAR;
5315 FLAG_Z = ZFLAG_SET;
5316 FLAG_V = VFLAG_CLEAR;
5317 return;
5318 }
5320 FLAG_C = CFLAG_CLEAR;
5321 FLAG_N = NFLAG_16(src);
5322 FLAG_Z = src;
5323 FLAG_V = VFLAG_CLEAR;
5324 }
5327 M68KMAKE_OP(lsl, 32, r, .)
5328 {
5329 uint* r_dst = &DY;
5330 uint shift = DX & 0x3f;
5331 uint src = *r_dst;
5332 uint res = MASK_OUT_ABOVE_32(src << shift);
5334 if(shift != 0)
5335 {
5336 USE_CYCLES(shift<<CYC_SHIFT);
5338 if(shift < 32)
5339 {
5340 *r_dst = res;
5341 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
5342 FLAG_N = NFLAG_32(res);
5343 FLAG_Z = res;
5344 FLAG_V = VFLAG_CLEAR;
5345 return;
5346 }
5348 *r_dst = 0;
5349 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
5350 FLAG_N = NFLAG_CLEAR;
5351 FLAG_Z = ZFLAG_SET;
5352 FLAG_V = VFLAG_CLEAR;
5353 return;
5354 }
5356 FLAG_C = CFLAG_CLEAR;
5357 FLAG_N = NFLAG_32(src);
5358 FLAG_Z = src;
5359 FLAG_V = VFLAG_CLEAR;
5360 }
5363 M68KMAKE_OP(lsl, 16, ., .)
5364 {
5365 uint ea = M68KMAKE_GET_EA_AY_16;
5366 uint src = m68ki_read_16(ea);
5367 uint res = MASK_OUT_ABOVE_16(src << 1);
5369 m68ki_write_16(ea, res);
5371 FLAG_N = NFLAG_16(res);
5372 FLAG_Z = res;
5373 FLAG_X = FLAG_C = src >> 7;
5374 FLAG_V = VFLAG_CLEAR;
5375 }
5378 M68KMAKE_OP(move, 8, d, d)
5379 {
5380 uint res = MASK_OUT_ABOVE_8(DY);
5381 uint* r_dst = &DX;
5383 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5385 FLAG_N = NFLAG_8(res);
5386 FLAG_Z = res;
5387 FLAG_V = VFLAG_CLEAR;
5388 FLAG_C = CFLAG_CLEAR;
5389 }
5392 M68KMAKE_OP(move, 8, d, .)
5393 {
5394 uint res = M68KMAKE_GET_OPER_AY_8;
5395 uint* r_dst = &DX;
5397 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
5399 FLAG_N = NFLAG_8(res);
5400 FLAG_Z = res;
5401 FLAG_V = VFLAG_CLEAR;
5402 FLAG_C = CFLAG_CLEAR;
5403 }
5406 M68KMAKE_OP(move, 8, ai, d)
5407 {
5408 uint res = MASK_OUT_ABOVE_8(DY);
5409 uint ea = EA_AX_AI_8();
5411 m68ki_write_8(ea, res);
5413 FLAG_N = NFLAG_8(res);
5414 FLAG_Z = res;
5415 FLAG_V = VFLAG_CLEAR;
5416 FLAG_C = CFLAG_CLEAR;
5417 }
5420 M68KMAKE_OP(move, 8, ai, .)
5421 {
5422 uint res = M68KMAKE_GET_OPER_AY_8;
5423 uint ea = EA_AX_AI_8();
5425 m68ki_write_8(ea, res);
5427 FLAG_N = NFLAG_8(res);
5428 FLAG_Z = res;
5429 FLAG_V = VFLAG_CLEAR;
5430 FLAG_C = CFLAG_CLEAR;
5431 }
5434 M68KMAKE_OP(move, 8, pi7, d)
5435 {
5436 uint res = MASK_OUT_ABOVE_8(DY);
5437 uint ea = EA_A7_PI_8();
5439 m68ki_write_8(ea, res);
5441 FLAG_N = NFLAG_8(res);
5442 FLAG_Z = res;
5443 FLAG_V = VFLAG_CLEAR;
5444 FLAG_C = CFLAG_CLEAR;
5445 }
5448 M68KMAKE_OP(move, 8, pi, d)
5449 {
5450 uint res = MASK_OUT_ABOVE_8(DY);
5451 uint ea = EA_AX_PI_8();
5453 m68ki_write_8(ea, res);
5455 FLAG_N = NFLAG_8(res);
5456 FLAG_Z = res;
5457 FLAG_V = VFLAG_CLEAR;
5458 FLAG_C = CFLAG_CLEAR;
5459 }
5462 M68KMAKE_OP(move, 8, pi7, .)
5463 {
5464 uint res = M68KMAKE_GET_OPER_AY_8;
5465 uint ea = EA_A7_PI_8();
5467 m68ki_write_8(ea, res);
5469 FLAG_N = NFLAG_8(res);
5470 FLAG_Z = res;
5471 FLAG_V = VFLAG_CLEAR;
5472 FLAG_C = CFLAG_CLEAR;
5473 }
5476 M68KMAKE_OP(move, 8, pi, .)
5477 {
5478 uint res = M68KMAKE_GET_OPER_AY_8;
5479 uint ea = EA_AX_PI_8();
5481 m68ki_write_8(ea, res);
5483 FLAG_N = NFLAG_8(res);
5484 FLAG_Z = res;
5485 FLAG_V = VFLAG_CLEAR;
5486 FLAG_C = CFLAG_CLEAR;
5487 }
5490 M68KMAKE_OP(move, 8, pd7, d)
5491 {
5492 uint res = MASK_OUT_ABOVE_8(DY);
5493 uint ea = EA_A7_PD_8();
5495 m68ki_write_8(ea, res);
5497 FLAG_N = NFLAG_8(res);
5498 FLAG_Z = res;
5499 FLAG_V = VFLAG_CLEAR;
5500 FLAG_C = CFLAG_CLEAR;
5501 }
5504 M68KMAKE_OP(move, 8, pd, d)
5505 {
5506 uint res = MASK_OUT_ABOVE_8(DY);
5507 uint ea = EA_AX_PD_8();
5509 m68ki_write_8(ea, res);
5511 FLAG_N = NFLAG_8(res);
5512 FLAG_Z = res;
5513 FLAG_V = VFLAG_CLEAR;
5514 FLAG_C = CFLAG_CLEAR;
5515 }
5518 M68KMAKE_OP(move, 8, pd7, .)
5519 {
5520 uint res = M68KMAKE_GET_OPER_AY_8;
5521 uint ea = EA_A7_PD_8();
5523 m68ki_write_8(ea, res);
5525 FLAG_N = NFLAG_8(res);
5526 FLAG_Z = res;
5527 FLAG_V = VFLAG_CLEAR;
5528 FLAG_C = CFLAG_CLEAR;
5529 }
5532 M68KMAKE_OP(move, 8, pd, .)
5533 {
5534 uint res = M68KMAKE_GET_OPER_AY_8;
5535 uint ea = EA_AX_PD_8();
5537 m68ki_write_8(ea, res);
5539 FLAG_N = NFLAG_8(res);
5540 FLAG_Z = res;
5541 FLAG_V = VFLAG_CLEAR;
5542 FLAG_C = CFLAG_CLEAR;
5543 }
5546 M68KMAKE_OP(move, 8, di, d)
5547 {
5548 uint res = MASK_OUT_ABOVE_8(DY);
5549 uint ea = EA_AX_DI_8();
5551 m68ki_write_8(ea, res);
5553 FLAG_N = NFLAG_8(res);
5554 FLAG_Z = res;
5555 FLAG_V = VFLAG_CLEAR;
5556 FLAG_C = CFLAG_CLEAR;
5557 }
5560 M68KMAKE_OP(move, 8, di, .)
5561 {
5562 uint res = M68KMAKE_GET_OPER_AY_8;
5563 uint ea = EA_AX_DI_8();
5565 m68ki_write_8(ea, res);
5567 FLAG_N = NFLAG_8(res);
5568 FLAG_Z = res;
5569 FLAG_V = VFLAG_CLEAR;
5570 FLAG_C = CFLAG_CLEAR;
5571 }
5574 M68KMAKE_OP(move, 8, ix, d)
5575 {
5576 uint res = MASK_OUT_ABOVE_8(DY);
5577 uint ea = EA_AX_IX_8();
5579 m68ki_write_8(ea, res);
5581 FLAG_N = NFLAG_8(res);
5582 FLAG_Z = res;
5583 FLAG_V = VFLAG_CLEAR;
5584 FLAG_C = CFLAG_CLEAR;
5585 }
5588 M68KMAKE_OP(move, 8, ix, .)
5589 {
5590 uint res = M68KMAKE_GET_OPER_AY_8;
5591 uint ea = EA_AX_IX_8();
5593 m68ki_write_8(ea, res);
5595 FLAG_N = NFLAG_8(res);
5596 FLAG_Z = res;
5597 FLAG_V = VFLAG_CLEAR;
5598 FLAG_C = CFLAG_CLEAR;
5599 }
5602 M68KMAKE_OP(move, 8, aw, d)
5603 {
5604 uint res = MASK_OUT_ABOVE_8(DY);
5605 uint ea = EA_AW_8();
5607 m68ki_write_8(ea, res);
5609 FLAG_N = NFLAG_8(res);
5610 FLAG_Z = res;
5611 FLAG_V = VFLAG_CLEAR;
5612 FLAG_C = CFLAG_CLEAR;
5613 }
5616 M68KMAKE_OP(move, 8, aw, .)
5617 {
5618 uint res = M68KMAKE_GET_OPER_AY_8;
5619 uint ea = EA_AW_8();
5621 m68ki_write_8(ea, res);
5623 FLAG_N = NFLAG_8(res);
5624 FLAG_Z = res;
5625 FLAG_V = VFLAG_CLEAR;
5626 FLAG_C = CFLAG_CLEAR;
5627 }
5630 M68KMAKE_OP(move, 8, al, d)
5631 {
5632 uint res = MASK_OUT_ABOVE_8(DY);
5633 uint ea = EA_AL_8();
5635 m68ki_write_8(ea, res);
5637 FLAG_N = NFLAG_8(res);
5638 FLAG_Z = res;
5639 FLAG_V = VFLAG_CLEAR;
5640 FLAG_C = CFLAG_CLEAR;
5641 }
5644 M68KMAKE_OP(move, 8, al, .)
5645 {
5646 uint res = M68KMAKE_GET_OPER_AY_8;
5647 uint ea = EA_AL_8();
5649 m68ki_write_8(ea, res);
5651 FLAG_N = NFLAG_8(res);
5652 FLAG_Z = res;
5653 FLAG_V = VFLAG_CLEAR;
5654 FLAG_C = CFLAG_CLEAR;
5655 }
5658 M68KMAKE_OP(move, 16, d, d)
5659 {
5660 uint res = MASK_OUT_ABOVE_16(DY);
5661 uint* r_dst = &DX;
5663 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5665 FLAG_N = NFLAG_16(res);
5666 FLAG_Z = res;
5667 FLAG_V = VFLAG_CLEAR;
5668 FLAG_C = CFLAG_CLEAR;
5669 }
5672 M68KMAKE_OP(move, 16, d, a)
5673 {
5674 uint res = MASK_OUT_ABOVE_16(AY);
5675 uint* r_dst = &DX;
5677 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5679 FLAG_N = NFLAG_16(res);
5680 FLAG_Z = res;
5681 FLAG_V = VFLAG_CLEAR;
5682 FLAG_C = CFLAG_CLEAR;
5683 }
5686 M68KMAKE_OP(move, 16, d, .)
5687 {
5688 uint res = M68KMAKE_GET_OPER_AY_16;
5689 uint* r_dst = &DX;
5691 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
5693 FLAG_N = NFLAG_16(res);
5694 FLAG_Z = res;
5695 FLAG_V = VFLAG_CLEAR;
5696 FLAG_C = CFLAG_CLEAR;
5697 }
5700 M68KMAKE_OP(move, 16, ai, d)
5701 {
5702 uint res = MASK_OUT_ABOVE_16(DY);
5703 uint ea = EA_AX_AI_16();
5705 m68ki_write_16(ea, res);
5707 FLAG_N = NFLAG_16(res);
5708 FLAG_Z = res;
5709 FLAG_V = VFLAG_CLEAR;
5710 FLAG_C = CFLAG_CLEAR;
5711 }
5714 M68KMAKE_OP(move, 16, ai, a)
5715 {
5716 uint res = MASK_OUT_ABOVE_16(AY);
5717 uint ea = EA_AX_AI_16();
5719 m68ki_write_16(ea, res);
5721 FLAG_N = NFLAG_16(res);
5722 FLAG_Z = res;
5723 FLAG_V = VFLAG_CLEAR;
5724 FLAG_C = CFLAG_CLEAR;
5725 }
5728 M68KMAKE_OP(move, 16, ai, .)
5729 {
5730 uint res = M68KMAKE_GET_OPER_AY_16;
5731 uint ea = EA_AX_AI_16();
5733 m68ki_write_16(ea, res);
5735 FLAG_N = NFLAG_16(res);
5736 FLAG_Z = res;
5737 FLAG_V = VFLAG_CLEAR;
5738 FLAG_C = CFLAG_CLEAR;
5739 }
5742 M68KMAKE_OP(move, 16, pi, d)
5743 {
5744 uint res = MASK_OUT_ABOVE_16(DY);
5745 uint ea = EA_AX_PI_16();
5747 m68ki_write_16(ea, res);
5749 FLAG_N = NFLAG_16(res);
5750 FLAG_Z = res;
5751 FLAG_V = VFLAG_CLEAR;
5752 FLAG_C = CFLAG_CLEAR;
5753 }
5756 M68KMAKE_OP(move, 16, pi, a)
5757 {
5758 uint res = MASK_OUT_ABOVE_16(AY);
5759 uint ea = EA_AX_PI_16();
5761 m68ki_write_16(ea, res);
5763 FLAG_N = NFLAG_16(res);
5764 FLAG_Z = res;
5765 FLAG_V = VFLAG_CLEAR;
5766 FLAG_C = CFLAG_CLEAR;
5767 }
5770 M68KMAKE_OP(move, 16, pi, .)
5771 {
5772 uint res = M68KMAKE_GET_OPER_AY_16;
5773 uint ea = EA_AX_PI_16();
5775 m68ki_write_16(ea, res);
5777 FLAG_N = NFLAG_16(res);
5778 FLAG_Z = res;
5779 FLAG_V = VFLAG_CLEAR;
5780 FLAG_C = CFLAG_CLEAR;
5781 }
5784 M68KMAKE_OP(move, 16, pd, d)
5785 {
5786 uint res = MASK_OUT_ABOVE_16(DY);
5787 uint ea = EA_AX_PD_16();
5789 m68ki_write_16(ea, res);
5791 FLAG_N = NFLAG_16(res);
5792 FLAG_Z = res;
5793 FLAG_V = VFLAG_CLEAR;
5794 FLAG_C = CFLAG_CLEAR;
5795 }
5798 M68KMAKE_OP(move, 16, pd, a)
5799 {
5800 uint res = MASK_OUT_ABOVE_16(AY);
5801 uint ea = EA_AX_PD_16();
5803 m68ki_write_16(ea, res);
5805 FLAG_N = NFLAG_16(res);
5806 FLAG_Z = res;
5807 FLAG_V = VFLAG_CLEAR;
5808 FLAG_C = CFLAG_CLEAR;
5809 }
5812 M68KMAKE_OP(move, 16, pd, .)
5813 {
5814 uint res = M68KMAKE_GET_OPER_AY_16;
5815 uint ea = EA_AX_PD_16();
5817 m68ki_write_16(ea, res);
5819 FLAG_N = NFLAG_16(res);
5820 FLAG_Z = res;
5821 FLAG_V = VFLAG_CLEAR;
5822 FLAG_C = CFLAG_CLEAR;
5823 }
5826 M68KMAKE_OP(move, 16, di, d)
5827 {
5828 uint res = MASK_OUT_ABOVE_16(DY);
5829 uint ea = EA_AX_DI_16();
5831 m68ki_write_16(ea, res);
5833 FLAG_N = NFLAG_16(res);
5834 FLAG_Z = res;
5835 FLAG_V = VFLAG_CLEAR;
5836 FLAG_C = CFLAG_CLEAR;
5837 }
5840 M68KMAKE_OP(move, 16, di, a)
5841 {
5842 uint res = MASK_OUT_ABOVE_16(AY);
5843 uint ea = EA_AX_DI_16();
5845 m68ki_write_16(ea, res);
5847 FLAG_N = NFLAG_16(res);
5848 FLAG_Z = res;
5849 FLAG_V = VFLAG_CLEAR;
5850 FLAG_C = CFLAG_CLEAR;
5851 }
5854 M68KMAKE_OP(move, 16, di, .)
5855 {
5856 uint res = M68KMAKE_GET_OPER_AY_16;
5857 uint ea = EA_AX_DI_16();
5859 m68ki_write_16(ea, res);
5861 FLAG_N = NFLAG_16(res);
5862 FLAG_Z = res;
5863 FLAG_V = VFLAG_CLEAR;
5864 FLAG_C = CFLAG_CLEAR;
5865 }
5868 M68KMAKE_OP(move, 16, ix, d)
5869 {
5870 uint res = MASK_OUT_ABOVE_16(DY);
5871 uint ea = EA_AX_IX_16();
5873 m68ki_write_16(ea, res);
5875 FLAG_N = NFLAG_16(res);
5876 FLAG_Z = res;
5877 FLAG_V = VFLAG_CLEAR;
5878 FLAG_C = CFLAG_CLEAR;
5879 }
5882 M68KMAKE_OP(move, 16, ix, a)
5883 {
5884 uint res = MASK_OUT_ABOVE_16(AY);
5885 uint ea = EA_AX_IX_16();
5887 m68ki_write_16(ea, res);
5889 FLAG_N = NFLAG_16(res);
5890 FLAG_Z = res;
5891 FLAG_V = VFLAG_CLEAR;
5892 FLAG_C = CFLAG_CLEAR;
5893 }
5896 M68KMAKE_OP(move, 16, ix, .)
5897 {
5898 uint res = M68KMAKE_GET_OPER_AY_16;
5899 uint ea = EA_AX_IX_16();
5901 m68ki_write_16(ea, res);
5903 FLAG_N = NFLAG_16(res);
5904 FLAG_Z = res;
5905 FLAG_V = VFLAG_CLEAR;
5906 FLAG_C = CFLAG_CLEAR;
5907 }
5910 M68KMAKE_OP(move, 16, aw, d)
5911 {
5912 uint res = MASK_OUT_ABOVE_16(DY);
5913 uint ea = EA_AW_16();
5915 m68ki_write_16(ea, res);
5917 FLAG_N = NFLAG_16(res);
5918 FLAG_Z = res;
5919 FLAG_V = VFLAG_CLEAR;
5920 FLAG_C = CFLAG_CLEAR;
5921 }
5924 M68KMAKE_OP(move, 16, aw, a)
5925 {
5926 uint res = MASK_OUT_ABOVE_16(AY);
5927 uint ea = EA_AW_16();
5929 m68ki_write_16(ea, res);
5931 FLAG_N = NFLAG_16(res);
5932 FLAG_Z = res;
5933 FLAG_V = VFLAG_CLEAR;
5934 FLAG_C = CFLAG_CLEAR;
5935 }
5938 M68KMAKE_OP(move, 16, aw, .)
5939 {
5940 uint res = M68KMAKE_GET_OPER_AY_16;
5941 uint ea = EA_AW_16();
5943 m68ki_write_16(ea, res);
5945 FLAG_N = NFLAG_16(res);
5946 FLAG_Z = res;
5947 FLAG_V = VFLAG_CLEAR;
5948 FLAG_C = CFLAG_CLEAR;
5949 }
5952 M68KMAKE_OP(move, 16, al, d)
5953 {
5954 uint res = MASK_OUT_ABOVE_16(DY);
5955 uint ea = EA_AL_16();
5957 m68ki_write_16(ea, res);
5959 FLAG_N = NFLAG_16(res);
5960 FLAG_Z = res;
5961 FLAG_V = VFLAG_CLEAR;
5962 FLAG_C = CFLAG_CLEAR;
5963 }
5966 M68KMAKE_OP(move, 16, al, a)
5967 {
5968 uint res = MASK_OUT_ABOVE_16(AY);
5969 uint ea = EA_AL_16();
5971 m68ki_write_16(ea, res);
5973 FLAG_N = NFLAG_16(res);
5974 FLAG_Z = res;
5975 FLAG_V = VFLAG_CLEAR;
5976 FLAG_C = CFLAG_CLEAR;
5977 }
5980 M68KMAKE_OP(move, 16, al, .)
5981 {
5982 uint res = M68KMAKE_GET_OPER_AY_16;
5983 uint ea = EA_AL_16();
5985 m68ki_write_16(ea, res);
5987 FLAG_N = NFLAG_16(res);
5988 FLAG_Z = res;
5989 FLAG_V = VFLAG_CLEAR;
5990 FLAG_C = CFLAG_CLEAR;
5991 }
5994 M68KMAKE_OP(move, 32, d, d)
5995 {
5996 uint res = DY;
5997 uint* r_dst = &DX;
5999 *r_dst = res;
6001 FLAG_N = NFLAG_32(res);
6002 FLAG_Z = res;
6003 FLAG_V = VFLAG_CLEAR;
6004 FLAG_C = CFLAG_CLEAR;
6005 }
6008 M68KMAKE_OP(move, 32, d, a)
6009 {
6010 uint res = AY;
6011 uint* r_dst = &DX;
6013 *r_dst = res;
6015 FLAG_N = NFLAG_32(res);
6016 FLAG_Z = res;
6017 FLAG_V = VFLAG_CLEAR;
6018 FLAG_C = CFLAG_CLEAR;
6019 }
6022 M68KMAKE_OP(move, 32, d, .)
6023 {
6024 uint res = M68KMAKE_GET_OPER_AY_32;
6025 uint* r_dst = &DX;
6027 *r_dst = res;
6029 FLAG_N = NFLAG_32(res);
6030 FLAG_Z = res;
6031 FLAG_V = VFLAG_CLEAR;
6032 FLAG_C = CFLAG_CLEAR;
6033 }
6036 M68KMAKE_OP(move, 32, ai, d)
6037 {
6038 uint res = DY;
6039 uint ea = EA_AX_AI_32();
6041 m68ki_write_32(ea, res);
6043 FLAG_N = NFLAG_32(res);
6044 FLAG_Z = res;
6045 FLAG_V = VFLAG_CLEAR;
6046 FLAG_C = CFLAG_CLEAR;
6047 }
6050 M68KMAKE_OP(move, 32, ai, a)
6051 {
6052 uint res = AY;
6053 uint ea = EA_AX_AI_32();
6055 m68ki_write_32(ea, res);
6057 FLAG_N = NFLAG_32(res);
6058 FLAG_Z = res;
6059 FLAG_V = VFLAG_CLEAR;
6060 FLAG_C = CFLAG_CLEAR;
6061 }
6064 M68KMAKE_OP(move, 32, ai, .)
6065 {
6066 uint res = M68KMAKE_GET_OPER_AY_32;
6067 uint ea = EA_AX_AI_32();
6069 m68ki_write_32(ea, res);
6071 FLAG_N = NFLAG_32(res);
6072 FLAG_Z = res;
6073 FLAG_V = VFLAG_CLEAR;
6074 FLAG_C = CFLAG_CLEAR;
6075 }
6078 M68KMAKE_OP(move, 32, pi, d)
6079 {
6080 uint res = DY;
6081 uint ea = EA_AX_PI_32();
6083 m68ki_write_32(ea, res);
6085 FLAG_N = NFLAG_32(res);
6086 FLAG_Z = res;
6087 FLAG_V = VFLAG_CLEAR;
6088 FLAG_C = CFLAG_CLEAR;
6089 }
6092 M68KMAKE_OP(move, 32, pi, a)
6093 {
6094 uint res = AY;
6095 uint ea = EA_AX_PI_32();
6097 m68ki_write_32(ea, res);
6099 FLAG_N = NFLAG_32(res);
6100 FLAG_Z = res;
6101 FLAG_V = VFLAG_CLEAR;
6102 FLAG_C = CFLAG_CLEAR;
6103 }
6106 M68KMAKE_OP(move, 32, pi, .)
6107 {
6108 uint res = M68KMAKE_GET_OPER_AY_32;
6109 uint ea = EA_AX_PI_32();
6111 m68ki_write_32(ea, res);
6113 FLAG_N = NFLAG_32(res);
6114 FLAG_Z = res;
6115 FLAG_V = VFLAG_CLEAR;
6116 FLAG_C = CFLAG_CLEAR;
6117 }
6120 M68KMAKE_OP(move, 32, pd, d)
6121 {
6122 uint res = DY;
6123 uint ea = EA_AX_PD_32();
6125 m68ki_write_32(ea, res);
6127 FLAG_N = NFLAG_32(res);
6128 FLAG_Z = res;
6129 FLAG_V = VFLAG_CLEAR;
6130 FLAG_C = CFLAG_CLEAR;
6131 }
6134 M68KMAKE_OP(move, 32, pd, a)
6135 {
6136 uint res = AY;
6137 uint ea = EA_AX_PD_32();
6139 m68ki_write_32(ea, res);
6141 FLAG_N = NFLAG_32(res);
6142 FLAG_Z = res;
6143 FLAG_V = VFLAG_CLEAR;
6144 FLAG_C = CFLAG_CLEAR;
6145 }
6148 M68KMAKE_OP(move, 32, pd, .)
6149 {
6150 uint res = M68KMAKE_GET_OPER_AY_32;
6151 uint ea = EA_AX_PD_32();
6153 m68ki_write_32(ea, res);
6155 FLAG_N = NFLAG_32(res);
6156 FLAG_Z = res;
6157 FLAG_V = VFLAG_CLEAR;
6158 FLAG_C = CFLAG_CLEAR;
6159 }
6162 M68KMAKE_OP(move, 32, di, d)
6163 {
6164 uint res = DY;
6165 uint ea = EA_AX_DI_32();
6167 m68ki_write_32(ea, res);
6169 FLAG_N = NFLAG_32(res);
6170 FLAG_Z = res;
6171 FLAG_V = VFLAG_CLEAR;
6172 FLAG_C = CFLAG_CLEAR;
6173 }
6176 M68KMAKE_OP(move, 32, di, a)
6177 {
6178 uint res = AY;
6179 uint ea = EA_AX_DI_32();
6181 m68ki_write_32(ea, res);
6183 FLAG_N = NFLAG_32(res);
6184 FLAG_Z = res;
6185 FLAG_V = VFLAG_CLEAR;
6186 FLAG_C = CFLAG_CLEAR;
6187 }
6190 M68KMAKE_OP(move, 32, di, .)
6191 {
6192 uint res = M68KMAKE_GET_OPER_AY_32;
6193 uint ea = EA_AX_DI_32();
6195 m68ki_write_32(ea, res);
6197 FLAG_N = NFLAG_32(res);
6198 FLAG_Z = res;
6199 FLAG_V = VFLAG_CLEAR;
6200 FLAG_C = CFLAG_CLEAR;
6201 }
6204 M68KMAKE_OP(move, 32, ix, d)
6205 {
6206 uint res = DY;
6207 uint ea = EA_AX_IX_32();
6209 m68ki_write_32(ea, res);
6211 FLAG_N = NFLAG_32(res);
6212 FLAG_Z = res;
6213 FLAG_V = VFLAG_CLEAR;
6214 FLAG_C = CFLAG_CLEAR;
6215 }
6218 M68KMAKE_OP(move, 32, ix, a)
6219 {
6220 uint res = AY;
6221 uint ea = EA_AX_IX_32();
6223 m68ki_write_32(ea, res);
6225 FLAG_N = NFLAG_32(res);
6226 FLAG_Z = res;
6227 FLAG_V = VFLAG_CLEAR;
6228 FLAG_C = CFLAG_CLEAR;
6229 }
6232 M68KMAKE_OP(move, 32, ix, .)
6233 {
6234 uint res = M68KMAKE_GET_OPER_AY_32;
6235 uint ea = EA_AX_IX_32();
6237 m68ki_write_32(ea, res);
6239 FLAG_N = NFLAG_32(res);
6240 FLAG_Z = res;
6241 FLAG_V = VFLAG_CLEAR;
6242 FLAG_C = CFLAG_CLEAR;
6243 }
6246 M68KMAKE_OP(move, 32, aw, d)
6247 {
6248 uint res = DY;
6249 uint ea = EA_AW_32();
6251 m68ki_write_32(ea, res);
6253 FLAG_N = NFLAG_32(res);
6254 FLAG_Z = res;
6255 FLAG_V = VFLAG_CLEAR;
6256 FLAG_C = CFLAG_CLEAR;
6257 }
6260 M68KMAKE_OP(move, 32, aw, a)
6261 {
6262 uint res = AY;
6263 uint ea = EA_AW_32();
6265 m68ki_write_32(ea, res);
6267 FLAG_N = NFLAG_32(res);
6268 FLAG_Z = res;
6269 FLAG_V = VFLAG_CLEAR;
6270 FLAG_C = CFLAG_CLEAR;
6271 }
6274 M68KMAKE_OP(move, 32, aw, .)
6275 {
6276 uint res = M68KMAKE_GET_OPER_AY_32;
6277 uint ea = EA_AW_32();
6279 m68ki_write_32(ea, res);
6281 FLAG_N = NFLAG_32(res);
6282 FLAG_Z = res;
6283 FLAG_V = VFLAG_CLEAR;
6284 FLAG_C = CFLAG_CLEAR;
6285 }
6288 M68KMAKE_OP(move, 32, al, d)
6289 {
6290 uint res = DY;
6291 uint ea = EA_AL_32();
6293 m68ki_write_32(ea, res);
6295 FLAG_N = NFLAG_32(res);
6296 FLAG_Z = res;
6297 FLAG_V = VFLAG_CLEAR;
6298 FLAG_C = CFLAG_CLEAR;
6299 }
6302 M68KMAKE_OP(move, 32, al, a)
6303 {
6304 uint res = AY;
6305 uint ea = EA_AL_32();
6307 m68ki_write_32(ea, res);
6309 FLAG_N = NFLAG_32(res);
6310 FLAG_Z = res;
6311 FLAG_V = VFLAG_CLEAR;
6312 FLAG_C = CFLAG_CLEAR;
6313 }
6316 M68KMAKE_OP(move, 32, al, .)
6317 {
6318 uint res = M68KMAKE_GET_OPER_AY_32;
6319 uint ea = EA_AL_32();
6321 m68ki_write_32(ea, res);
6323 FLAG_N = NFLAG_32(res);
6324 FLAG_Z = res;
6325 FLAG_V = VFLAG_CLEAR;
6326 FLAG_C = CFLAG_CLEAR;
6327 }
6330 M68KMAKE_OP(movea, 16, ., d)
6331 {
6332 AX = MAKE_INT_16(DY);
6333 }
6336 M68KMAKE_OP(movea, 16, ., a)
6337 {
6338 AX = MAKE_INT_16(AY);
6339 }
6342 M68KMAKE_OP(movea, 16, ., .)
6343 {
6344 AX = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
6345 }
6348 M68KMAKE_OP(movea, 32, ., d)
6349 {
6350 AX = DY;
6351 }
6354 M68KMAKE_OP(movea, 32, ., a)
6355 {
6356 AX = AY;
6357 }
6360 M68KMAKE_OP(movea, 32, ., .)
6361 {
6362 AX = M68KMAKE_GET_OPER_AY_32;
6363 }
6366 M68KMAKE_OP(move, 16, frc, d)
6367 {
6368 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6369 {
6370 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr();
6371 return;
6372 }
6373 m68ki_exception_illegal();
6374 }
6377 M68KMAKE_OP(move, 16, frc, .)
6378 {
6379 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6380 {
6381 m68ki_write_16(M68KMAKE_GET_EA_AY_16, m68ki_get_ccr());
6382 return;
6383 }
6384 m68ki_exception_illegal();
6385 }
6388 M68KMAKE_OP(move, 16, toc, d)
6389 {
6390 m68ki_set_ccr(DY);
6391 }
6394 M68KMAKE_OP(move, 16, toc, .)
6395 {
6396 m68ki_set_ccr(M68KMAKE_GET_OPER_AY_16);
6397 }
6400 M68KMAKE_OP(move, 16, frs, d)
6401 {
6402 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
6403 {
6404 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();
6405 return;
6406 }
6407 m68ki_exception_privilege_violation();
6408 }
6411 M68KMAKE_OP(move, 16, frs, .)
6412 {
6413 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
6414 {
6415 uint ea = M68KMAKE_GET_EA_AY_16;
6416 m68ki_write_16(ea, m68ki_get_sr());
6417 return;
6418 }
6419 m68ki_exception_privilege_violation();
6420 }
6423 M68KMAKE_OP(move, 16, tos, d)
6424 {
6425 if(FLAG_S)
6426 {
6427 m68ki_set_sr(DY);
6428 return;
6429 }
6430 m68ki_exception_privilege_violation();
6431 }
6434 M68KMAKE_OP(move, 16, tos, .)
6435 {
6436 if(FLAG_S)
6437 {
6438 uint new_sr = M68KMAKE_GET_OPER_AY_16;
6439 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6440 m68ki_set_sr(new_sr);
6441 return;
6442 }
6443 m68ki_exception_privilege_violation();
6444 }
6447 M68KMAKE_OP(move, 32, fru, .)
6448 {
6449 if(FLAG_S)
6450 {
6451 AY = REG_USP;
6452 return;
6453 }
6454 m68ki_exception_privilege_violation();
6455 }
6458 M68KMAKE_OP(move, 32, tou, .)
6459 {
6460 if(FLAG_S)
6461 {
6462 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6463 REG_USP = AY;
6464 return;
6465 }
6466 m68ki_exception_privilege_violation();
6467 }
6470 M68KMAKE_OP(movec, 32, cr, .)
6471 {
6472 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6473 {
6474 if(FLAG_S)
6475 {
6476 uint word2 = OPER_I_16();
6478 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6479 switch (word2 & 0xfff)
6480 {
6481 case 0x000: /* SFC */
6482 REG_DA[(word2 >> 12) & 15] = REG_SFC;
6483 return;
6484 case 0x001: /* DFC */
6485 REG_DA[(word2 >> 12) & 15] = REG_DFC;
6486 return;
6487 case 0x002: /* CACR */
6488 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6489 {
6490 REG_DA[(word2 >> 12) & 15] = REG_CACR;
6491 return;
6492 }
6493 return;
6494 case 0x800: /* USP */
6495 REG_DA[(word2 >> 12) & 15] = REG_USP;
6496 return;
6497 case 0x801: /* VBR */
6498 REG_DA[(word2 >> 12) & 15] = REG_VBR;
6499 return;
6500 case 0x802: /* CAAR */
6501 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6502 {
6503 REG_DA[(word2 >> 12) & 15] = REG_CAAR;
6504 return;
6505 }
6506 m68ki_exception_illegal();
6507 break;
6508 case 0x803: /* MSP */
6509 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6510 {
6511 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP;
6512 return;
6513 }
6514 m68ki_exception_illegal();
6515 return;
6516 case 0x804: /* ISP */
6517 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6518 {
6519 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP;
6520 return;
6521 }
6522 m68ki_exception_illegal();
6523 return;
6524 default:
6525 m68ki_exception_illegal();
6526 return;
6527 }
6528 }
6529 m68ki_exception_privilege_violation();
6530 return;
6531 }
6532 m68ki_exception_illegal();
6533 }
6536 M68KMAKE_OP(movec, 32, rc, .)
6537 {
6538 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6539 {
6540 if(FLAG_S)
6541 {
6542 uint word2 = OPER_I_16();
6544 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6545 switch (word2 & 0xfff)
6546 {
6547 case 0x000: /* SFC */
6548 REG_SFC = REG_DA[(word2 >> 12) & 15] & 7;
6549 return;
6550 case 0x001: /* DFC */
6551 REG_DFC = REG_DA[(word2 >> 12) & 15] & 7;
6552 return;
6553 case 0x002: /* CACR */
6554 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6555 {
6556 REG_CACR = REG_DA[(word2 >> 12) & 15];
6557 return;
6558 }
6559 m68ki_exception_illegal();
6560 return;
6561 case 0x800: /* USP */
6562 REG_USP = REG_DA[(word2 >> 12) & 15];
6563 return;
6564 case 0x801: /* VBR */
6565 REG_VBR = REG_DA[(word2 >> 12) & 15];
6566 return;
6567 case 0x802: /* CAAR */
6568 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6569 {
6570 REG_CAAR = REG_DA[(word2 >> 12) & 15];
6571 return;
6572 }
6573 m68ki_exception_illegal();
6574 return;
6575 case 0x803: /* MSP */
6576 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6577 {
6578 /* we are in supervisor mode so just check for M flag */
6579 if(!FLAG_M)
6580 {
6581 REG_MSP = REG_DA[(word2 >> 12) & 15];
6582 return;
6583 }
6584 REG_SP = REG_DA[(word2 >> 12) & 15];
6585 return;
6586 }
6587 m68ki_exception_illegal();
6588 return;
6589 case 0x804: /* ISP */
6590 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6591 {
6592 if(!FLAG_M)
6593 {
6594 REG_SP = REG_DA[(word2 >> 12) & 15];
6595 return;
6596 }
6597 REG_ISP = REG_DA[(word2 >> 12) & 15];
6598 return;
6599 }
6600 m68ki_exception_illegal();
6601 return;
6602 default:
6603 m68ki_exception_illegal();
6604 return;
6605 }
6606 }
6607 m68ki_exception_privilege_violation();
6608 return;
6609 }
6610 m68ki_exception_illegal();
6611 }
6614 M68KMAKE_OP(movem, 16, re, pd)
6615 {
6616 uint i = 0;
6617 uint register_list = OPER_I_16();
6618 uint ea = AY;
6619 uint count = 0;
6621 for(; i < 16; i++)
6622 if(register_list & (1 << i))
6623 {
6624 ea -= 2;
6625 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));
6626 count++;
6627 }
6628 AY = ea;
6630 USE_CYCLES(count<<CYC_MOVEM_W);
6631 }
6634 M68KMAKE_OP(movem, 16, re, .)
6635 {
6636 uint i = 0;
6637 uint register_list = OPER_I_16();
6638 uint ea = M68KMAKE_GET_EA_AY_16;
6639 uint count = 0;
6641 for(; i < 16; i++)
6642 if(register_list & (1 << i))
6643 {
6644 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
6645 ea += 2;
6646 count++;
6647 }
6649 USE_CYCLES(count<<CYC_MOVEM_W);
6650 }
6653 M68KMAKE_OP(movem, 32, re, pd)
6654 {
6655 uint i = 0;
6656 uint register_list = OPER_I_16();
6657 uint ea = AY;
6658 uint count = 0;
6660 for(; i < 16; i++)
6661 if(register_list & (1 << i))
6662 {
6663 ea -= 4;
6664 m68ki_write_32(ea, REG_DA[15-i]);
6665 count++;
6666 }
6667 AY = ea;
6669 USE_CYCLES(count<<CYC_MOVEM_L);
6670 }
6673 M68KMAKE_OP(movem, 32, re, .)
6674 {
6675 uint i = 0;
6676 uint register_list = OPER_I_16();
6677 uint ea = M68KMAKE_GET_EA_AY_32;
6678 uint count = 0;
6680 for(; i < 16; i++)
6681 if(register_list & (1 << i))
6682 {
6683 m68ki_write_32(ea, REG_DA[i]);
6684 ea += 4;
6685 count++;
6686 }
6688 USE_CYCLES(count<<CYC_MOVEM_L);
6689 }
6692 M68KMAKE_OP(movem, 16, er, pi)
6693 {
6694 uint i = 0;
6695 uint register_list = OPER_I_16();
6696 uint ea = AY;
6697 uint count = 0;
6699 for(; i < 16; i++)
6700 if(register_list & (1 << i))
6701 {
6702 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
6703 ea += 2;
6704 count++;
6705 }
6706 AY = ea;
6708 USE_CYCLES(count<<CYC_MOVEM_W);
6709 }
6712 M68KMAKE_OP(movem, 16, er, .)
6713 {
6714 uint i = 0;
6715 uint register_list = OPER_I_16();
6716 uint ea = M68KMAKE_GET_EA_AY_16;
6717 uint count = 0;
6719 for(; i < 16; i++)
6720 if(register_list & (1 << i))
6721 {
6722 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
6723 ea += 2;
6724 count++;
6725 }
6727 USE_CYCLES(count<<CYC_MOVEM_W);
6728 }
6731 M68KMAKE_OP(movem, 32, er, pi)
6732 {
6733 uint i = 0;
6734 uint register_list = OPER_I_16();
6735 uint ea = AY;
6736 uint count = 0;
6738 for(; i < 16; i++)
6739 if(register_list & (1 << i))
6740 {
6741 REG_DA[i] = m68ki_read_32(ea);
6742 ea += 4;
6743 count++;
6744 }
6745 AY = ea;
6747 USE_CYCLES(count<<CYC_MOVEM_L);
6748 }
6751 M68KMAKE_OP(movem, 32, er, .)
6752 {
6753 uint i = 0;
6754 uint register_list = OPER_I_16();
6755 uint ea = M68KMAKE_GET_EA_AY_32;
6756 uint count = 0;
6758 for(; i < 16; i++)
6759 if(register_list & (1 << i))
6760 {
6761 REG_DA[i] = m68ki_read_32(ea);
6762 ea += 4;
6763 count++;
6764 }
6766 USE_CYCLES(count<<CYC_MOVEM_L);
6767 }
6770 M68KMAKE_OP(movep, 16, re, .)
6771 {
6772 uint ea = EA_AY_DI_16();
6773 uint src = DX;
6775 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));
6776 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
6777 }
6780 M68KMAKE_OP(movep, 32, re, .)
6781 {
6782 uint ea = EA_AY_DI_32();
6783 uint src = DX;
6785 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));
6786 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));
6787 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));
6788 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
6789 }
6792 M68KMAKE_OP(movep, 16, er, .)
6793 {
6794 uint ea = EA_AY_DI_16();
6795 uint* r_dst = &DX;
6797 *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));
6798 }
6801 M68KMAKE_OP(movep, 32, er, .)
6802 {
6803 uint ea = EA_AY_DI_32();
6805 DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)
6806 + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);
6807 }
6810 M68KMAKE_OP(moves, 8, ., .)
6811 {
6812 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6813 {
6814 if(FLAG_S)
6815 {
6816 uint word2 = OPER_I_16();
6817 uint ea = M68KMAKE_GET_EA_AY_8;
6819 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6820 if(BIT_B(word2)) /* Register to memory */
6821 {
6822 m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
6823 return;
6824 }
6825 if(BIT_F(word2)) /* Memory to address register */
6826 {
6827 REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
6828 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
6829 USE_CYCLES(2);
6830 return;
6831 }
6832 /* Memory to data register */
6833 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
6834 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
6835 USE_CYCLES(2);
6836 return;
6837 }
6838 m68ki_exception_privilege_violation();
6839 return;
6840 }
6841 m68ki_exception_illegal();
6842 }
6845 M68KMAKE_OP(moves, 16, ., .)
6846 {
6847 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6848 {
6849 if(FLAG_S)
6850 {
6851 uint word2 = OPER_I_16();
6852 uint ea = M68KMAKE_GET_EA_AY_16;
6854 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6855 if(BIT_B(word2)) /* Register to memory */
6856 {
6857 m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
6858 return;
6859 }
6860 if(BIT_F(word2)) /* Memory to address register */
6861 {
6862 REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
6863 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
6864 USE_CYCLES(2);
6865 return;
6866 }
6867 /* Memory to data register */
6868 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
6869 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
6870 USE_CYCLES(2);
6871 return;
6872 }
6873 m68ki_exception_privilege_violation();
6874 return;
6875 }
6876 m68ki_exception_illegal();
6877 }
6880 M68KMAKE_OP(moves, 32, ., .)
6881 {
6882 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
6883 {
6884 if(FLAG_S)
6885 {
6886 uint word2 = OPER_I_16();
6887 uint ea = M68KMAKE_GET_EA_AY_32;
6889 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
6890 if(BIT_B(word2)) /* Register to memory */
6891 {
6892 m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
6893 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
6894 USE_CYCLES(2);
6895 return;
6896 }
6897 /* Memory to register */
6898 REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
6899 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
6900 USE_CYCLES(2);
6901 return;
6902 }
6903 m68ki_exception_privilege_violation();
6904 return;
6905 }
6906 m68ki_exception_illegal();
6907 }
6910 M68KMAKE_OP(moveq, 32, ., .)
6911 {
6912 uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));
6914 FLAG_N = NFLAG_32(res);
6915 FLAG_Z = res;
6916 FLAG_V = VFLAG_CLEAR;
6917 FLAG_C = CFLAG_CLEAR;
6918 }
6921 M68KMAKE_OP(muls, 16, ., d)
6922 {
6923 uint* r_dst = &DX;
6924 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
6926 *r_dst = res;
6928 FLAG_Z = res;
6929 FLAG_N = NFLAG_32(res);
6930 FLAG_V = VFLAG_CLEAR;
6931 FLAG_C = CFLAG_CLEAR;
6932 }
6935 M68KMAKE_OP(muls, 16, ., .)
6936 {
6937 uint* r_dst = &DX;
6938 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(M68KMAKE_GET_OPER_AY_16) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
6940 *r_dst = res;
6942 FLAG_Z = res;
6943 FLAG_N = NFLAG_32(res);
6944 FLAG_V = VFLAG_CLEAR;
6945 FLAG_C = CFLAG_CLEAR;
6946 }
6949 M68KMAKE_OP(mulu, 16, ., d)
6950 {
6951 uint* r_dst = &DX;
6952 uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst);
6954 *r_dst = res;
6956 FLAG_Z = res;
6957 FLAG_N = NFLAG_32(res);
6958 FLAG_V = VFLAG_CLEAR;
6959 FLAG_C = CFLAG_CLEAR;
6960 }
6963 M68KMAKE_OP(mulu, 16, ., .)
6964 {
6965 uint* r_dst = &DX;
6966 uint res = M68KMAKE_GET_OPER_AY_16 * MASK_OUT_ABOVE_16(*r_dst);
6968 *r_dst = res;
6970 FLAG_Z = res;
6971 FLAG_N = NFLAG_32(res);
6972 FLAG_V = VFLAG_CLEAR;
6973 FLAG_C = CFLAG_CLEAR;
6974 }
6977 M68KMAKE_OP(mull, 32, ., d)
6978 {
6979 #if M68K_USE_64_BIT
6981 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
6982 {
6983 uint word2 = OPER_I_16();
6984 uint64 src = DY;
6985 uint64 dst = REG_D[(word2 >> 12) & 7];
6986 uint64 res;
6988 FLAG_C = CFLAG_CLEAR;
6990 if(BIT_B(word2)) /* signed */
6991 {
6992 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
6993 if(!BIT_A(word2))
6994 {
6995 FLAG_Z = MASK_OUT_ABOVE_32(res);
6996 FLAG_N = NFLAG_32(res);
6997 FLAG_V = ((sint64)res != (sint32)res)<<7;
6998 REG_D[(word2 >> 12) & 7] = FLAG_Z;
6999 return;
7000 }
7001 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7002 FLAG_N = NFLAG_64(res);
7003 FLAG_V = VFLAG_CLEAR;
7004 REG_D[word2 & 7] = (res >> 32);
7005 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7006 return;
7007 }
7009 res = src * dst;
7010 if(!BIT_A(word2))
7011 {
7012 FLAG_Z = MASK_OUT_ABOVE_32(res);
7013 FLAG_N = NFLAG_32(res);
7014 FLAG_V = (res > 0xffffffff)<<7;
7015 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7016 return;
7017 }
7018 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7019 FLAG_N = NFLAG_64(res);
7020 FLAG_V = VFLAG_CLEAR;
7021 REG_D[word2 & 7] = (res >> 32);
7022 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7023 return;
7024 }
7025 m68ki_exception_illegal();
7027 #else
7029 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7030 {
7031 uint word2 = OPER_I_16();
7032 uint src = DY;
7033 uint dst = REG_D[(word2 >> 12) & 7];
7034 uint neg = GET_MSB_32(src ^ dst);
7035 uint src1;
7036 uint src2;
7037 uint dst1;
7038 uint dst2;
7039 uint r1;
7040 uint r2;
7041 uint r3;
7042 uint r4;
7043 uint lo;
7044 uint hi;
7046 FLAG_C = CFLAG_CLEAR;
7048 if(BIT_B(word2)) /* signed */
7049 {
7050 if(GET_MSB_32(src))
7051 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
7052 if(GET_MSB_32(dst))
7053 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
7054 }
7056 src1 = MASK_OUT_ABOVE_16(src);
7057 src2 = src>>16;
7058 dst1 = MASK_OUT_ABOVE_16(dst);
7059 dst2 = dst>>16;
7062 r1 = src1 * dst1;
7063 r2 = src1 * dst2;
7064 r3 = src2 * dst1;
7065 r4 = src2 * dst2;
7067 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
7068 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
7070 if(BIT_B(word2) && neg)
7071 {
7072 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
7073 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
7074 }
7076 if(BIT_A(word2))
7077 {
7078 REG_D[word2 & 7] = hi;
7079 REG_D[(word2 >> 12) & 7] = lo;
7080 FLAG_N = NFLAG_32(hi);
7081 FLAG_Z = hi | lo;
7082 FLAG_V = VFLAG_CLEAR;
7083 return;
7084 }
7086 REG_D[(word2 >> 12) & 7] = lo;
7087 FLAG_N = NFLAG_32(lo);
7088 FLAG_Z = lo;
7089 if(BIT_B(word2))
7090 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
7091 else
7092 FLAG_V = (hi != 0) << 7;
7093 return;
7094 }
7095 m68ki_exception_illegal();
7097 #endif
7098 }
7101 M68KMAKE_OP(mull, 32, ., .)
7102 {
7103 #if M68K_USE_64_BIT
7105 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7106 {
7107 uint word2 = OPER_I_16();
7108 uint64 src = M68KMAKE_GET_OPER_AY_32;
7109 uint64 dst = REG_D[(word2 >> 12) & 7];
7110 uint64 res;
7112 FLAG_C = CFLAG_CLEAR;
7114 if(BIT_B(word2)) /* signed */
7115 {
7116 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
7117 if(!BIT_A(word2))
7118 {
7119 FLAG_Z = MASK_OUT_ABOVE_32(res);
7120 FLAG_N = NFLAG_32(res);
7121 FLAG_V = ((sint64)res != (sint32)res)<<7;
7122 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7123 return;
7124 }
7125 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7126 FLAG_N = NFLAG_64(res);
7127 FLAG_V = VFLAG_CLEAR;
7128 REG_D[word2 & 7] = (res >> 32);
7129 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7130 return;
7131 }
7133 res = src * dst;
7134 if(!BIT_A(word2))
7135 {
7136 FLAG_Z = MASK_OUT_ABOVE_32(res);
7137 FLAG_N = NFLAG_32(res);
7138 FLAG_V = (res > 0xffffffff)<<7;
7139 REG_D[(word2 >> 12) & 7] = FLAG_Z;
7140 return;
7141 }
7142 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
7143 FLAG_N = NFLAG_64(res);
7144 FLAG_V = VFLAG_CLEAR;
7145 REG_D[word2 & 7] = (res >> 32);
7146 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
7147 return;
7148 }
7149 m68ki_exception_illegal();
7151 #else
7153 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7154 {
7155 uint word2 = OPER_I_16();
7156 uint src = M68KMAKE_GET_OPER_AY_32;
7157 uint dst = REG_D[(word2 >> 12) & 7];
7158 uint neg = GET_MSB_32(src ^ dst);
7159 uint src1;
7160 uint src2;
7161 uint dst1;
7162 uint dst2;
7163 uint r1;
7164 uint r2;
7165 uint r3;
7166 uint r4;
7167 uint lo;
7168 uint hi;
7170 FLAG_C = CFLAG_CLEAR;
7172 if(BIT_B(word2)) /* signed */
7173 {
7174 if(GET_MSB_32(src))
7175 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
7176 if(GET_MSB_32(dst))
7177 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
7178 }
7180 src1 = MASK_OUT_ABOVE_16(src);
7181 src2 = src>>16;
7182 dst1 = MASK_OUT_ABOVE_16(dst);
7183 dst2 = dst>>16;
7186 r1 = src1 * dst1;
7187 r2 = src1 * dst2;
7188 r3 = src2 * dst1;
7189 r4 = src2 * dst2;
7191 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
7192 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
7194 if(BIT_B(word2) && neg)
7195 {
7196 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
7197 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
7198 }
7200 if(BIT_A(word2))
7201 {
7202 REG_D[word2 & 7] = hi;
7203 REG_D[(word2 >> 12) & 7] = lo;
7204 FLAG_N = NFLAG_32(hi);
7205 FLAG_Z = hi | lo;
7206 FLAG_V = VFLAG_CLEAR;
7207 return;
7208 }
7210 REG_D[(word2 >> 12) & 7] = lo;
7211 FLAG_N = NFLAG_32(lo);
7212 FLAG_Z = lo;
7213 if(BIT_B(word2))
7214 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
7215 else
7216 FLAG_V = (hi != 0) << 7;
7217 return;
7218 }
7219 m68ki_exception_illegal();
7221 #endif
7222 }
7225 M68KMAKE_OP(nbcd, 8, ., d)
7226 {
7227 uint* r_dst = &DY;
7228 uint dst = *r_dst;
7229 uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
7231 if(res != 0x9a)
7232 {
7233 if((res & 0x0f) == 0xa)
7234 res = (res & 0xf0) + 0x10;
7236 res = MASK_OUT_ABOVE_8(res);
7238 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
7240 FLAG_Z |= res;
7241 FLAG_C = CFLAG_SET;
7242 FLAG_X = XFLAG_SET;
7243 }
7244 else
7245 {
7246 FLAG_C = CFLAG_CLEAR;
7247 FLAG_X = XFLAG_CLEAR;
7248 }
7249 FLAG_N = NFLAG_8(res); /* officially undefined */
7250 }
7253 M68KMAKE_OP(nbcd, 8, ., .)
7254 {
7255 uint ea = M68KMAKE_GET_EA_AY_8;
7256 uint dst = m68ki_read_8(ea);
7257 uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
7259 if(res != 0x9a)
7260 {
7261 if((res & 0x0f) == 0xa)
7262 res = (res & 0xf0) + 0x10;
7264 res = MASK_OUT_ABOVE_8(res);
7266 m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
7268 FLAG_Z |= res;
7269 FLAG_C = CFLAG_SET;
7270 FLAG_X = XFLAG_SET;
7271 }
7272 else
7273 {
7274 FLAG_C = CFLAG_CLEAR;
7275 FLAG_X = XFLAG_CLEAR;
7276 }
7277 FLAG_N = NFLAG_8(res); /* officially undefined */
7278 }
7281 M68KMAKE_OP(neg, 8, ., d)
7282 {
7283 uint* r_dst = &DY;
7284 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);
7286 FLAG_N = NFLAG_8(res);
7287 FLAG_C = FLAG_X = CFLAG_8(res);
7288 FLAG_V = *r_dst & res;
7289 FLAG_Z = MASK_OUT_ABOVE_8(res);
7291 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
7292 }
7295 M68KMAKE_OP(neg, 8, ., .)
7296 {
7297 uint ea = M68KMAKE_GET_EA_AY_8;
7298 uint src = m68ki_read_8(ea);
7299 uint res = 0 - src;
7301 FLAG_N = NFLAG_8(res);
7302 FLAG_C = FLAG_X = CFLAG_8(res);
7303 FLAG_V = src & res;
7304 FLAG_Z = MASK_OUT_ABOVE_8(res);
7306 m68ki_write_8(ea, FLAG_Z);
7307 }
7310 M68KMAKE_OP(neg, 16, ., d)
7311 {
7312 uint* r_dst = &DY;
7313 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);
7315 FLAG_N = NFLAG_16(res);
7316 FLAG_C = FLAG_X = CFLAG_16(res);
7317 FLAG_V = (*r_dst & res)>>8;
7318 FLAG_Z = MASK_OUT_ABOVE_16(res);
7320 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
7321 }
7324 M68KMAKE_OP(neg, 16, ., .)
7325 {
7326 uint ea = M68KMAKE_GET_EA_AY_16;
7327 uint src = m68ki_read_16(ea);
7328 uint res = 0 - src;
7330 FLAG_N = NFLAG_16(res);
7331 FLAG_C = FLAG_X = CFLAG_16(res);
7332 FLAG_V = (src & res)>>8;
7333 FLAG_Z = MASK_OUT_ABOVE_16(res);
7335 m68ki_write_16(ea, FLAG_Z);
7336 }
7339 M68KMAKE_OP(neg, 32, ., d)
7340 {
7341 uint* r_dst = &DY;
7342 uint res = 0 - *r_dst;
7344 FLAG_N = NFLAG_32(res);
7345 FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);
7346 FLAG_V = (*r_dst & res)>>24;
7347 FLAG_Z = MASK_OUT_ABOVE_32(res);
7349 *r_dst = FLAG_Z;
7350 }
7353 M68KMAKE_OP(neg, 32, ., .)
7354 {
7355 uint ea = M68KMAKE_GET_EA_AY_32;
7356 uint src = m68ki_read_32(ea);
7357 uint res = 0 - src;
7359 FLAG_N = NFLAG_32(res);
7360 FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
7361 FLAG_V = (src & res)>>24;
7362 FLAG_Z = MASK_OUT_ABOVE_32(res);
7364 m68ki_write_32(ea, FLAG_Z);
7365 }
7368 M68KMAKE_OP(negx, 8, ., d)
7369 {
7370 uint* r_dst = &DY;
7371 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();
7373 FLAG_N = NFLAG_8(res);
7374 FLAG_X = FLAG_C = CFLAG_8(res);
7375 FLAG_V = *r_dst & res;
7377 res = MASK_OUT_ABOVE_8(res);
7378 FLAG_Z |= res;
7380 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
7381 }
7384 M68KMAKE_OP(negx, 8, ., .)
7385 {
7386 uint ea = M68KMAKE_GET_EA_AY_8;
7387 uint src = m68ki_read_8(ea);
7388 uint res = 0 - src - XFLAG_AS_1();
7390 FLAG_N = NFLAG_8(res);
7391 FLAG_X = FLAG_C = CFLAG_8(res);
7392 FLAG_V = src & res;
7394 res = MASK_OUT_ABOVE_8(res);
7395 FLAG_Z |= res;
7397 m68ki_write_8(ea, res);
7398 }
7401 M68KMAKE_OP(negx, 16, ., d)
7402 {
7403 uint* r_dst = &DY;
7404 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();
7406 FLAG_N = NFLAG_16(res);
7407 FLAG_X = FLAG_C = CFLAG_16(res);
7408 FLAG_V = (*r_dst & res)>>8;
7410 res = MASK_OUT_ABOVE_16(res);
7411 FLAG_Z |= res;
7413 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
7414 }
7417 M68KMAKE_OP(negx, 16, ., .)
7418 {
7419 uint ea = M68KMAKE_GET_EA_AY_16;
7420 uint src = m68ki_read_16(ea);
7421 uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
7423 FLAG_N = NFLAG_16(res);
7424 FLAG_X = FLAG_C = CFLAG_16(res);
7425 FLAG_V = (src & res)>>8;
7427 res = MASK_OUT_ABOVE_16(res);
7428 FLAG_Z |= res;
7430 m68ki_write_16(ea, res);
7431 }
7434 M68KMAKE_OP(negx, 32, ., d)
7435 {
7436 uint* r_dst = &DY;
7437 uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();
7439 FLAG_N = NFLAG_32(res);
7440 FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);
7441 FLAG_V = (*r_dst & res)>>24;
7443 res = MASK_OUT_ABOVE_32(res);
7444 FLAG_Z |= res;
7446 *r_dst = res;
7447 }
7450 M68KMAKE_OP(negx, 32, ., .)
7451 {
7452 uint ea = M68KMAKE_GET_EA_AY_32;
7453 uint src = m68ki_read_32(ea);
7454 uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
7456 FLAG_N = NFLAG_32(res);
7457 FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
7458 FLAG_V = (src & res)>>24;
7460 res = MASK_OUT_ABOVE_32(res);
7461 FLAG_Z |= res;
7463 m68ki_write_32(ea, res);
7464 }
7467 M68KMAKE_OP(nop, 0, ., .)
7468 {
7469 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
7470 }
7473 M68KMAKE_OP(not, 8, ., d)
7474 {
7475 uint* r_dst = &DY;
7476 uint res = MASK_OUT_ABOVE_8(~*r_dst);
7478 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
7480 FLAG_N = NFLAG_8(res);
7481 FLAG_Z = res;
7482 FLAG_C = CFLAG_CLEAR;
7483 FLAG_V = VFLAG_CLEAR;
7484 }
7487 M68KMAKE_OP(not, 8, ., .)
7488 {
7489 uint ea = M68KMAKE_GET_EA_AY_8;
7490 uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
7492 m68ki_write_8(ea, res);
7494 FLAG_N = NFLAG_8(res);
7495 FLAG_Z = res;
7496 FLAG_C = CFLAG_CLEAR;
7497 FLAG_V = VFLAG_CLEAR;
7498 }
7501 M68KMAKE_OP(not, 16, ., d)
7502 {
7503 uint* r_dst = &DY;
7504 uint res = MASK_OUT_ABOVE_16(~*r_dst);
7506 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
7508 FLAG_N = NFLAG_16(res);
7509 FLAG_Z = res;
7510 FLAG_C = CFLAG_CLEAR;
7511 FLAG_V = VFLAG_CLEAR;
7512 }
7515 M68KMAKE_OP(not, 16, ., .)
7516 {
7517 uint ea = M68KMAKE_GET_EA_AY_16;
7518 uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
7520 m68ki_write_16(ea, res);
7522 FLAG_N = NFLAG_16(res);
7523 FLAG_Z = res;
7524 FLAG_C = CFLAG_CLEAR;
7525 FLAG_V = VFLAG_CLEAR;
7526 }
7529 M68KMAKE_OP(not, 32, ., d)
7530 {
7531 uint* r_dst = &DY;
7532 uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);
7534 FLAG_N = NFLAG_32(res);
7535 FLAG_Z = res;
7536 FLAG_C = CFLAG_CLEAR;
7537 FLAG_V = VFLAG_CLEAR;
7538 }
7541 M68KMAKE_OP(not, 32, ., .)
7542 {
7543 uint ea = M68KMAKE_GET_EA_AY_32;
7544 uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
7546 m68ki_write_32(ea, res);
7548 FLAG_N = NFLAG_32(res);
7549 FLAG_Z = res;
7550 FLAG_C = CFLAG_CLEAR;
7551 FLAG_V = VFLAG_CLEAR;
7552 }
7555 M68KMAKE_OP(or, 8, er, d)
7556 {
7557 uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));
7559 FLAG_N = NFLAG_8(res);
7560 FLAG_Z = res;
7561 FLAG_C = CFLAG_CLEAR;
7562 FLAG_V = VFLAG_CLEAR;
7563 }
7566 M68KMAKE_OP(or, 8, er, .)
7567 {
7568 uint res = MASK_OUT_ABOVE_8((DX |= M68KMAKE_GET_OPER_AY_8));
7570 FLAG_N = NFLAG_8(res);
7571 FLAG_Z = res;
7572 FLAG_C = CFLAG_CLEAR;
7573 FLAG_V = VFLAG_CLEAR;
7574 }
7577 M68KMAKE_OP(or, 16, er, d)
7578 {
7579 uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));
7581 FLAG_N = NFLAG_16(res);
7582 FLAG_Z = res;
7583 FLAG_C = CFLAG_CLEAR;
7584 FLAG_V = VFLAG_CLEAR;
7585 }
7588 M68KMAKE_OP(or, 16, er, .)
7589 {
7590 uint res = MASK_OUT_ABOVE_16((DX |= M68KMAKE_GET_OPER_AY_16));
7592 FLAG_N = NFLAG_16(res);
7593 FLAG_Z = res;
7594 FLAG_C = CFLAG_CLEAR;
7595 FLAG_V = VFLAG_CLEAR;
7596 }
7599 M68KMAKE_OP(or, 32, er, d)
7600 {
7601 uint res = DX |= DY;
7603 FLAG_N = NFLAG_32(res);
7604 FLAG_Z = res;
7605 FLAG_C = CFLAG_CLEAR;
7606 FLAG_V = VFLAG_CLEAR;
7607 }
7610 M68KMAKE_OP(or, 32, er, .)
7611 {
7612 uint res = DX |= M68KMAKE_GET_OPER_AY_32;
7614 FLAG_N = NFLAG_32(res);
7615 FLAG_Z = res;
7616 FLAG_C = CFLAG_CLEAR;
7617 FLAG_V = VFLAG_CLEAR;
7618 }
7621 M68KMAKE_OP(or, 8, re, .)
7622 {
7623 uint ea = M68KMAKE_GET_EA_AY_8;
7624 uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
7626 m68ki_write_8(ea, res);
7628 FLAG_N = NFLAG_8(res);
7629 FLAG_Z = res;
7630 FLAG_C = CFLAG_CLEAR;
7631 FLAG_V = VFLAG_CLEAR;
7632 }
7635 M68KMAKE_OP(or, 16, re, .)
7636 {
7637 uint ea = M68KMAKE_GET_EA_AY_16;
7638 uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
7640 m68ki_write_16(ea, res);
7642 FLAG_N = NFLAG_16(res);
7643 FLAG_Z = res;
7644 FLAG_C = CFLAG_CLEAR;
7645 FLAG_V = VFLAG_CLEAR;
7646 }
7649 M68KMAKE_OP(or, 32, re, .)
7650 {
7651 uint ea = M68KMAKE_GET_EA_AY_32;
7652 uint res = DX | m68ki_read_32(ea);
7654 m68ki_write_32(ea, res);
7656 FLAG_N = NFLAG_32(res);
7657 FLAG_Z = res;
7658 FLAG_C = CFLAG_CLEAR;
7659 FLAG_V = VFLAG_CLEAR;
7660 }
7663 M68KMAKE_OP(ori, 8, ., d)
7664 {
7665 uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));
7667 FLAG_N = NFLAG_8(res);
7668 FLAG_Z = res;
7669 FLAG_C = CFLAG_CLEAR;
7670 FLAG_V = VFLAG_CLEAR;
7671 }
7674 M68KMAKE_OP(ori, 8, ., .)
7675 {
7676 uint src = OPER_I_8();
7677 uint ea = M68KMAKE_GET_EA_AY_8;
7678 uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
7680 m68ki_write_8(ea, res);
7682 FLAG_N = NFLAG_8(res);
7683 FLAG_Z = res;
7684 FLAG_C = CFLAG_CLEAR;
7685 FLAG_V = VFLAG_CLEAR;
7686 }
7689 M68KMAKE_OP(ori, 16, ., d)
7690 {
7691 uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());
7693 FLAG_N = NFLAG_16(res);
7694 FLAG_Z = res;
7695 FLAG_C = CFLAG_CLEAR;
7696 FLAG_V = VFLAG_CLEAR;
7697 }
7700 M68KMAKE_OP(ori, 16, ., .)
7701 {
7702 uint src = OPER_I_16();
7703 uint ea = M68KMAKE_GET_EA_AY_16;
7704 uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
7706 m68ki_write_16(ea, res);
7708 FLAG_N = NFLAG_16(res);
7709 FLAG_Z = res;
7710 FLAG_C = CFLAG_CLEAR;
7711 FLAG_V = VFLAG_CLEAR;
7712 }
7715 M68KMAKE_OP(ori, 32, ., d)
7716 {
7717 uint res = DY |= OPER_I_32();
7719 FLAG_N = NFLAG_32(res);
7720 FLAG_Z = res;
7721 FLAG_C = CFLAG_CLEAR;
7722 FLAG_V = VFLAG_CLEAR;
7723 }
7726 M68KMAKE_OP(ori, 32, ., .)
7727 {
7728 uint src = OPER_I_32();
7729 uint ea = M68KMAKE_GET_EA_AY_32;
7730 uint res = src | m68ki_read_32(ea);
7732 m68ki_write_32(ea, res);
7734 FLAG_N = NFLAG_32(res);
7735 FLAG_Z = res;
7736 FLAG_C = CFLAG_CLEAR;
7737 FLAG_V = VFLAG_CLEAR;
7738 }
7741 M68KMAKE_OP(ori, 16, toc, .)
7742 {
7743 m68ki_set_ccr(m68ki_get_ccr() | OPER_I_16());
7744 }
7747 M68KMAKE_OP(ori, 16, tos, .)
7748 {
7749 if(FLAG_S)
7750 {
7751 uint src = OPER_I_16();
7752 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
7753 m68ki_set_sr(m68ki_get_sr() | src);
7754 return;
7755 }
7756 m68ki_exception_privilege_violation();
7757 }
7760 M68KMAKE_OP(pack, 16, rr, .)
7761 {
7762 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7763 {
7764 /* Note: DX and DY are reversed in Motorola's docs */
7765 uint src = DY + OPER_I_16();
7766 uint* r_dst = &DX;
7768 *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);
7769 return;
7770 }
7771 m68ki_exception_illegal();
7772 }
7775 M68KMAKE_OP(pack, 16, mm, ax7)
7776 {
7777 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7778 {
7779 /* Note: AX and AY are reversed in Motorola's docs */
7780 uint ea_src = EA_AY_PD_8();
7781 uint src = m68ki_read_8(ea_src);
7782 ea_src = EA_AY_PD_8();
7783 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
7785 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
7786 return;
7787 }
7788 m68ki_exception_illegal();
7789 }
7792 M68KMAKE_OP(pack, 16, mm, ay7)
7793 {
7794 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7795 {
7796 /* Note: AX and AY are reversed in Motorola's docs */
7797 uint ea_src = EA_A7_PD_8();
7798 uint src = m68ki_read_8(ea_src);
7799 ea_src = EA_A7_PD_8();
7800 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
7802 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
7803 return;
7804 }
7805 m68ki_exception_illegal();
7806 }
7809 M68KMAKE_OP(pack, 16, mm, axy7)
7810 {
7811 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7812 {
7813 uint ea_src = EA_A7_PD_8();
7814 uint src = m68ki_read_8(ea_src);
7815 ea_src = EA_A7_PD_8();
7816 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
7818 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
7819 return;
7820 }
7821 m68ki_exception_illegal();
7822 }
7825 M68KMAKE_OP(pack, 16, mm, .)
7826 {
7827 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
7828 {
7829 /* Note: AX and AY are reversed in Motorola's docs */
7830 uint ea_src = EA_AY_PD_8();
7831 uint src = m68ki_read_8(ea_src);
7832 ea_src = EA_AY_PD_8();
7833 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
7835 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
7836 return;
7837 }
7838 m68ki_exception_illegal();
7839 }
7842 M68KMAKE_OP(pea, 32, ., .)
7843 {
7844 uint ea = M68KMAKE_GET_EA_AY_32;
7846 m68ki_push_32(ea);
7847 }
7850 M68KMAKE_OP(reset, 0, ., .)
7851 {
7852 if(FLAG_S)
7853 {
7854 m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */
7855 USE_CYCLES(CYC_RESET);
7856 return;
7857 }
7858 m68ki_exception_privilege_violation();
7859 }
7862 M68KMAKE_OP(ror, 8, s, .)
7863 {
7864 uint* r_dst = &DY;
7865 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
7866 uint shift = orig_shift & 7;
7867 uint src = MASK_OUT_ABOVE_8(*r_dst);
7868 uint res = ROR_8(src, shift);
7870 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
7872 FLAG_N = NFLAG_8(res);
7873 FLAG_Z = res;
7874 FLAG_C = src << (9-orig_shift);
7875 FLAG_V = VFLAG_CLEAR;
7876 }
7879 M68KMAKE_OP(ror, 16, s, .)
7880 {
7881 uint* r_dst = &DY;
7882 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
7883 uint src = MASK_OUT_ABOVE_16(*r_dst);
7884 uint res = ROR_16(src, shift);
7886 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
7888 FLAG_N = NFLAG_16(res);
7889 FLAG_Z = res;
7890 FLAG_C = src << (9-shift);
7891 FLAG_V = VFLAG_CLEAR;
7892 }
7895 M68KMAKE_OP(ror, 32, s, .)
7896 {
7897 uint* r_dst = &DY;
7898 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
7899 uint64 src = *r_dst;
7900 uint res = ROR_32(src, shift);
7902 *r_dst = res;
7904 FLAG_N = NFLAG_32(res);
7905 FLAG_Z = res;
7906 FLAG_C = src << (9-shift);
7907 FLAG_V = VFLAG_CLEAR;
7908 }
7911 M68KMAKE_OP(ror, 8, r, .)
7912 {
7913 uint* r_dst = &DY;
7914 uint orig_shift = DX & 0x3f;
7915 uint shift = orig_shift & 7;
7916 uint src = MASK_OUT_ABOVE_8(*r_dst);
7917 uint res = ROR_8(src, shift);
7919 if(orig_shift != 0)
7920 {
7921 USE_CYCLES(orig_shift<<CYC_SHIFT);
7923 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
7924 FLAG_C = src << (8-((shift-1)&7));
7925 FLAG_N = NFLAG_8(res);
7926 FLAG_Z = res;
7927 FLAG_V = VFLAG_CLEAR;
7928 return;
7929 }
7931 FLAG_C = CFLAG_CLEAR;
7932 FLAG_N = NFLAG_8(src);
7933 FLAG_Z = src;
7934 FLAG_V = VFLAG_CLEAR;
7935 }
7938 M68KMAKE_OP(ror, 16, r, .)
7939 {
7940 uint* r_dst = &DY;
7941 uint orig_shift = DX & 0x3f;
7942 uint shift = orig_shift & 15;
7943 uint src = MASK_OUT_ABOVE_16(*r_dst);
7944 uint res = ROR_16(src, shift);
7946 if(orig_shift != 0)
7947 {
7948 USE_CYCLES(orig_shift<<CYC_SHIFT);
7950 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
7951 FLAG_C = (src >> ((shift - 1) & 15)) << 8;
7952 FLAG_N = NFLAG_16(res);
7953 FLAG_Z = res;
7954 FLAG_V = VFLAG_CLEAR;
7955 return;
7956 }
7958 FLAG_C = CFLAG_CLEAR;
7959 FLAG_N = NFLAG_16(src);
7960 FLAG_Z = src;
7961 FLAG_V = VFLAG_CLEAR;
7962 }
7965 M68KMAKE_OP(ror, 32, r, .)
7966 {
7967 uint* r_dst = &DY;
7968 uint orig_shift = DX & 0x3f;
7969 uint shift = orig_shift & 31;
7970 uint64 src = *r_dst;
7971 uint res = ROR_32(src, shift);
7973 if(orig_shift != 0)
7974 {
7975 USE_CYCLES(orig_shift<<CYC_SHIFT);
7977 *r_dst = res;
7978 FLAG_C = (src >> ((shift - 1) & 31)) << 8;
7979 FLAG_N = NFLAG_32(res);
7980 FLAG_Z = res;
7981 FLAG_V = VFLAG_CLEAR;
7982 return;
7983 }
7985 FLAG_C = CFLAG_CLEAR;
7986 FLAG_N = NFLAG_32(src);
7987 FLAG_Z = src;
7988 FLAG_V = VFLAG_CLEAR;
7989 }
7992 M68KMAKE_OP(ror, 16, ., .)
7993 {
7994 uint ea = M68KMAKE_GET_EA_AY_16;
7995 uint src = m68ki_read_16(ea);
7996 uint res = ROR_16(src, 1);
7998 m68ki_write_16(ea, res);
8000 FLAG_N = NFLAG_16(res);
8001 FLAG_Z = res;
8002 FLAG_C = src << 8;
8003 FLAG_V = VFLAG_CLEAR;
8004 }
8007 M68KMAKE_OP(rol, 8, s, .)
8008 {
8009 uint* r_dst = &DY;
8010 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
8011 uint shift = orig_shift & 7;
8012 uint src = MASK_OUT_ABOVE_8(*r_dst);
8013 uint res = ROL_8(src, shift);
8015 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8017 FLAG_N = NFLAG_8(res);
8018 FLAG_Z = res;
8019 FLAG_C = src << orig_shift;
8020 FLAG_V = VFLAG_CLEAR;
8021 }
8024 M68KMAKE_OP(rol, 16, s, .)
8025 {
8026 uint* r_dst = &DY;
8027 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8028 uint src = MASK_OUT_ABOVE_16(*r_dst);
8029 uint res = ROL_16(src, shift);
8031 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8033 FLAG_N = NFLAG_16(res);
8034 FLAG_Z = res;
8035 FLAG_C = src >> (8-shift);
8036 FLAG_V = VFLAG_CLEAR;
8037 }
8040 M68KMAKE_OP(rol, 32, s, .)
8041 {
8042 uint* r_dst = &DY;
8043 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8044 uint64 src = *r_dst;
8045 uint res = ROL_32(src, shift);
8047 *r_dst = res;
8049 FLAG_N = NFLAG_32(res);
8050 FLAG_Z = res;
8051 FLAG_C = src >> (24-shift);
8052 FLAG_V = VFLAG_CLEAR;
8053 }
8056 M68KMAKE_OP(rol, 8, r, .)
8057 {
8058 uint* r_dst = &DY;
8059 uint orig_shift = DX & 0x3f;
8060 uint shift = orig_shift & 7;
8061 uint src = MASK_OUT_ABOVE_8(*r_dst);
8062 uint res = ROL_8(src, shift);
8064 if(orig_shift != 0)
8065 {
8066 USE_CYCLES(orig_shift<<CYC_SHIFT);
8068 if(shift != 0)
8069 {
8070 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8071 FLAG_C = src << shift;
8072 FLAG_N = NFLAG_8(res);
8073 FLAG_Z = res;
8074 FLAG_V = VFLAG_CLEAR;
8075 return;
8076 }
8077 FLAG_C = (src & 1)<<8;
8078 FLAG_N = NFLAG_8(src);
8079 FLAG_Z = src;
8080 FLAG_V = VFLAG_CLEAR;
8081 return;
8082 }
8084 FLAG_C = CFLAG_CLEAR;
8085 FLAG_N = NFLAG_8(src);
8086 FLAG_Z = src;
8087 FLAG_V = VFLAG_CLEAR;
8088 }
8091 M68KMAKE_OP(rol, 16, r, .)
8092 {
8093 uint* r_dst = &DY;
8094 uint orig_shift = DX & 0x3f;
8095 uint shift = orig_shift & 15;
8096 uint src = MASK_OUT_ABOVE_16(*r_dst);
8097 uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));
8099 if(orig_shift != 0)
8100 {
8101 USE_CYCLES(orig_shift<<CYC_SHIFT);
8103 if(shift != 0)
8104 {
8105 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8106 FLAG_C = (src << shift) >> 8;
8107 FLAG_N = NFLAG_16(res);
8108 FLAG_Z = res;
8109 FLAG_V = VFLAG_CLEAR;
8110 return;
8111 }
8112 FLAG_C = (src & 1)<<8;
8113 FLAG_N = NFLAG_16(src);
8114 FLAG_Z = src;
8115 FLAG_V = VFLAG_CLEAR;
8116 return;
8117 }
8119 FLAG_C = CFLAG_CLEAR;
8120 FLAG_N = NFLAG_16(src);
8121 FLAG_Z = src;
8122 FLAG_V = VFLAG_CLEAR;
8123 }
8126 M68KMAKE_OP(rol, 32, r, .)
8127 {
8128 uint* r_dst = &DY;
8129 uint orig_shift = DX & 0x3f;
8130 uint shift = orig_shift & 31;
8131 uint64 src = *r_dst;
8132 uint res = ROL_32(src, shift);
8134 if(orig_shift != 0)
8135 {
8136 USE_CYCLES(orig_shift<<CYC_SHIFT);
8138 *r_dst = res;
8140 FLAG_C = (src >> (32 - shift)) << 8;
8141 FLAG_N = NFLAG_32(res);
8142 FLAG_Z = res;
8143 FLAG_V = VFLAG_CLEAR;
8144 return;
8145 }
8147 FLAG_C = CFLAG_CLEAR;
8148 FLAG_N = NFLAG_32(src);
8149 FLAG_Z = src;
8150 FLAG_V = VFLAG_CLEAR;
8151 }
8154 M68KMAKE_OP(rol, 16, ., .)
8155 {
8156 uint ea = M68KMAKE_GET_EA_AY_16;
8157 uint src = m68ki_read_16(ea);
8158 uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
8160 m68ki_write_16(ea, res);
8162 FLAG_N = NFLAG_16(res);
8163 FLAG_Z = res;
8164 FLAG_C = src >> 7;
8165 FLAG_V = VFLAG_CLEAR;
8166 }
8169 M68KMAKE_OP(roxr, 8, s, .)
8170 {
8171 uint* r_dst = &DY;
8172 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8173 uint src = MASK_OUT_ABOVE_8(*r_dst);
8174 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
8176 FLAG_C = FLAG_X = res;
8177 res = MASK_OUT_ABOVE_8(res);
8179 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8181 FLAG_N = NFLAG_8(res);
8182 FLAG_Z = res;
8183 FLAG_V = VFLAG_CLEAR;
8184 }
8187 M68KMAKE_OP(roxr, 16, s, .)
8188 {
8189 uint* r_dst = &DY;
8190 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8191 uint src = MASK_OUT_ABOVE_16(*r_dst);
8192 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
8194 FLAG_C = FLAG_X = res >> 8;
8195 res = MASK_OUT_ABOVE_16(res);
8197 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8199 FLAG_N = NFLAG_16(res);
8200 FLAG_Z = res;
8201 FLAG_V = VFLAG_CLEAR;
8202 }
8205 M68KMAKE_OP(roxr, 32, s, .)
8206 {
8207 #if M68K_USE_64_BIT
8209 uint* r_dst = &DY;
8210 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8211 uint64 src = *r_dst;
8212 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
8214 res = ROR_33_64(res, shift);
8216 FLAG_C = FLAG_X = res >> 24;
8217 res = MASK_OUT_ABOVE_32(res);
8219 *r_dst = res;
8221 FLAG_N = NFLAG_32(res);
8222 FLAG_Z = res;
8223 FLAG_V = VFLAG_CLEAR;
8225 #else
8227 uint* r_dst = &DY;
8228 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8229 uint src = *r_dst;
8230 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
8231 uint new_x_flag = src & (1 << (shift - 1));
8233 *r_dst = res;
8235 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
8236 FLAG_N = NFLAG_32(res);
8237 FLAG_Z = res;
8238 FLAG_V = VFLAG_CLEAR;
8240 #endif
8241 }
8244 M68KMAKE_OP(roxr, 8, r, .)
8245 {
8246 uint* r_dst = &DY;
8247 uint orig_shift = DX & 0x3f;
8249 if(orig_shift != 0)
8250 {
8251 uint shift = orig_shift % 9;
8252 uint src = MASK_OUT_ABOVE_8(*r_dst);
8253 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
8255 USE_CYCLES(orig_shift<<CYC_SHIFT);
8257 FLAG_C = FLAG_X = res;
8258 res = MASK_OUT_ABOVE_8(res);
8260 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8261 FLAG_N = NFLAG_8(res);
8262 FLAG_Z = res;
8263 FLAG_V = VFLAG_CLEAR;
8264 return;
8265 }
8267 FLAG_C = FLAG_X;
8268 FLAG_N = NFLAG_8(*r_dst);
8269 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
8270 FLAG_V = VFLAG_CLEAR;
8271 }
8274 M68KMAKE_OP(roxr, 16, r, .)
8275 {
8276 uint* r_dst = &DY;
8277 uint orig_shift = DX & 0x3f;
8279 if(orig_shift != 0)
8280 {
8281 uint shift = orig_shift % 17;
8282 uint src = MASK_OUT_ABOVE_16(*r_dst);
8283 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
8285 USE_CYCLES(orig_shift<<CYC_SHIFT);
8287 FLAG_C = FLAG_X = res >> 8;
8288 res = MASK_OUT_ABOVE_16(res);
8290 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8291 FLAG_N = NFLAG_16(res);
8292 FLAG_Z = res;
8293 FLAG_V = VFLAG_CLEAR;
8294 return;
8295 }
8297 FLAG_C = FLAG_X;
8298 FLAG_N = NFLAG_16(*r_dst);
8299 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
8300 FLAG_V = VFLAG_CLEAR;
8301 }
8304 M68KMAKE_OP(roxr, 32, r, .)
8305 {
8306 #if M68K_USE_64_BIT
8308 uint* r_dst = &DY;
8309 uint orig_shift = DX & 0x3f;
8311 if(orig_shift != 0)
8312 {
8313 uint shift = orig_shift % 33;
8314 uint64 src = *r_dst;
8315 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
8317 res = ROR_33_64(res, shift);
8319 USE_CYCLES(orig_shift<<CYC_SHIFT);
8321 FLAG_C = FLAG_X = res >> 24;
8322 res = MASK_OUT_ABOVE_32(res);
8324 *r_dst = res;
8325 FLAG_N = NFLAG_32(res);
8326 FLAG_Z = res;
8327 FLAG_V = VFLAG_CLEAR;
8328 return;
8329 }
8331 FLAG_C = FLAG_X;
8332 FLAG_N = NFLAG_32(*r_dst);
8333 FLAG_Z = *r_dst;
8334 FLAG_V = VFLAG_CLEAR;
8336 #else
8338 uint* r_dst = &DY;
8339 uint orig_shift = DX & 0x3f;
8340 uint shift = orig_shift % 33;
8341 uint src = *r_dst;
8342 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
8343 uint new_x_flag = src & (1 << (shift - 1));
8345 if(orig_shift != 0)
8346 USE_CYCLES(orig_shift<<CYC_SHIFT);
8348 if(shift != 0)
8349 {
8350 *r_dst = res;
8351 FLAG_X = (new_x_flag != 0)<<8;
8352 }
8353 else
8354 res = src;
8355 FLAG_C = FLAG_X;
8356 FLAG_N = NFLAG_32(res);
8357 FLAG_Z = res;
8358 FLAG_V = VFLAG_CLEAR;
8360 #endif
8361 }
8364 M68KMAKE_OP(roxr, 16, ., .)
8365 {
8366 uint ea = M68KMAKE_GET_EA_AY_16;
8367 uint src = m68ki_read_16(ea);
8368 uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
8370 FLAG_C = FLAG_X = res >> 8;
8371 res = MASK_OUT_ABOVE_16(res);
8373 m68ki_write_16(ea, res);
8375 FLAG_N = NFLAG_16(res);
8376 FLAG_Z = res;
8377 FLAG_V = VFLAG_CLEAR;
8378 }
8381 M68KMAKE_OP(roxl, 8, s, .)
8382 {
8383 uint* r_dst = &DY;
8384 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8385 uint src = MASK_OUT_ABOVE_8(*r_dst);
8386 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
8388 FLAG_C = FLAG_X = res;
8389 res = MASK_OUT_ABOVE_8(res);
8391 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8393 FLAG_N = NFLAG_8(res);
8394 FLAG_Z = res;
8395 FLAG_V = VFLAG_CLEAR;
8396 }
8399 M68KMAKE_OP(roxl, 16, s, .)
8400 {
8401 uint* r_dst = &DY;
8402 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8403 uint src = MASK_OUT_ABOVE_16(*r_dst);
8404 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
8406 FLAG_C = FLAG_X = res >> 8;
8407 res = MASK_OUT_ABOVE_16(res);
8409 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8411 FLAG_N = NFLAG_16(res);
8412 FLAG_Z = res;
8413 FLAG_V = VFLAG_CLEAR;
8414 }
8417 M68KMAKE_OP(roxl, 32, s, .)
8418 {
8419 #if M68K_USE_64_BIT
8421 uint* r_dst = &DY;
8422 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8423 uint64 src = *r_dst;
8424 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
8426 res = ROL_33_64(res, shift);
8428 FLAG_C = FLAG_X = res >> 24;
8429 res = MASK_OUT_ABOVE_32(res);
8431 *r_dst = res;
8433 FLAG_N = NFLAG_32(res);
8434 FLAG_Z = res;
8435 FLAG_V = VFLAG_CLEAR;
8437 #else
8439 uint* r_dst = &DY;
8440 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
8441 uint src = *r_dst;
8442 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
8443 uint new_x_flag = src & (1 << (32 - shift));
8445 *r_dst = res;
8447 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
8448 FLAG_N = NFLAG_32(res);
8449 FLAG_Z = res;
8450 FLAG_V = VFLAG_CLEAR;
8452 #endif
8453 }
8456 M68KMAKE_OP(roxl, 8, r, .)
8457 {
8458 uint* r_dst = &DY;
8459 uint orig_shift = DX & 0x3f;
8462 if(orig_shift != 0)
8463 {
8464 uint shift = orig_shift % 9;
8465 uint src = MASK_OUT_ABOVE_8(*r_dst);
8466 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
8468 USE_CYCLES(orig_shift<<CYC_SHIFT);
8470 FLAG_C = FLAG_X = res;
8471 res = MASK_OUT_ABOVE_8(res);
8473 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8474 FLAG_N = NFLAG_8(res);
8475 FLAG_Z = res;
8476 FLAG_V = VFLAG_CLEAR;
8477 return;
8478 }
8480 FLAG_C = FLAG_X;
8481 FLAG_N = NFLAG_8(*r_dst);
8482 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
8483 FLAG_V = VFLAG_CLEAR;
8484 }
8487 M68KMAKE_OP(roxl, 16, r, .)
8488 {
8489 uint* r_dst = &DY;
8490 uint orig_shift = DX & 0x3f;
8492 if(orig_shift != 0)
8493 {
8494 uint shift = orig_shift % 17;
8495 uint src = MASK_OUT_ABOVE_16(*r_dst);
8496 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
8498 USE_CYCLES(orig_shift<<CYC_SHIFT);
8500 FLAG_C = FLAG_X = res >> 8;
8501 res = MASK_OUT_ABOVE_16(res);
8503 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
8504 FLAG_N = NFLAG_16(res);
8505 FLAG_Z = res;
8506 FLAG_V = VFLAG_CLEAR;
8507 return;
8508 }
8510 FLAG_C = FLAG_X;
8511 FLAG_N = NFLAG_16(*r_dst);
8512 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
8513 FLAG_V = VFLAG_CLEAR;
8514 }
8517 M68KMAKE_OP(roxl, 32, r, .)
8518 {
8519 #if M68K_USE_64_BIT
8521 uint* r_dst = &DY;
8522 uint orig_shift = DX & 0x3f;
8524 if(orig_shift != 0)
8525 {
8526 uint shift = orig_shift % 33;
8527 uint64 src = *r_dst;
8528 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
8530 res = ROL_33_64(res, shift);
8532 USE_CYCLES(orig_shift<<CYC_SHIFT);
8534 FLAG_C = FLAG_X = res >> 24;
8535 res = MASK_OUT_ABOVE_32(res);
8537 *r_dst = res;
8538 FLAG_N = NFLAG_32(res);
8539 FLAG_Z = res;
8540 FLAG_V = VFLAG_CLEAR;
8541 return;
8542 }
8544 FLAG_C = FLAG_X;
8545 FLAG_N = NFLAG_32(*r_dst);
8546 FLAG_Z = *r_dst;
8547 FLAG_V = VFLAG_CLEAR;
8549 #else
8551 uint* r_dst = &DY;
8552 uint orig_shift = DX & 0x3f;
8553 uint shift = orig_shift % 33;
8554 uint src = *r_dst;
8555 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
8556 uint new_x_flag = src & (1 << (32 - shift));
8558 if(orig_shift != 0)
8559 USE_CYCLES(orig_shift<<CYC_SHIFT);
8561 if(shift != 0)
8562 {
8563 *r_dst = res;
8564 FLAG_X = (new_x_flag != 0)<<8;
8565 }
8566 else
8567 res = src;
8568 FLAG_C = FLAG_X;
8569 FLAG_N = NFLAG_32(res);
8570 FLAG_Z = res;
8571 FLAG_V = VFLAG_CLEAR;
8573 #endif
8574 }
8577 M68KMAKE_OP(roxl, 16, ., .)
8578 {
8579 uint ea = M68KMAKE_GET_EA_AY_16;
8580 uint src = m68ki_read_16(ea);
8581 uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
8583 FLAG_C = FLAG_X = res >> 8;
8584 res = MASK_OUT_ABOVE_16(res);
8586 m68ki_write_16(ea, res);
8588 FLAG_N = NFLAG_16(res);
8589 FLAG_Z = res;
8590 FLAG_V = VFLAG_CLEAR;
8591 }
8594 M68KMAKE_OP(rtd, 32, ., .)
8595 {
8596 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
8597 {
8598 uint new_pc = m68ki_pull_32();
8600 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
8601 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
8602 m68ki_jump(new_pc);
8603 return;
8604 }
8605 m68ki_exception_illegal();
8606 }
8609 M68KMAKE_OP(rte, 32, ., .)
8610 {
8611 if(FLAG_S)
8612 {
8613 uint new_sr;
8614 uint new_pc;
8615 uint format_word;
8617 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
8619 if(CPU_TYPE_IS_000(CPU_TYPE))
8620 {
8621 new_sr = m68ki_pull_16();
8622 new_pc = m68ki_pull_32();
8623 m68ki_jump(new_pc);
8624 m68ki_set_sr(new_sr);
8625 return;
8626 }
8628 if(CPU_TYPE_IS_010(CPU_TYPE))
8629 {
8630 format_word = m68ki_read_16(REG_A[7]+6) >> 12;
8631 if(format_word == 0)
8632 {
8633 new_sr = m68ki_pull_16();
8634 new_pc = m68ki_pull_32();
8635 m68ki_fake_pull_16(); /* format word */
8636 m68ki_jump(new_pc);
8637 m68ki_set_sr(new_sr);
8638 return;
8639 } else if (format_word == 8) {
8640 /* Format 8 stack frame -- 68010 only. 29 word bus/address error */
8641 new_sr = m68ki_pull_16();
8642 new_pc = m68ki_pull_32();
8643 m68ki_fake_pull_16(); /* format word */
8644 m68ki_fake_pull_16(); /* special status word */
8645 m68ki_fake_pull_32(); /* fault address */
8646 m68ki_fake_pull_16(); /* unused/reserved */
8647 m68ki_fake_pull_16(); /* data output buffer */
8648 m68ki_fake_pull_16(); /* unused/reserved */
8649 m68ki_fake_pull_16(); /* data input buffer */
8650 m68ki_fake_pull_16(); /* unused/reserved */
8651 m68ki_fake_pull_16(); /* instruction input buffer */
8652 m68ki_fake_pull_32(); /* internal information, 16 words */
8653 m68ki_fake_pull_32(); /* (actually, we use 8 DWORDs) */
8654 m68ki_fake_pull_32();
8655 m68ki_fake_pull_32();
8656 m68ki_fake_pull_32();
8657 m68ki_fake_pull_32();
8658 m68ki_fake_pull_32();
8659 m68ki_fake_pull_32();
8660 m68ki_jump(new_pc);
8661 m68ki_set_sr(new_sr);
8662 return;
8663 }
8664 /* FIXME: Not handling other exception types (9) */
8665 m68ki_exception_format_error();
8666 return;
8667 }
8669 /* Otherwise it's 020 */
8670 rte_loop:
8671 format_word = m68ki_read_16(REG_A[7]+6) >> 12;
8672 switch(format_word)
8673 {
8674 case 0: /* Normal */
8675 new_sr = m68ki_pull_16();
8676 new_pc = m68ki_pull_32();
8677 m68ki_fake_pull_16(); /* format word */
8678 m68ki_jump(new_pc);
8679 m68ki_set_sr(new_sr);
8680 return;
8681 case 1: /* Throwaway */
8682 new_sr = m68ki_pull_16();
8683 m68ki_fake_pull_32(); /* program counter */
8684 m68ki_fake_pull_16(); /* format word */
8685 m68ki_set_sr_noint(new_sr);
8686 goto rte_loop;
8687 case 2: /* Trap */
8688 new_sr = m68ki_pull_16();
8689 new_pc = m68ki_pull_32();
8690 m68ki_fake_pull_16(); /* format word */
8691 m68ki_fake_pull_32(); /* address */
8692 m68ki_jump(new_pc);
8693 m68ki_set_sr(new_sr);
8694 return;
8695 }
8696 /* FIXME: Not handling long or short bus fault */
8697 m68ki_exception_format_error();
8698 return;
8699 }
8700 m68ki_exception_privilege_violation();
8701 }
8704 M68KMAKE_OP(rtm, 32, ., .)
8705 {
8706 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
8707 {
8708 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
8709 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
8710 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
8711 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
8712 return;
8713 }
8714 m68ki_exception_illegal();
8715 }
8718 M68KMAKE_OP(rtr, 32, ., .)
8719 {
8720 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
8721 m68ki_set_ccr(m68ki_pull_16());
8722 m68ki_jump(m68ki_pull_32());
8723 }
8726 M68KMAKE_OP(rts, 32, ., .)
8727 {
8728 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
8729 m68ki_jump(m68ki_pull_32());
8730 }
8733 M68KMAKE_OP(sbcd, 8, rr, .)
8734 {
8735 uint* r_dst = &DX;
8736 uint src = DY;
8737 uint dst = *r_dst;
8738 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
8740 if(res > 9)
8741 res -= 6;
8742 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
8743 FLAG_X = FLAG_C = (res > 0x99) << 8;
8744 if(FLAG_C)
8745 res += 0xa0;
8747 res = MASK_OUT_ABOVE_8(res);
8749 FLAG_N = NFLAG_8(res); /* officially undefined */
8750 FLAG_Z |= res;
8752 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
8753 }
8756 M68KMAKE_OP(sbcd, 8, mm, ax7)
8757 {
8758 uint src = OPER_AY_PD_8();
8759 uint ea = EA_A7_PD_8();
8760 uint dst = m68ki_read_8(ea);
8761 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
8763 if(res > 9)
8764 res -= 6;
8765 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
8766 FLAG_X = FLAG_C = (res > 0x99) << 8;
8767 if(FLAG_C)
8768 res += 0xa0;
8770 res = MASK_OUT_ABOVE_8(res);
8772 FLAG_N = NFLAG_8(res); /* officially undefined */
8773 FLAG_Z |= res;
8775 m68ki_write_8(ea, res);
8776 }
8779 M68KMAKE_OP(sbcd, 8, mm, ay7)
8780 {
8781 uint src = OPER_A7_PD_8();
8782 uint ea = EA_AX_PD_8();
8783 uint dst = m68ki_read_8(ea);
8784 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
8786 if(res > 9)
8787 res -= 6;
8788 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
8789 FLAG_X = FLAG_C = (res > 0x99) << 8;
8790 if(FLAG_C)
8791 res += 0xa0;
8793 res = MASK_OUT_ABOVE_8(res);
8795 FLAG_N = NFLAG_8(res); /* officially undefined */
8796 FLAG_Z |= res;
8798 m68ki_write_8(ea, res);
8799 }
8802 M68KMAKE_OP(sbcd, 8, mm, axy7)
8803 {
8804 uint src = OPER_A7_PD_8();
8805 uint ea = EA_A7_PD_8();
8806 uint dst = m68ki_read_8(ea);
8807 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
8809 if(res > 9)
8810 res -= 6;
8811 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
8812 FLAG_X = FLAG_C = (res > 0x99) << 8;
8813 if(FLAG_C)
8814 res += 0xa0;
8816 res = MASK_OUT_ABOVE_8(res);
8818 FLAG_N = NFLAG_8(res); /* officially undefined */
8819 FLAG_Z |= res;
8821 m68ki_write_8(ea, res);
8822 }
8825 M68KMAKE_OP(sbcd, 8, mm, .)
8826 {
8827 uint src = OPER_AY_PD_8();
8828 uint ea = EA_AX_PD_8();
8829 uint dst = m68ki_read_8(ea);
8830 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
8832 if(res > 9)
8833 res -= 6;
8834 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
8835 FLAG_X = FLAG_C = (res > 0x99) << 8;
8836 if(FLAG_C)
8837 res += 0xa0;
8839 res = MASK_OUT_ABOVE_8(res);
8841 FLAG_N = NFLAG_8(res); /* officially undefined */
8842 FLAG_Z |= res;
8844 m68ki_write_8(ea, res);
8845 }
8848 M68KMAKE_OP(st, 8, ., d)
8849 {
8850 DY |= 0xff;
8851 }
8854 M68KMAKE_OP(st, 8, ., .)
8855 {
8856 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0xff);
8857 }
8860 M68KMAKE_OP(sf, 8, ., d)
8861 {
8862 DY &= 0xffffff00;
8863 }
8866 M68KMAKE_OP(sf, 8, ., .)
8867 {
8868 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
8869 }
8872 M68KMAKE_OP(scc, 8, ., d)
8873 {
8874 if(M68KMAKE_CC)
8875 {
8876 DY |= 0xff;
8877 return;
8878 }
8879 DY &= 0xffffff00;
8880 }
8883 M68KMAKE_OP(scc, 8, ., .)
8884 {
8885 m68ki_write_8(M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0);
8886 }
8889 M68KMAKE_OP(stop, 0, ., .)
8890 {
8891 if(FLAG_S)
8892 {
8893 uint new_sr = OPER_I_16();
8894 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
8895 CPU_STOPPED |= STOP_LEVEL_STOP;
8896 m68ki_set_sr(new_sr);
8897 m68ki_remaining_cycles = 0;
8898 return;
8899 }
8900 m68ki_exception_privilege_violation();
8901 }
8904 M68KMAKE_OP(sub, 8, er, d)
8905 {
8906 uint* r_dst = &DX;
8907 uint src = MASK_OUT_ABOVE_8(DY);
8908 uint dst = MASK_OUT_ABOVE_8(*r_dst);
8909 uint res = dst - src;
8911 FLAG_N = NFLAG_8(res);
8912 FLAG_X = FLAG_C = CFLAG_8(res);
8913 FLAG_V = VFLAG_SUB_8(src, dst, res);
8914 FLAG_Z = MASK_OUT_ABOVE_8(res);
8916 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
8917 }
8920 M68KMAKE_OP(sub, 8, er, .)
8921 {
8922 uint* r_dst = &DX;
8923 uint src = M68KMAKE_GET_OPER_AY_8;
8924 uint dst = MASK_OUT_ABOVE_8(*r_dst);
8925 uint res = dst - src;
8927 FLAG_N = NFLAG_8(res);
8928 FLAG_X = FLAG_C = CFLAG_8(res);
8929 FLAG_V = VFLAG_SUB_8(src, dst, res);
8930 FLAG_Z = MASK_OUT_ABOVE_8(res);
8932 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
8933 }
8936 M68KMAKE_OP(sub, 16, er, d)
8937 {
8938 uint* r_dst = &DX;
8939 uint src = MASK_OUT_ABOVE_16(DY);
8940 uint dst = MASK_OUT_ABOVE_16(*r_dst);
8941 uint res = dst - src;
8943 FLAG_N = NFLAG_16(res);
8944 FLAG_X = FLAG_C = CFLAG_16(res);
8945 FLAG_V = VFLAG_SUB_16(src, dst, res);
8946 FLAG_Z = MASK_OUT_ABOVE_16(res);
8948 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
8949 }
8952 M68KMAKE_OP(sub, 16, er, a)
8953 {
8954 uint* r_dst = &DX;
8955 uint src = MASK_OUT_ABOVE_16(AY);
8956 uint dst = MASK_OUT_ABOVE_16(*r_dst);
8957 uint res = dst - src;
8959 FLAG_N = NFLAG_16(res);
8960 FLAG_X = FLAG_C = CFLAG_16(res);
8961 FLAG_V = VFLAG_SUB_16(src, dst, res);
8962 FLAG_Z = MASK_OUT_ABOVE_16(res);
8964 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
8965 }
8968 M68KMAKE_OP(sub, 16, er, .)
8969 {
8970 uint* r_dst = &DX;
8971 uint src = M68KMAKE_GET_OPER_AY_16;
8972 uint dst = MASK_OUT_ABOVE_16(*r_dst);
8973 uint res = dst - src;
8975 FLAG_N = NFLAG_16(res);
8976 FLAG_X = FLAG_C = CFLAG_16(res);
8977 FLAG_V = VFLAG_SUB_16(src, dst, res);
8978 FLAG_Z = MASK_OUT_ABOVE_16(res);
8980 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
8981 }
8984 M68KMAKE_OP(sub, 32, er, d)
8985 {
8986 uint* r_dst = &DX;
8987 uint src = DY;
8988 uint dst = *r_dst;
8989 uint res = dst - src;
8991 FLAG_N = NFLAG_32(res);
8992 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
8993 FLAG_V = VFLAG_SUB_32(src, dst, res);
8994 FLAG_Z = MASK_OUT_ABOVE_32(res);
8996 *r_dst = FLAG_Z;
8997 }
9000 M68KMAKE_OP(sub, 32, er, a)
9001 {
9002 uint* r_dst = &DX;
9003 uint src = AY;
9004 uint dst = *r_dst;
9005 uint res = dst - src;
9007 FLAG_N = NFLAG_32(res);
9008 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9009 FLAG_V = VFLAG_SUB_32(src, dst, res);
9010 FLAG_Z = MASK_OUT_ABOVE_32(res);
9012 *r_dst = FLAG_Z;
9013 }
9016 M68KMAKE_OP(sub, 32, er, .)
9017 {
9018 uint* r_dst = &DX;
9019 uint src = M68KMAKE_GET_OPER_AY_32;
9020 uint dst = *r_dst;
9021 uint res = dst - src;
9023 FLAG_N = NFLAG_32(res);
9024 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9025 FLAG_V = VFLAG_SUB_32(src, dst, res);
9026 FLAG_Z = MASK_OUT_ABOVE_32(res);
9028 *r_dst = FLAG_Z;
9029 }
9032 M68KMAKE_OP(sub, 8, re, .)
9033 {
9034 uint ea = M68KMAKE_GET_EA_AY_8;
9035 uint src = MASK_OUT_ABOVE_8(DX);
9036 uint dst = m68ki_read_8(ea);
9037 uint res = dst - src;
9039 FLAG_N = NFLAG_8(res);
9040 FLAG_Z = MASK_OUT_ABOVE_8(res);
9041 FLAG_X = FLAG_C = CFLAG_8(res);
9042 FLAG_V = VFLAG_SUB_8(src, dst, res);
9044 m68ki_write_8(ea, FLAG_Z);
9045 }
9048 M68KMAKE_OP(sub, 16, re, .)
9049 {
9050 uint ea = M68KMAKE_GET_EA_AY_16;
9051 uint src = MASK_OUT_ABOVE_16(DX);
9052 uint dst = m68ki_read_16(ea);
9053 uint res = dst - src;
9055 FLAG_N = NFLAG_16(res);
9056 FLAG_Z = MASK_OUT_ABOVE_16(res);
9057 FLAG_X = FLAG_C = CFLAG_16(res);
9058 FLAG_V = VFLAG_SUB_16(src, dst, res);
9060 m68ki_write_16(ea, FLAG_Z);
9061 }
9064 M68KMAKE_OP(sub, 32, re, .)
9065 {
9066 uint ea = M68KMAKE_GET_EA_AY_32;
9067 uint src = DX;
9068 uint dst = m68ki_read_32(ea);
9069 uint res = dst - src;
9071 FLAG_N = NFLAG_32(res);
9072 FLAG_Z = MASK_OUT_ABOVE_32(res);
9073 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9074 FLAG_V = VFLAG_SUB_32(src, dst, res);
9076 m68ki_write_32(ea, FLAG_Z);
9077 }
9080 M68KMAKE_OP(suba, 16, ., d)
9081 {
9082 uint* r_dst = &AX;
9084 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));
9085 }
9088 M68KMAKE_OP(suba, 16, ., a)
9089 {
9090 uint* r_dst = &AX;
9092 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));
9093 }
9096 M68KMAKE_OP(suba, 16, ., .)
9097 {
9098 uint* r_dst = &AX;
9100 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(M68KMAKE_GET_OPER_AY_16));
9101 }
9104 M68KMAKE_OP(suba, 32, ., d)
9105 {
9106 uint* r_dst = &AX;
9108 *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);
9109 }
9112 M68KMAKE_OP(suba, 32, ., a)
9113 {
9114 uint* r_dst = &AX;
9116 *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);
9117 }
9120 M68KMAKE_OP(suba, 32, ., .)
9121 {
9122 uint* r_dst = &AX;
9124 *r_dst = MASK_OUT_ABOVE_32(*r_dst - M68KMAKE_GET_OPER_AY_32);
9125 }
9128 M68KMAKE_OP(subi, 8, ., d)
9129 {
9130 uint* r_dst = &DY;
9131 uint src = OPER_I_8();
9132 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9133 uint res = dst - src;
9135 FLAG_N = NFLAG_8(res);
9136 FLAG_Z = MASK_OUT_ABOVE_8(res);
9137 FLAG_X = FLAG_C = CFLAG_8(res);
9138 FLAG_V = VFLAG_SUB_8(src, dst, res);
9140 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
9141 }
9144 M68KMAKE_OP(subi, 8, ., .)
9145 {
9146 uint src = OPER_I_8();
9147 uint ea = M68KMAKE_GET_EA_AY_8;
9148 uint dst = m68ki_read_8(ea);
9149 uint res = dst - src;
9151 FLAG_N = NFLAG_8(res);
9152 FLAG_Z = MASK_OUT_ABOVE_8(res);
9153 FLAG_X = FLAG_C = CFLAG_8(res);
9154 FLAG_V = VFLAG_SUB_8(src, dst, res);
9156 m68ki_write_8(ea, FLAG_Z);
9157 }
9160 M68KMAKE_OP(subi, 16, ., d)
9161 {
9162 uint* r_dst = &DY;
9163 uint src = OPER_I_16();
9164 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9165 uint res = dst - src;
9167 FLAG_N = NFLAG_16(res);
9168 FLAG_Z = MASK_OUT_ABOVE_16(res);
9169 FLAG_X = FLAG_C = CFLAG_16(res);
9170 FLAG_V = VFLAG_SUB_16(src, dst, res);
9172 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9173 }
9176 M68KMAKE_OP(subi, 16, ., .)
9177 {
9178 uint src = OPER_I_16();
9179 uint ea = M68KMAKE_GET_EA_AY_16;
9180 uint dst = m68ki_read_16(ea);
9181 uint res = dst - src;
9183 FLAG_N = NFLAG_16(res);
9184 FLAG_Z = MASK_OUT_ABOVE_16(res);
9185 FLAG_X = FLAG_C = CFLAG_16(res);
9186 FLAG_V = VFLAG_SUB_16(src, dst, res);
9188 m68ki_write_16(ea, FLAG_Z);
9189 }
9192 M68KMAKE_OP(subi, 32, ., d)
9193 {
9194 uint* r_dst = &DY;
9195 uint src = OPER_I_32();
9196 uint dst = *r_dst;
9197 uint res = dst - src;
9199 FLAG_N = NFLAG_32(res);
9200 FLAG_Z = MASK_OUT_ABOVE_32(res);
9201 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9202 FLAG_V = VFLAG_SUB_32(src, dst, res);
9204 *r_dst = FLAG_Z;
9205 }
9208 M68KMAKE_OP(subi, 32, ., .)
9209 {
9210 uint src = OPER_I_32();
9211 uint ea = M68KMAKE_GET_EA_AY_32;
9212 uint dst = m68ki_read_32(ea);
9213 uint res = dst - src;
9215 FLAG_N = NFLAG_32(res);
9216 FLAG_Z = MASK_OUT_ABOVE_32(res);
9217 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9218 FLAG_V = VFLAG_SUB_32(src, dst, res);
9220 m68ki_write_32(ea, FLAG_Z);
9221 }
9224 M68KMAKE_OP(subq, 8, ., d)
9225 {
9226 uint* r_dst = &DY;
9227 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9228 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9229 uint res = dst - src;
9231 FLAG_N = NFLAG_8(res);
9232 FLAG_Z = MASK_OUT_ABOVE_8(res);
9233 FLAG_X = FLAG_C = CFLAG_8(res);
9234 FLAG_V = VFLAG_SUB_8(src, dst, res);
9236 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
9237 }
9240 M68KMAKE_OP(subq, 8, ., .)
9241 {
9242 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9243 uint ea = M68KMAKE_GET_EA_AY_8;
9244 uint dst = m68ki_read_8(ea);
9245 uint res = dst - src;
9247 FLAG_N = NFLAG_8(res);
9248 FLAG_Z = MASK_OUT_ABOVE_8(res);
9249 FLAG_X = FLAG_C = CFLAG_8(res);
9250 FLAG_V = VFLAG_SUB_8(src, dst, res);
9252 m68ki_write_8(ea, FLAG_Z);
9253 }
9256 M68KMAKE_OP(subq, 16, ., d)
9257 {
9258 uint* r_dst = &DY;
9259 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9260 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9261 uint res = dst - src;
9263 FLAG_N = NFLAG_16(res);
9264 FLAG_Z = MASK_OUT_ABOVE_16(res);
9265 FLAG_X = FLAG_C = CFLAG_16(res);
9266 FLAG_V = VFLAG_SUB_16(src, dst, res);
9268 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
9269 }
9272 M68KMAKE_OP(subq, 16, ., a)
9273 {
9274 uint* r_dst = &AY;
9276 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
9277 }
9280 M68KMAKE_OP(subq, 16, ., .)
9281 {
9282 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9283 uint ea = M68KMAKE_GET_EA_AY_16;
9284 uint dst = m68ki_read_16(ea);
9285 uint res = dst - src;
9287 FLAG_N = NFLAG_16(res);
9288 FLAG_Z = MASK_OUT_ABOVE_16(res);
9289 FLAG_X = FLAG_C = CFLAG_16(res);
9290 FLAG_V = VFLAG_SUB_16(src, dst, res);
9292 m68ki_write_16(ea, FLAG_Z);
9293 }
9296 M68KMAKE_OP(subq, 32, ., d)
9297 {
9298 uint* r_dst = &DY;
9299 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9300 uint dst = *r_dst;
9301 uint res = dst - src;
9303 FLAG_N = NFLAG_32(res);
9304 FLAG_Z = MASK_OUT_ABOVE_32(res);
9305 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9306 FLAG_V = VFLAG_SUB_32(src, dst, res);
9308 *r_dst = FLAG_Z;
9309 }
9312 M68KMAKE_OP(subq, 32, ., a)
9313 {
9314 uint* r_dst = &AY;
9316 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
9317 }
9320 M68KMAKE_OP(subq, 32, ., .)
9321 {
9322 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
9323 uint ea = M68KMAKE_GET_EA_AY_32;
9324 uint dst = m68ki_read_32(ea);
9325 uint res = dst - src;
9327 FLAG_N = NFLAG_32(res);
9328 FLAG_Z = MASK_OUT_ABOVE_32(res);
9329 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9330 FLAG_V = VFLAG_SUB_32(src, dst, res);
9332 m68ki_write_32(ea, FLAG_Z);
9333 }
9336 M68KMAKE_OP(subx, 8, rr, .)
9337 {
9338 uint* r_dst = &DX;
9339 uint src = MASK_OUT_ABOVE_8(DY);
9340 uint dst = MASK_OUT_ABOVE_8(*r_dst);
9341 uint res = dst - src - XFLAG_AS_1();
9343 FLAG_N = NFLAG_8(res);
9344 FLAG_X = FLAG_C = CFLAG_8(res);
9345 FLAG_V = VFLAG_SUB_8(src, dst, res);
9347 res = MASK_OUT_ABOVE_8(res);
9348 FLAG_Z |= res;
9350 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
9351 }
9354 M68KMAKE_OP(subx, 16, rr, .)
9355 {
9356 uint* r_dst = &DX;
9357 uint src = MASK_OUT_ABOVE_16(DY);
9358 uint dst = MASK_OUT_ABOVE_16(*r_dst);
9359 uint res = dst - src - XFLAG_AS_1();
9361 FLAG_N = NFLAG_16(res);
9362 FLAG_X = FLAG_C = CFLAG_16(res);
9363 FLAG_V = VFLAG_SUB_16(src, dst, res);
9365 res = MASK_OUT_ABOVE_16(res);
9366 FLAG_Z |= res;
9368 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
9369 }
9372 M68KMAKE_OP(subx, 32, rr, .)
9373 {
9374 uint* r_dst = &DX;
9375 uint src = DY;
9376 uint dst = *r_dst;
9377 uint res = dst - src - XFLAG_AS_1();
9379 FLAG_N = NFLAG_32(res);
9380 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9381 FLAG_V = VFLAG_SUB_32(src, dst, res);
9383 res = MASK_OUT_ABOVE_32(res);
9384 FLAG_Z |= res;
9386 *r_dst = res;
9387 }
9390 M68KMAKE_OP(subx, 8, mm, ax7)
9391 {
9392 uint src = OPER_AY_PD_8();
9393 uint ea = EA_A7_PD_8();
9394 uint dst = m68ki_read_8(ea);
9395 uint res = dst - src - XFLAG_AS_1();
9397 FLAG_N = NFLAG_8(res);
9398 FLAG_X = FLAG_C = CFLAG_8(res);
9399 FLAG_V = VFLAG_SUB_8(src, dst, res);
9401 res = MASK_OUT_ABOVE_8(res);
9402 FLAG_Z |= res;
9404 m68ki_write_8(ea, res);
9405 }
9408 M68KMAKE_OP(subx, 8, mm, ay7)
9409 {
9410 uint src = OPER_A7_PD_8();
9411 uint ea = EA_AX_PD_8();
9412 uint dst = m68ki_read_8(ea);
9413 uint res = dst - src - XFLAG_AS_1();
9415 FLAG_N = NFLAG_8(res);
9416 FLAG_X = FLAG_C = CFLAG_8(res);
9417 FLAG_V = VFLAG_SUB_8(src, dst, res);
9419 res = MASK_OUT_ABOVE_8(res);
9420 FLAG_Z |= res;
9422 m68ki_write_8(ea, res);
9423 }
9426 M68KMAKE_OP(subx, 8, mm, axy7)
9427 {
9428 uint src = OPER_A7_PD_8();
9429 uint ea = EA_A7_PD_8();
9430 uint dst = m68ki_read_8(ea);
9431 uint res = dst - src - XFLAG_AS_1();
9433 FLAG_N = NFLAG_8(res);
9434 FLAG_X = FLAG_C = CFLAG_8(res);
9435 FLAG_V = VFLAG_SUB_8(src, dst, res);
9437 res = MASK_OUT_ABOVE_8(res);
9438 FLAG_Z |= res;
9440 m68ki_write_8(ea, res);
9441 }
9444 M68KMAKE_OP(subx, 8, mm, .)
9445 {
9446 uint src = OPER_AY_PD_8();
9447 uint ea = EA_AX_PD_8();
9448 uint dst = m68ki_read_8(ea);
9449 uint res = dst - src - XFLAG_AS_1();
9451 FLAG_N = NFLAG_8(res);
9452 FLAG_X = FLAG_C = CFLAG_8(res);
9453 FLAG_V = VFLAG_SUB_8(src, dst, res);
9455 res = MASK_OUT_ABOVE_8(res);
9456 FLAG_Z |= res;
9458 m68ki_write_8(ea, res);
9459 }
9462 M68KMAKE_OP(subx, 16, mm, .)
9463 {
9464 uint src = OPER_AY_PD_16();
9465 uint ea = EA_AX_PD_16();
9466 uint dst = m68ki_read_16(ea);
9467 uint res = dst - src - XFLAG_AS_1();
9469 FLAG_N = NFLAG_16(res);
9470 FLAG_X = FLAG_C = CFLAG_16(res);
9471 FLAG_V = VFLAG_SUB_16(src, dst, res);
9473 res = MASK_OUT_ABOVE_16(res);
9474 FLAG_Z |= res;
9476 m68ki_write_16(ea, res);
9477 }
9480 M68KMAKE_OP(subx, 32, mm, .)
9481 {
9482 uint src = OPER_AY_PD_32();
9483 uint ea = EA_AX_PD_32();
9484 uint dst = m68ki_read_32(ea);
9485 uint res = dst - src - XFLAG_AS_1();
9487 FLAG_N = NFLAG_32(res);
9488 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
9489 FLAG_V = VFLAG_SUB_32(src, dst, res);
9491 res = MASK_OUT_ABOVE_32(res);
9492 FLAG_Z |= res;
9494 m68ki_write_32(ea, res);
9495 }
9498 M68KMAKE_OP(swap, 32, ., .)
9499 {
9500 uint* r_dst = &DY;
9502 FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);
9503 *r_dst = (*r_dst>>16) | FLAG_Z;
9505 FLAG_Z = *r_dst;
9506 FLAG_N = NFLAG_32(*r_dst);
9507 FLAG_C = CFLAG_CLEAR;
9508 FLAG_V = VFLAG_CLEAR;
9509 }
9512 M68KMAKE_OP(tas, 8, ., d)
9513 {
9514 uint* r_dst = &DY;
9516 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
9517 FLAG_N = NFLAG_8(*r_dst);
9518 FLAG_V = VFLAG_CLEAR;
9519 FLAG_C = CFLAG_CLEAR;
9520 *r_dst |= 0x80;
9521 }
9524 M68KMAKE_OP(tas, 8, ., .)
9525 {
9526 uint ea = M68KMAKE_GET_EA_AY_8;
9527 uint dst = m68ki_read_8(ea);
9529 FLAG_Z = dst;
9530 FLAG_N = NFLAG_8(dst);
9531 FLAG_V = VFLAG_CLEAR;
9532 FLAG_C = CFLAG_CLEAR;
9533 m68ki_write_8(ea, dst | 0x80);
9534 }
9537 M68KMAKE_OP(trap, 0, ., .)
9538 {
9539 /* Trap#n stacks exception frame type 0 */
9540 m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */
9541 }
9544 M68KMAKE_OP(trapt, 0, ., .)
9545 {
9546 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9547 {
9548 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
9549 return;
9550 }
9551 m68ki_exception_illegal();
9552 }
9555 M68KMAKE_OP(trapt, 16, ., .)
9556 {
9557 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9558 {
9559 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
9560 return;
9561 }
9562 m68ki_exception_illegal();
9563 }
9566 M68KMAKE_OP(trapt, 32, ., .)
9567 {
9568 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9569 {
9570 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
9571 return;
9572 }
9573 m68ki_exception_illegal();
9574 }
9577 M68KMAKE_OP(trapf, 0, ., .)
9578 {
9579 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9580 {
9581 return;
9582 }
9583 m68ki_exception_illegal();
9584 }
9587 M68KMAKE_OP(trapf, 16, ., .)
9588 {
9589 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9590 {
9591 REG_PC += 2;
9592 return;
9593 }
9594 m68ki_exception_illegal();
9595 }
9598 M68KMAKE_OP(trapf, 32, ., .)
9599 {
9600 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9601 {
9602 REG_PC += 4;
9603 return;
9604 }
9605 m68ki_exception_illegal();
9606 }
9609 M68KMAKE_OP(trapcc, 0, ., .)
9610 {
9611 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9612 {
9613 if(M68KMAKE_CC)
9614 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
9615 return;
9616 }
9617 m68ki_exception_illegal();
9618 }
9621 M68KMAKE_OP(trapcc, 16, ., .)
9622 {
9623 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9624 {
9625 if(M68KMAKE_CC)
9626 {
9627 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
9628 return;
9629 }
9630 REG_PC += 2;
9631 return;
9632 }
9633 m68ki_exception_illegal();
9634 }
9637 M68KMAKE_OP(trapcc, 32, ., .)
9638 {
9639 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9640 {
9641 if(M68KMAKE_CC)
9642 {
9643 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
9644 return;
9645 }
9646 REG_PC += 4;
9647 return;
9648 }
9649 m68ki_exception_illegal();
9650 }
9653 M68KMAKE_OP(trapv, 0, ., .)
9654 {
9655 if(COND_VC())
9656 {
9657 return;
9658 }
9659 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
9660 }
9663 M68KMAKE_OP(tst, 8, ., d)
9664 {
9665 uint res = MASK_OUT_ABOVE_8(DY);
9667 FLAG_N = NFLAG_8(res);
9668 FLAG_Z = res;
9669 FLAG_V = VFLAG_CLEAR;
9670 FLAG_C = CFLAG_CLEAR;
9671 }
9674 M68KMAKE_OP(tst, 8, ., .)
9675 {
9676 uint ea = M68KMAKE_GET_EA_AY_8;
9677 uint res = m68ki_read_8(ea);
9679 FLAG_N = NFLAG_8(res);
9680 FLAG_Z = res;
9681 FLAG_V = VFLAG_CLEAR;
9682 FLAG_C = CFLAG_CLEAR;
9683 }
9686 M68KMAKE_OP(tst, 8, ., pcdi)
9687 {
9688 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9689 {
9690 uint res = OPER_PCDI_8();
9692 FLAG_N = NFLAG_8(res);
9693 FLAG_Z = res;
9694 FLAG_V = VFLAG_CLEAR;
9695 FLAG_C = CFLAG_CLEAR;
9696 return;
9697 }
9698 m68ki_exception_illegal();
9699 }
9702 M68KMAKE_OP(tst, 8, ., pcix)
9703 {
9704 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9705 {
9706 uint res = OPER_PCIX_8();
9708 FLAG_N = NFLAG_8(res);
9709 FLAG_Z = res;
9710 FLAG_V = VFLAG_CLEAR;
9711 FLAG_C = CFLAG_CLEAR;
9712 return;
9713 }
9714 m68ki_exception_illegal();
9715 }
9718 M68KMAKE_OP(tst, 8, ., i)
9719 {
9720 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9721 {
9722 uint res = OPER_I_8();
9724 FLAG_N = NFLAG_8(res);
9725 FLAG_Z = res;
9726 FLAG_V = VFLAG_CLEAR;
9727 FLAG_C = CFLAG_CLEAR;
9728 return;
9729 }
9730 m68ki_exception_illegal();
9731 }
9734 M68KMAKE_OP(tst, 16, ., d)
9735 {
9736 uint res = MASK_OUT_ABOVE_16(DY);
9738 FLAG_N = NFLAG_16(res);
9739 FLAG_Z = res;
9740 FLAG_V = VFLAG_CLEAR;
9741 FLAG_C = CFLAG_CLEAR;
9742 }
9745 M68KMAKE_OP(tst, 16, ., a)
9746 {
9747 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9748 {
9749 uint res = MAKE_INT_16(AY);
9751 FLAG_N = NFLAG_16(res);
9752 FLAG_Z = res;
9753 FLAG_V = VFLAG_CLEAR;
9754 FLAG_C = CFLAG_CLEAR;
9755 return;
9756 }
9757 m68ki_exception_illegal();
9758 }
9761 M68KMAKE_OP(tst, 16, ., .)
9762 {
9763 uint res = M68KMAKE_GET_OPER_AY_16;
9765 FLAG_N = NFLAG_16(res);
9766 FLAG_Z = res;
9767 FLAG_V = VFLAG_CLEAR;
9768 FLAG_C = CFLAG_CLEAR;
9769 }
9772 M68KMAKE_OP(tst, 16, ., pcdi)
9773 {
9774 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9775 {
9776 uint res = OPER_PCDI_16();
9778 FLAG_N = NFLAG_16(res);
9779 FLAG_Z = res;
9780 FLAG_V = VFLAG_CLEAR;
9781 FLAG_C = CFLAG_CLEAR;
9782 return;
9783 }
9784 m68ki_exception_illegal();
9785 }
9788 M68KMAKE_OP(tst, 16, ., pcix)
9789 {
9790 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9791 {
9792 uint res = OPER_PCIX_16();
9794 FLAG_N = NFLAG_16(res);
9795 FLAG_Z = res;
9796 FLAG_V = VFLAG_CLEAR;
9797 FLAG_C = CFLAG_CLEAR;
9798 return;
9799 }
9800 m68ki_exception_illegal();
9801 }
9804 M68KMAKE_OP(tst, 16, ., i)
9805 {
9806 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9807 {
9808 uint res = OPER_I_16();
9810 FLAG_N = NFLAG_16(res);
9811 FLAG_Z = res;
9812 FLAG_V = VFLAG_CLEAR;
9813 FLAG_C = CFLAG_CLEAR;
9814 return;
9815 }
9816 m68ki_exception_illegal();
9817 }
9820 M68KMAKE_OP(tst, 32, ., d)
9821 {
9822 uint res = DY;
9824 FLAG_N = NFLAG_32(res);
9825 FLAG_Z = res;
9826 FLAG_V = VFLAG_CLEAR;
9827 FLAG_C = CFLAG_CLEAR;
9828 }
9831 M68KMAKE_OP(tst, 32, ., a)
9832 {
9833 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9834 {
9835 uint res = AY;
9837 FLAG_N = NFLAG_32(res);
9838 FLAG_Z = res;
9839 FLAG_V = VFLAG_CLEAR;
9840 FLAG_C = CFLAG_CLEAR;
9841 return;
9842 }
9843 m68ki_exception_illegal();
9844 }
9847 M68KMAKE_OP(tst, 32, ., .)
9848 {
9849 uint res = M68KMAKE_GET_OPER_AY_32;
9851 FLAG_N = NFLAG_32(res);
9852 FLAG_Z = res;
9853 FLAG_V = VFLAG_CLEAR;
9854 FLAG_C = CFLAG_CLEAR;
9855 }
9858 M68KMAKE_OP(tst, 32, ., pcdi)
9859 {
9860 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9861 {
9862 uint res = OPER_PCDI_32();
9864 FLAG_N = NFLAG_32(res);
9865 FLAG_Z = res;
9866 FLAG_V = VFLAG_CLEAR;
9867 FLAG_C = CFLAG_CLEAR;
9868 return;
9869 }
9870 m68ki_exception_illegal();
9871 }
9874 M68KMAKE_OP(tst, 32, ., pcix)
9875 {
9876 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9877 {
9878 uint res = OPER_PCIX_32();
9880 FLAG_N = NFLAG_32(res);
9881 FLAG_Z = res;
9882 FLAG_V = VFLAG_CLEAR;
9883 FLAG_C = CFLAG_CLEAR;
9884 return;
9885 }
9886 m68ki_exception_illegal();
9887 }
9890 M68KMAKE_OP(tst, 32, ., i)
9891 {
9892 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9893 {
9894 uint res = OPER_I_32();
9896 FLAG_N = NFLAG_32(res);
9897 FLAG_Z = res;
9898 FLAG_V = VFLAG_CLEAR;
9899 FLAG_C = CFLAG_CLEAR;
9900 return;
9901 }
9902 m68ki_exception_illegal();
9903 }
9906 M68KMAKE_OP(unlk, 32, ., a7)
9907 {
9908 REG_A[7] = m68ki_read_32(REG_A[7]);
9909 }
9912 M68KMAKE_OP(unlk, 32, ., .)
9913 {
9914 uint* r_dst = &AY;
9916 REG_A[7] = *r_dst;
9917 *r_dst = m68ki_pull_32();
9918 }
9921 M68KMAKE_OP(unpk, 16, rr, .)
9922 {
9923 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9924 {
9925 /* Note: DX and DY are reversed in Motorola's docs */
9926 uint src = DY;
9927 uint* r_dst = &DX;
9929 *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff);
9930 return;
9931 }
9932 m68ki_exception_illegal();
9933 }
9936 M68KMAKE_OP(unpk, 16, mm, ax7)
9937 {
9938 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9939 {
9940 /* Note: AX and AY are reversed in Motorola's docs */
9941 uint src = OPER_AY_PD_8();
9942 uint ea_dst;
9944 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
9945 ea_dst = EA_A7_PD_8();
9946 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
9947 ea_dst = EA_A7_PD_8();
9948 m68ki_write_8(ea_dst, src & 0xff);
9949 return;
9950 }
9951 m68ki_exception_illegal();
9952 }
9955 M68KMAKE_OP(unpk, 16, mm, ay7)
9956 {
9957 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9958 {
9959 /* Note: AX and AY are reversed in Motorola's docs */
9960 uint src = OPER_A7_PD_8();
9961 uint ea_dst;
9963 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
9964 ea_dst = EA_AX_PD_8();
9965 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
9966 ea_dst = EA_AX_PD_8();
9967 m68ki_write_8(ea_dst, src & 0xff);
9968 return;
9969 }
9970 m68ki_exception_illegal();
9971 }
9974 M68KMAKE_OP(unpk, 16, mm, axy7)
9975 {
9976 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9977 {
9978 uint src = OPER_A7_PD_8();
9979 uint ea_dst;
9981 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
9982 ea_dst = EA_A7_PD_8();
9983 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
9984 ea_dst = EA_A7_PD_8();
9985 m68ki_write_8(ea_dst, src & 0xff);
9986 return;
9987 }
9988 m68ki_exception_illegal();
9989 }
9992 M68KMAKE_OP(unpk, 16, mm, .)
9993 {
9994 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
9995 {
9996 /* Note: AX and AY are reversed in Motorola's docs */
9997 uint src = OPER_AY_PD_8();
9998 uint ea_dst;
10000 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
10001 ea_dst = EA_AX_PD_8();
10002 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
10003 ea_dst = EA_AX_PD_8();
10004 m68ki_write_8(ea_dst, src & 0xff);
10005 return;
10006 }
10007 m68ki_exception_illegal();
10008 }
10012 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
10013 M68KMAKE_END