Fri, 18 Apr 2014 01:34:20 -0600
added RTC emulation (attempts to set the date are ignored, and the year is currently hardcoded to 1987 because UNIX PC SysV has a few Y2K bugs)
1 #include <stdio.h>
2 #include <stdlib.h>
3 #include <stdint.h>
4 #include <stdbool.h>
5 #include <assert.h>
6 #include "musashi/m68k.h"
7 #include "state.h"
8 #include "utils.h"
9 #include "memory.h"
11 // The value which will be returned if the CPU attempts to read from empty memory
12 // TODO (FIXME?) - need to figure out if R/W ops wrap around. This seems to appease the UNIX kernel and P4TEST.
13 #define EMPTY 0xFFFFFFFFUL
14 //#define EMPTY 0x55555555UL
15 //#define EMPTY 0x00000000UL
17 /******************
18 * Memory mapping
19 ******************/
21 #define MAPRAM(addr) (((uint16_t)state.map[addr*2] << 8) + ((uint16_t)state.map[(addr*2)+1]))
23 static uint32_t map_address_debug(uint32_t addr)
24 {
25 uint16_t page = (addr >> 12) & 0x3FF;
27 // Look it up in the map RAM and get the physical page address
28 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
29 return (new_page_addr << 12) + (addr & 0xFFF);
30 }
32 uint32_t mapAddr(uint32_t addr, bool writing)/*{{{*/
33 {
34 if (addr < 0x400000) {
35 // RAM access. Check against the Map RAM
36 // Start by getting the original page address
37 uint16_t page = (addr >> 12) & 0x3FF;
39 // Look it up in the map RAM and get the physical page address
40 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
42 // Update the Page Status bits
43 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x03;
44 // Pagebits --
45 // 0 = not present
46 // 1 = present but not accessed
47 // 2 = present, accessed (read from)
48 // 3 = present, dirty (written to)
49 switch (pagebits) {
50 case 0:
51 // Page not present
52 // This should cause a page fault
53 LOGS("Whoa! Pagebit update, when the page is not present!");
54 break;
56 case 1:
57 // Page present -- first access
58 state.map[page*2] &= 0x9F; // turn off "present" bit (but not write enable!)
59 if (writing)
60 state.map[page*2] |= 0x60; // Page written to (dirty)
61 else
62 state.map[page*2] |= 0x40; // Page accessed but not written
63 break;
65 case 2:
66 case 3:
67 // Page present, 2nd or later access
68 if (writing)
69 state.map[page*2] |= 0x60; // Page written to (dirty)
70 break;
71 }
73 // Return the address with the new physical page spliced in
74 return (new_page_addr << 12) + (addr & 0xFFF);
75 } else {
76 // I/O, VRAM or MapRAM space; no mapping is performed or required
77 // TODO: assert here?
78 return addr;
79 }
80 }/*}}}*/
82 MEM_STATUS checkMemoryAccess(uint32_t addr, bool writing, bool dma)/*{{{*/
83 {
84 // Get the page bits for this page.
85 uint16_t page = (addr >> 12) & 0x3FF;
86 uint8_t pagebits = (MAPRAM(page) >> 13) & 0x07;
88 // Check page is present (but only for RAM zone)
89 if ((addr < 0x400000) && ((pagebits & 0x03) == 0)) {
90 LOG("Page not mapped in: addr %08X, page %04X, mapbits %04X", addr, page, MAPRAM(page));
91 return MEM_PAGEFAULT;
92 }
94 // Are we in Supervisor mode?
95 if (dma || (m68k_get_reg(NULL, M68K_REG_SR) & 0x2000))
96 // Yes. We can do anything we like.
97 return MEM_ALLOWED;
99 // If we're here, then we must be in User mode.
100 // Check that the user didn't access memory outside of the RAM area
101 if (addr >= 0x400000) {
102 LOGS("User accessed privileged memory");
103 return MEM_UIE;
104 }
106 // User attempt to access the kernel
107 // A19, A20, A21, A22 low (kernel access): RAM addr before paging; not in Supervisor mode
108 if (((addr >> 19) & 0x0F) == 0 && !(!writing && addr <= 0x1000)) {
109 LOGS("Attempt by user code to access kernel space");
110 return MEM_KERNEL;
111 }
113 // Check page is write enabled
114 if (writing && ((pagebits & 0x04) == 0)) {
115 LOG("Page not write enabled: inaddr %08X, page %04X, mapram %04X [%02X %02X], pagebits %d",
116 addr, page, MAPRAM(page), state.map[page*2], state.map[(page*2)+1], pagebits);
117 return MEM_PAGE_NO_WE;
118 }
119 // Page access allowed.
120 return MEM_ALLOWED;
121 }/*}}}*/
123 #define _ACCESS_CHECK_WR_BYTE(address) \
124 do { \
125 switch (st = checkMemoryAccess(address, true, false)) { \
126 case MEM_ALLOWED: \
127 /* Access allowed */ \
128 break; \
129 case MEM_PAGEFAULT: \
130 /* Page fault */ \
131 state.genstat = 0x8BFF | (state.pie ? 0x0400 : 0); \
132 fault = true; \
133 break; \
134 case MEM_UIE: \
135 /* User access to memory above 4MB */ \
136 state.genstat = 0x9AFF | (state.pie ? 0x0400 : 0); \
137 fault = true; \
138 break; \
139 case MEM_KERNEL: \
140 case MEM_PAGE_NO_WE: \
141 /* kernel access or page not write enabled */ \
142 /* XXX: is this the correct value? */ \
143 state.genstat = 0x9BFF | (state.pie ? 0x0400 : 0); \
144 fault = true; \
145 break; \
146 } \
147 }while (0)
151 /********************************************************
152 * m68k memory read/write support functions for Musashi
153 ********************************************************/
155 /**
156 * @brief Check memory access permissions for a write operation.
157 * @note This used to be a single macro (merged with ACCESS_CHECK_RD), but
158 * gcc throws warnings when you have a return-with-value in a void
159 * function, even if the return-with-value is completely unreachable.
160 * Similarly it doesn't like it if you have a return without a value
161 * in a non-void function, even if it's impossible to ever reach the
162 * return-with-no-value. UGH!
163 */
164 /*{{{ macro: ACCESS_CHECK_WR(address, bits)*/
165 #define ACCESS_CHECK_WR(address, bits) \
166 do { \
167 bool fault = false; \
168 MEM_STATUS st; \
169 _ACCESS_CHECK_WR_BYTE(address); \
170 if (!fault && bits == 32 \
171 && ((address + 3) & ~0xfff) != ((address & ~0xfff))){ \
172 _ACCESS_CHECK_WR_BYTE(address + 3); \
173 } \
174 if (fault) { \
175 if (bits >= 16) \
176 state.bsr0 = 0x7C00; \
177 else \
178 state.bsr0 = (address & 1) ? 0x7E00 : 0x7D00; \
179 state.bsr0 |= (address >> 16); \
180 state.bsr1 = address & 0xffff; \
181 LOG("Bus Error while writing, addr %08X, statcode %d", address, st); \
182 if (state.ee) m68k_pulse_bus_error(); \
183 return; \
184 } \
185 } while (0)
186 /*}}}*/
188 #define _ACCESS_CHECK_RD_BYTE(address) \
189 do { \
190 switch (st = checkMemoryAccess(address, false, false)) { \
191 case MEM_ALLOWED: \
192 /* Access allowed */ \
193 break; \
194 case MEM_PAGEFAULT: \
195 /* Page fault */ \
196 state.genstat = 0xCBFF | (state.pie ? 0x0400 : 0); \
197 fault = true; \
198 break; \
199 case MEM_UIE: \
200 /* User access to memory above 4MB */ \
201 state.genstat = 0xDAFF | (state.pie ? 0x0400 : 0); \
202 fault = true; \
203 break; \
204 case MEM_KERNEL: \
205 case MEM_PAGE_NO_WE: \
206 /* kernel access or page not write enabled */ \
207 /* XXX: is this the correct value? */ \
208 state.genstat = 0xDBFF | (state.pie ? 0x0400 : 0); \
209 fault = true; \
210 break; \
211 } \
212 } while (0)
214 /**
215 * @brief Check memory access permissions for a read operation.
216 * @note This used to be a single macro (merged with ACCESS_CHECK_WR), but
217 * gcc throws warnings when you have a return-with-value in a void
218 * function, even if the return-with-value is completely unreachable.
219 * Similarly it doesn't like it if you have a return without a value
220 * in a non-void function, even if it's impossible to ever reach the
221 * return-with-no-value. UGH!
222 */
223 /*{{{ macro: ACCESS_CHECK_RD(address, bits)*/
224 #define ACCESS_CHECK_RD(address, bits) \
225 do { \
226 bool fault = false; \
227 uint32_t faultAddr = address; \
228 MEM_STATUS st; \
229 _ACCESS_CHECK_RD_BYTE(address); \
230 if (!fault && bits == 32 \
231 && ((address + 2) & ~0xfff) != (address & ~0xfff)){ \
232 _ACCESS_CHECK_RD_BYTE(address + 2); \
233 if (fault) faultAddr = address + 2; \
234 } \
235 \
236 if (fault) { \
237 if (bits >= 16) \
238 state.bsr0 = 0x7C00; \
239 else \
240 state.bsr0 = (faultAddr & 1) ? 0x7E00 : 0x7D00; \
241 state.bsr0 |= (faultAddr >> 16); \
242 state.bsr1 = faultAddr & 0xffff; \
243 LOG("Bus Error while reading, addr %08X, statcode %d", faultAddr, st); \
244 if (state.ee) m68k_pulse_bus_error(); \
245 if (bits >= 32) \
246 return EMPTY & 0xFFFFFFFF; \
247 else \
248 return EMPTY & ((1ULL << bits)-1); \
249 } \
250 } while (0)
251 /*}}}*/
253 bool access_check_dma(int reading)
254 {
255 // Check memory access permissions
256 bool access_ok = false;
257 switch (checkMemoryAccess(state.dma_address, !reading, true)) {
258 case MEM_PAGEFAULT:
259 // Page fault
260 state.genstat = 0xABFF
261 | (reading ? 0x4000 : 0)
262 | (state.pie ? 0x0400 : 0);
263 access_ok = false;
264 break;
266 case MEM_UIE:
267 // User access to memory above 4MB
268 // FIXME? Shouldn't be possible with DMA... assert this?
269 state.genstat = 0xBAFF
270 | (reading ? 0x4000 : 0)
271 | (state.pie ? 0x0400 : 0);
272 access_ok = false;
273 break;
275 case MEM_KERNEL:
276 case MEM_PAGE_NO_WE:
277 // Kernel access or page not write enabled
278 /* XXX: is this correct? */
279 state.genstat = 0xBBFF
280 | (reading ? 0x4000 : 0)
281 | (state.pie ? 0x0400 : 0);
282 access_ok = false;
283 break;
285 case MEM_ALLOWED:
286 access_ok = true;
287 break;
288 }
289 if (!access_ok) {
290 state.bsr0 = 0x3C00;
291 state.bsr0 |= (state.dma_address >> 16);
292 state.bsr1 = state.dma_address & 0xffff;
293 if (state.ee) m68k_set_irq(7);
294 printf("BUS ERROR FROM DMA: genstat=%04X, bsr0=%04X, bsr1=%04X\n", state.genstat, state.bsr0, state.bsr1);
295 }
296 return (access_ok);
297 }
299 // Logging macros
300 #define LOG_NOT_HANDLED_R(bits) \
301 if (!handled) printf("unhandled read%02d, addr=0x%08X\n", bits, address);
303 #define LOG_NOT_HANDLED_W(bits) \
304 if (!handled) printf("unhandled write%02d, addr=0x%08X, data=0x%08X\n", bits, address, data);
306 /********************************************************
307 * I/O read/write functions
308 ********************************************************/
310 /**
311 * Issue a warning if a read operation is made with an invalid size
312 */
313 inline static void ENFORCE_SIZE(int bits, uint32_t address, bool read, int allowed, char *regname)
314 {
315 assert((bits == 8) || (bits == 16) || (bits == 32));
316 if ((bits & allowed) == 0) {
317 printf("WARNING: %s 0x%08X (%s) with invalid size %d!\n", read ? "read from" : "write to", address, regname, bits);
318 }
319 }
321 inline static void ENFORCE_SIZE_R(int bits, uint32_t address, int allowed, char *regname)
322 {
323 ENFORCE_SIZE(bits, address, true, allowed, regname);
324 }
326 inline static void ENFORCE_SIZE_W(int bits, uint32_t address, int allowed, char *regname)
327 {
328 ENFORCE_SIZE(bits, address, false, allowed, regname);
329 }
331 void IoWrite(uint32_t address, uint32_t data, int bits)/*{{{*/
332 {
333 bool handled = false;
335 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
336 // I/O register space, zone A
337 switch (address & 0x0F0000) {
338 case 0x010000: // General Status Register
339 if (bits == 16)
340 state.genstat = (data & 0xffff);
341 else if (bits == 8) {
342 if (address & 0)
343 state.genstat = data;
344 else
345 state.genstat = data << 8;
346 }
347 handled = true;
348 break;
349 case 0x030000: // Bus Status Register 0
350 break;
351 case 0x040000: // Bus Status Register 1
352 break;
353 case 0x050000: // Phone status
354 break;
355 case 0x060000: // DMA Count
356 ENFORCE_SIZE_W(bits, address, 16, "DMACOUNT");
357 state.dma_count = (data & 0x3FFF);
358 state.idmarw = ((data & 0x4000) == 0x4000);
359 state.dmaen = ((data & 0x8000) == 0x8000);
360 // This handles the "dummy DMA transfer" mentioned in the docs
361 // disabled because it causes the floppy test to fail
362 #if 0
363 if (!state.idmarw){
364 if (access_check_dma(true)){
365 uint32_t newAddr = mapAddr(state.dma_address, true);
366 // RAM access
367 if (newAddr <= 0x1fffff)
368 WR16(state.base_ram, newAddr, state.base_ram_size - 1, 0xFF);
369 else if (address <= 0x3FFFFF)
370 WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, 0xFF);
371 }
372 }
373 #endif
374 state.dma_count++;
375 handled = true;
376 break;
377 case 0x070000: // Line Printer Status Register
378 break;
379 case 0x080000: // Real Time Clock
380 ENFORCE_SIZE_W(bits, address, 16, "RTCWRITE");
381 /*printf("IoWrite RTCWRITE %x\n", data);*/
382 tc8250_set_chip_enable(&state.rtc_ctx, data & 0x8000);
383 tc8250_set_address_latch_enable(&state.rtc_ctx, data & 0x4000);
384 tc8250_set_write_enable(&state.rtc_ctx, data & 0x2000);
385 tc8250_write_reg(&state.rtc_ctx, (data & 0x0F00) >> 8);
386 handled = true;
387 break;
388 case 0x090000: // Phone registers
389 switch (address & 0x0FF000) {
390 case 0x090000: // Handset relay
391 case 0x098000:
392 break;
393 case 0x091000: // Line select 2
394 case 0x099000:
395 break;
396 case 0x092000: // Hook relay 1
397 case 0x09A000:
398 break;
399 case 0x093000: // Hook relay 2
400 case 0x09B000:
401 break;
402 case 0x094000: // Line 1 hold
403 case 0x09C000:
404 break;
405 case 0x095000: // Line 2 hold
406 case 0x09D000:
407 break;
408 case 0x096000: // Line 1 A-lead
409 case 0x09E000:
410 break;
411 case 0x097000: // Line 2 A-lead
412 case 0x09F000:
413 break;
414 }
415 break;
416 case 0x0A0000: // Miscellaneous Control Register
417 ENFORCE_SIZE_W(bits, address, 16, "MISCCON");
418 // TODO: handle the ctrl bits properly
419 if (data & 0x8000){
420 state.timer_enabled = 1;
421 }else{
422 state.timer_enabled = 0;
423 state.timer_asserted = 0;
424 }
425 state.dma_reading = (data & 0x4000);
426 if (state.leds != ((~data & 0xF00) >> 8)) {
427 state.leds = (~data & 0xF00) >> 8;
428 #ifdef SHOW_LEDS
429 printf("LEDs: %s %s %s %s\n",
430 (state.leds & 8) ? "R" : "-",
431 (state.leds & 4) ? "G" : "-",
432 (state.leds & 2) ? "Y" : "-",
433 (state.leds & 1) ? "R" : "-");
434 #endif
435 }
436 handled = true;
437 break;
438 case 0x0B0000: // TM/DIALWR
439 break;
440 case 0x0C0000: // Clear Status Register
441 state.genstat = 0xFFFF;
442 state.bsr0 = 0xFFFF;
443 state.bsr1 = 0xFFFF;
444 handled = true;
445 break;
446 case 0x0D0000: // DMA Address Register
447 if (address & 0x004000) {
448 // A14 high -- set most significant bits
449 state.dma_address = (state.dma_address & 0x1fe) | ((address & 0x3ffe) << 8);
450 } else {
451 // A14 low -- set least significant bits
452 state.dma_address = (state.dma_address & 0x3ffe00) | (address & 0x1fe);
453 }
454 handled = true;
455 break;
456 case 0x0E0000: // Disk Control Register
457 {
458 bool fd_selected;
459 bool hd_selected;
460 ENFORCE_SIZE_W(bits, address, 16, "DISKCON");
461 // B7 = FDD controller reset
462 if ((data & 0x80) == 0) wd2797_reset(&state.fdc_ctx);
463 // B6 = drive 0 select
464 fd_selected = (data & 0x40) != 0;
465 // B5 = motor enable -- TODO
466 // B4 = HDD controller reset
467 if ((data & 0x10) == 0) wd2010_reset(&state.hdc_ctx);
468 // B3 = HDD0 select
469 hd_selected = (data & 0x08) != 0;
470 // B2,1,0 = HDD0 head select -- TODO?
471 if (hd_selected && !state.hd_selected){
472 state.fd_selected = false;
473 state.hd_selected = true;
474 }else if (fd_selected && !state.fd_selected){
475 state.hd_selected = false;
476 state.fd_selected = true;
477 }
478 handled = true;
479 break;
480 }
481 case 0x0F0000: // Line Printer Data Register
482 break;
483 }
484 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
485 // I/O register space, zone B
486 switch (address & 0xF00000) {
487 case 0xC00000: // Expansion slots
488 case 0xD00000:
489 switch (address & 0xFC0000) {
490 case 0xC00000: // Expansion slot 0
491 case 0xC40000: // Expansion slot 1
492 case 0xC80000: // Expansion slot 2
493 case 0xCC0000: // Expansion slot 3
494 case 0xD00000: // Expansion slot 4
495 case 0xD40000: // Expansion slot 5
496 case 0xD80000: // Expansion slot 6
497 case 0xDC0000: // Expansion slot 7
498 fprintf(stderr, "NOTE: WR%d to expansion card space, addr=0x%08X, data=0x%08X\n", bits, address, data);
499 handled = true;
500 break;
501 }
502 break;
503 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
504 case 0xF00000:
505 switch (address & 0x070000) {
506 case 0x000000: // [ef][08]xxxx ==> WD2010 hard disc controller
507 wd2010_write_reg(&state.hdc_ctx, (address >> 1) & 7, data);
508 handled = true;
509 break;
510 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
511 /*ENFORCE_SIZE_W(bits, address, 16, "FDC REGISTERS");*/
512 wd2797_write_reg(&state.fdc_ctx, (address >> 1) & 3, data);
513 handled = true;
514 break;
515 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
516 // MCR2 - UNIX PC Rev. P5.1 HDD head select b3 and potential HDD#2 select
517 wd2010_write_reg(&state.hdc_ctx, UNIXPC_REG_MCR2, data);
518 handled = true;
519 break;
520 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
521 break;
522 case 0x040000: // [ef][4c]xxxx ==> General Control Register
523 switch (address & 0x077000) {
524 case 0x040000: // [ef][4c][08]xxx ==> EE
525 // Error Enable. If =0, Level7 intrs and bus errors are masked.
526 ENFORCE_SIZE_W(bits, address, 16, "EE");
527 state.ee = ((data & 0x8000) == 0x8000);
528 handled = true;
529 break;
530 case 0x041000: // [ef][4c][19]xxx ==> PIE
531 ENFORCE_SIZE_W(bits, address, 16, "PIE");
532 state.pie = ((data & 0x8000) == 0x8000);
533 handled = true;
534 break;
535 case 0x042000: // [ef][4c][2A]xxx ==> BP
536 break;
537 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
538 ENFORCE_SIZE_W(bits, address, 16, "ROMLMAP");
539 state.romlmap = ((data & 0x8000) == 0x8000);
540 handled = true;
541 break;
542 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
543 ENFORCE_SIZE_W(bits, address, 16, "L1 MODEM");
544 break;
545 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
546 ENFORCE_SIZE_W(bits, address, 16, "L2 MODEM");
547 break;
548 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
549 ENFORCE_SIZE_W(bits, address, 16, "D/N CONNECT");
550 break;
551 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video
552 ENFORCE_SIZE_W(bits, address, 16, "WHOLE SCREEN REVERSE VIDEO");
553 break;
554 }
555 case 0x050000: // [ef][5d]xxxx ==> 8274
556 break;
557 case 0x060000: // [ef][6e]xxxx ==> Control regs
558 switch (address & 0x07F000) {
559 default:
560 break;
561 }
562 break;
563 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
564 // TODO: figure out which sizes are valid (probably just 8 and 16)
565 // ENFORCE_SIZE_W(bits, address, 16, "KEYBOARD CONTROLLER");
566 if (bits == 8) {
567 printf("KBD WR %02X => %02X\n", (address >> 1) & 3, data);
568 keyboard_write(&state.kbd, (address >> 1) & 3, data);
569 handled = true;
570 } else if (bits == 16) {
571 printf("KBD WR %02X => %04X\n", (address >> 1) & 3, data);
572 keyboard_write(&state.kbd, (address >> 1) & 3, data >> 8);
573 handled = true;
574 }
575 break;
576 }
577 }
578 }
580 LOG_NOT_HANDLED_W(bits);
581 }/*}}}*/
583 uint32_t IoRead(uint32_t address, int bits)/*{{{*/
584 {
585 bool handled = false;
586 uint32_t data = EMPTY & 0xFFFFFFFF;
588 if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
589 // I/O register space, zone A
590 switch (address & 0x0F0000) {
591 case 0x010000: // General Status Register
592 /* ENFORCE_SIZE_R(bits, address, 16, "GENSTAT"); */
593 if (bits == 32) {
594 return ((uint32_t)state.genstat << 16) + (uint32_t)state.genstat;
595 } else if (bits == 16) {
596 return (uint16_t)state.genstat;
597 } else {
598 return (uint8_t)(state.genstat & 0xff);
599 }
600 break;
601 case 0x030000: // Bus Status Register 0
602 ENFORCE_SIZE_R(bits, address, 16, "BSR0");
603 return ((uint32_t)state.bsr0 << 16) + (uint32_t)state.bsr0;
604 break;
605 case 0x040000: // Bus Status Register 1
606 ENFORCE_SIZE_R(bits, address, 16, "BSR1");
607 return ((uint32_t)state.bsr1 << 16) + (uint32_t)state.bsr1;
608 break;
609 case 0x050000: // Phone status
610 ENFORCE_SIZE_R(bits, address, 8 | 16, "PHONE STATUS");
611 break;
612 case 0x060000: // DMA Count
613 // TODO: U/OERR- is always inactive (bit set)... or should it be = DMAEN+?
614 // Bit 14 is always unused, so leave it set
615 ENFORCE_SIZE_R(bits, address, 16, "DMACOUNT");
616 return (state.dma_count & 0x3fff) | 0xC000;
617 break;
618 case 0x070000: // Line Printer Status Register
619 data = 0x00120012; // no parity error, no line printer error, no irqs from FDD or HDD
620 data |= wd2797_get_irq(&state.fdc_ctx) ? 0x00080008 : 0;
621 data |= wd2010_get_irq(&state.hdc_ctx) ? 0x00040004 : 0;
622 return data;
623 break;
624 case 0x080000: // Real Time Clock
625 printf("READ NOTIMP: Realtime Clock\n");
626 break;
627 case 0x090000: // Phone registers
628 switch (address & 0x0FF000) {
629 case 0x090000: // Handset relay
630 case 0x098000:
631 break;
632 case 0x091000: // Line select 2
633 case 0x099000:
634 break;
635 case 0x092000: // Hook relay 1
636 case 0x09A000:
637 break;
638 case 0x093000: // Hook relay 2
639 case 0x09B000:
640 break;
641 case 0x094000: // Line 1 hold
642 case 0x09C000:
643 break;
644 case 0x095000: // Line 2 hold
645 case 0x09D000:
646 break;
647 case 0x096000: // Line 1 A-lead
648 case 0x09E000:
649 break;
650 case 0x097000: // Line 2 A-lead
651 case 0x09F000:
652 break;
653 }
654 break;
655 case 0x0A0000: // Miscellaneous Control Register -- write only!
656 handled = true;
657 break;
658 case 0x0B0000: // TM/DIALWR
659 break;
660 case 0x0C0000: // Clear Status Register -- write only!
661 handled = true;
662 break;
663 case 0x0D0000: // DMA Address Register
664 break;
665 case 0x0E0000: // Disk Control Register
666 break;
667 case 0x0F0000: // Line Printer Data Register
668 break;
669 }
670 } else if ((address >= 0xC00000) && (address <= 0xFFFFFF)) {
671 // I/O register space, zone B
672 switch (address & 0xF00000) {
673 case 0xC00000: // Expansion slots
674 case 0xD00000:
675 switch (address & 0xFC0000) {
676 case 0xC00000: // Expansion slot 0
677 case 0xC40000: // Expansion slot 1
678 case 0xC80000: // Expansion slot 2
679 case 0xCC0000: // Expansion slot 3
680 case 0xD00000: // Expansion slot 4
681 case 0xD40000: // Expansion slot 5
682 case 0xD80000: // Expansion slot 6
683 case 0xDC0000: // Expansion slot 7
684 fprintf(stderr, "NOTE: RD%d from expansion card space, addr=0x%08X\n", bits, address);
685 handled = true;
686 break;
687 }
688 break;
689 case 0xE00000: // HDC, FDC, MCR2 and RTC data bits
690 case 0xF00000:
691 switch (address & 0x070000) {
692 case 0x000000: // [ef][08]xxxx ==> WD1010 hard disc controller
693 return (wd2010_read_reg(&state.hdc_ctx, (address >> 1) & 7));
695 break;
696 case 0x010000: // [ef][19]xxxx ==> WD2797 floppy disc controller
697 /*ENFORCE_SIZE_R(bits, address, 16, "FDC REGISTERS");*/
698 return wd2797_read_reg(&state.fdc_ctx, (address >> 1) & 3);
699 break;
700 case 0x020000: // [ef][2a]xxxx ==> Miscellaneous Control Register 2
701 break;
702 case 0x030000: // [ef][3b]xxxx ==> Real Time Clock data bits
703 return (tc8250_read_reg(&state.rtc_ctx));
704 case 0x040000: // [ef][4c]xxxx ==> General Control Register
705 switch (address & 0x077000) {
706 case 0x040000: // [ef][4c][08]xxx ==> EE
707 case 0x041000: // [ef][4c][19]xxx ==> PIE
708 case 0x042000: // [ef][4c][2A]xxx ==> BP
709 case 0x043000: // [ef][4c][3B]xxx ==> ROMLMAP
710 case 0x044000: // [ef][4c][4C]xxx ==> L1 MODEM
711 case 0x045000: // [ef][4c][5D]xxx ==> L2 MODEM
712 case 0x046000: // [ef][4c][6E]xxx ==> D/N CONNECT
713 // All write-only registers... TODO: bus error?
714 handled = true;
715 break;
716 case 0x047000: // [ef][4c][7F]xxx ==> Whole screen reverse video [FIXME: not in TRM]
717 break;
718 }
719 break;
720 case 0x050000: // [ef][5d]xxxx ==> 8274
721 break;
722 case 0x060000: // [ef][6e]xxxx ==> Control regs
723 switch (address & 0x07F000) {
724 default:
725 break;
726 }
727 break;
728 case 0x070000: // [ef][7f]xxxx ==> 6850 Keyboard Controller
729 // TODO: figure out which sizes are valid (probably just 8 and 16)
730 //ENFORCE_SIZE_R(bits, address, 16, "KEYBOARD CONTROLLER");
731 {
732 if (bits == 8) {
733 return keyboard_read(&state.kbd, (address >> 1) & 3);
734 } else {
735 return keyboard_read(&state.kbd, (address >> 1) & 3) << 8;
736 }
737 return data;
738 }
739 break;
740 }
741 }
742 }
744 LOG_NOT_HANDLED_R(bits);
746 return data;
747 }/*}}}*/
750 /********************************************************
751 * m68k memory read/write support functions for Musashi
752 ********************************************************/
755 static uint16_t ram_read_16(uint32_t address)
756 {
757 if (address <= 0x1fffff) {
758 // Base memory wraps around
759 return RD16(state.base_ram, address, state.base_ram_size - 1);
760 } else {
761 if ((address <= (state.exp_ram_size + 0x200000 - 1)) && (address >= 0x200000)){
762 return RD16(state.exp_ram, address - 0x200000, state.exp_ram_size - 1);
763 }else
764 return EMPTY & 0xffff;
765 }
766 }
768 /**
769 * @brief Read M68K memory, 32-bit
770 */
771 uint32_t m68k_read_memory_32(uint32_t address)/*{{{*/
772 {
773 uint32_t data = EMPTY & 0xFFFFFFFF;
775 // If ROMLMAP is set, force system to access ROM
776 if (!state.romlmap)
777 address |= 0x800000;
779 // Check access permissions
780 ACCESS_CHECK_RD(address, 32);
782 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
783 // ROM access
784 return RD32(state.rom, address, ROM_SIZE - 1);
785 } else if (address <= 0x3fffff) {
786 // RAM access
787 uint32_t newAddr = mapAddr(address, false);
788 // Base memory wraps around
789 data = ((ram_read_16(newAddr) << 16) |
790 ram_read_16(mapAddr(address + 2, false)));
792 return (data);
793 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
794 // I/O register space, zone A
795 switch (address & 0x0F0000) {
796 case 0x000000: // Map RAM access
797 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD32 from MapRAM mirror, addr=0x%08X\n", address);
798 return RD32(state.map, address, 0x7FF);
799 break;
800 case 0x020000: // Video RAM
801 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD32 from VideoRAM mirror, addr=0x%08X\n", address);
802 return RD32(state.vram, address, 0x7FFF);
803 break;
804 default:
805 return IoRead(address, 32);
806 }
807 } else {
808 return IoRead(address, 32);
809 }
811 return data;
812 }/*}}}*/
814 /**
815 * @brief Read M68K memory, 16-bit
816 */
817 uint32_t m68k_read_memory_16(uint32_t address)/*{{{*/
818 {
819 uint16_t data = EMPTY & 0xFFFF;
821 // If ROMLMAP is set, force system to access ROM
822 if (!state.romlmap)
823 address |= 0x800000;
825 // Check access permissions
826 ACCESS_CHECK_RD(address, 16);
828 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
829 // ROM access
830 data = RD16(state.rom, address, ROM_SIZE - 1);
831 } else if (address <= 0x3fffff) {
832 // RAM access
833 uint32_t newAddr = mapAddr(address, false);
834 if (newAddr <= 0x1fffff) {
835 // Base memory wraps around
836 return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
837 } else {
838 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
839 return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
840 else
841 return EMPTY & 0xffff;
842 }
843 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
844 // I/O register space, zone A
845 switch (address & 0x0F0000) {
846 case 0x000000: // Map RAM access
847 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD16 from MapRAM mirror, addr=0x%08X\n", address);
848 data = RD16(state.map, address, 0x7FF);
849 break;
850 case 0x020000: // Video RAM
851 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD16 from VideoRAM mirror, addr=0x%08X\n", address);
852 data = RD16(state.vram, address, 0x7FFF);
853 break;
854 default:
855 data = IoRead(address, 16);
856 }
857 } else {
858 data = IoRead(address, 16);
859 }
861 return data;
862 }/*}}}*/
864 /**
865 * @brief Read M68K memory, 8-bit
866 */
867 uint32_t m68k_read_memory_8(uint32_t address)/*{{{*/
868 {
869 uint8_t data = EMPTY & 0xFF;
871 // If ROMLMAP is set, force system to access ROM
872 if (!state.romlmap)
873 address |= 0x800000;
875 // Check access permissions
876 ACCESS_CHECK_RD(address, 8);
878 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
879 // ROM access
880 data = RD8(state.rom, address, ROM_SIZE - 1);
881 } else if (address <= 0x3fffff) {
882 // RAM access
883 uint32_t newAddr = mapAddr(address, false);
884 if (newAddr <= 0x1fffff) {
885 // Base memory wraps around
886 return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
887 } else {
888 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
889 return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
890 else
891 return EMPTY & 0xff;
892 }
893 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
894 // I/O register space, zone A
895 switch (address & 0x0F0000) {
896 case 0x000000: // Map RAM access
897 if (address > 0x4007FF) fprintf(stderr, "NOTE: RD8 from MapRAM mirror, addr=0x%08X\n", address);
898 data = RD8(state.map, address, 0x7FF);
899 break;
900 case 0x020000: // Video RAM
901 if (address > 0x427FFF) fprintf(stderr, "NOTE: RD8 from VideoRAM mirror, addr=0x%08X\n", address);
902 data = RD8(state.vram, address, 0x7FFF);
903 break;
904 default:
905 data = IoRead(address, 8);
906 }
907 } else {
908 data = IoRead(address, 8);
909 }
911 return data;
912 }/*}}}*/
915 static void ram_write_16(uint32_t address, uint32_t value)/*{{{*/
916 {
917 if (address <= 0x1fffff) {
918 if (address < state.base_ram_size) {
919 WR16(state.base_ram, address, state.base_ram_size - 1, value);
920 }
921 } else {
922 if ((address - 0x200000) < state.exp_ram_size) {
923 WR16(state.exp_ram, address - 0x200000, state.exp_ram_size - 1, value);
924 }
925 }
926 }
928 /**
929 * @brief Write M68K memory, 32-bit
930 */
931 void m68k_write_memory_32(uint32_t address, uint32_t value)/*{{{*/
932 {
933 // If ROMLMAP is set, force system to access ROM
934 if (!state.romlmap)
935 address |= 0x800000;
937 // Check access permissions
938 ACCESS_CHECK_WR(address, 32);
939 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
940 // ROM access
941 } else if (address <= 0x3FFFFF) {
942 // RAM access
943 uint32_t newAddr = mapAddr(address, true);
944 ram_write_16(newAddr, (value & 0xffff0000) >> 16);
945 ram_write_16(mapAddr(address + 2, true), (value & 0xffff));
946 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
947 // I/O register space, zone A
948 switch (address & 0x0F0000) {
949 case 0x000000: // Map RAM access
950 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR32 to MapRAM mirror, addr=0x%08X\n", address);
951 WR32(state.map, address, 0x7FF, value);
952 break;
953 case 0x020000: // Video RAM
954 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR32 to VideoRAM mirror, addr=0x%08X\n", address);
955 WR32(state.vram, address, 0x7FFF, value);
956 break;
957 default:
958 IoWrite(address, value, 32);
959 }
960 } else {
961 IoWrite(address, value, 32);
962 }
963 }/*}}}*/
965 /**
966 * @brief Write M68K memory, 16-bit
967 */
968 void m68k_write_memory_16(uint32_t address, uint32_t value)/*{{{*/
969 {
970 // If ROMLMAP is set, force system to access ROM
971 if (!state.romlmap)
972 address |= 0x800000;
974 // Check access permissions
975 ACCESS_CHECK_WR(address, 16);
977 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
978 // ROM access
979 } else if (address <= 0x3FFFFF) {
980 // RAM access
981 uint32_t newAddr = mapAddr(address, true);
983 if (newAddr <= 0x1fffff) {
984 if (newAddr < state.base_ram_size) {
985 WR16(state.base_ram, newAddr, state.base_ram_size - 1, value);
986 }
987 } else {
988 if ((newAddr - 0x200000) < state.exp_ram_size) {
989 WR16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
990 }
991 }
992 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
993 // I/O register space, zone A
994 switch (address & 0x0F0000) {
995 case 0x000000: // Map RAM access
996 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR16 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
997 WR16(state.map, address, 0x7FF, value);
998 break;
999 case 0x020000: // Video RAM
1000 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR16 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
1001 WR16(state.vram, address, 0x7FFF, value);
1002 break;
1003 default:
1004 IoWrite(address, value, 16);
1005 }
1006 } else {
1007 IoWrite(address, value, 16);
1008 }
1009 }/*}}}*/
1011 /**
1012 * @brief Write M68K memory, 8-bit
1013 */
1014 void m68k_write_memory_8(uint32_t address, uint32_t value)/*{{{*/
1015 {
1016 // If ROMLMAP is set, force system to access ROM
1017 if (!state.romlmap)
1018 address |= 0x800000;
1020 // Check access permissions
1021 ACCESS_CHECK_WR(address, 8);
1023 if ((address >= 0x800000) && (address <= 0xBFFFFF)) {
1024 // ROM access (read only!)
1025 } else if (address <= 0x3FFFFF) {
1026 // RAM access
1027 uint32_t newAddr = mapAddr(address, true);
1028 if (newAddr <= 0x1fffff) {
1029 if (newAddr < state.base_ram_size) {
1030 WR8(state.base_ram, newAddr, state.base_ram_size - 1, value);
1031 }
1032 } else {
1033 if ((newAddr - 0x200000) < state.exp_ram_size) {
1034 WR8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1, value);
1035 }
1036 }
1037 } else if ((address >= 0x400000) && (address <= 0x7FFFFF)) {
1038 // I/O register space, zone A
1039 switch (address & 0x0F0000) {
1040 case 0x000000: // Map RAM access
1041 if (address > 0x4007FF) fprintf(stderr, "NOTE: WR8 to MapRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
1042 WR8(state.map, address, 0x7FF, value);
1043 break;
1044 case 0x020000: // Video RAM
1045 if (address > 0x427FFF) fprintf(stderr, "NOTE: WR8 to VideoRAM mirror, addr=0x%08X, data=0x%04X\n", address, value);
1046 WR8(state.vram, address, 0x7FFF, value);
1047 break;
1048 default:
1049 IoWrite(address, value, 8);
1050 }
1051 } else {
1052 IoWrite(address, value, 8);
1053 }
1054 }/*}}}*/
1057 // for the disassembler
1058 uint32_t m68k_read_disassembler_32(uint32_t addr)
1059 {
1060 if (addr < 0x400000) {
1061 uint32_t newAddrHigh, newAddrLow;
1062 newAddrHigh = map_address_debug(addr);
1063 newAddrLow = map_address_debug(addr + 2);
1064 return ((ram_read_16(newAddrHigh) << 16) |
1065 ram_read_16(newAddrLow));
1067 } else {
1068 printf(">>> WARNING Disassembler RD32 out of range 0x%08X\n", addr);
1069 return EMPTY;
1070 }
1071 }
1073 uint32_t m68k_read_disassembler_16(uint32_t addr)
1074 {
1075 if (addr < 0x400000) {
1076 uint16_t page = (addr >> 12) & 0x3FF;
1077 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
1078 uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
1079 if (newAddr <= 0x1fffff) {
1080 if (newAddr >= state.base_ram_size)
1081 return EMPTY & 0xffff;
1082 else
1083 return RD16(state.base_ram, newAddr, state.base_ram_size - 1);
1084 } else {
1085 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
1086 return RD16(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
1087 else
1088 return EMPTY & 0xffff;
1089 }
1090 } else {
1091 printf(">>> WARNING Disassembler RD16 out of range 0x%08X\n", addr);
1092 return EMPTY & 0xffff;
1093 }
1094 }
1096 uint32_t m68k_read_disassembler_8 (uint32_t addr)
1097 {
1098 if (addr < 0x400000) {
1099 uint16_t page = (addr >> 12) & 0x3FF;
1100 uint32_t new_page_addr = MAPRAM(page) & 0x3FF;
1101 uint32_t newAddr = (new_page_addr << 12) + (addr & 0xFFF);
1102 if (newAddr <= 0x1fffff) {
1103 if (newAddr >= state.base_ram_size)
1104 return EMPTY & 0xff;
1105 else
1106 return RD8(state.base_ram, newAddr, state.base_ram_size - 1);
1107 } else {
1108 if ((newAddr <= (state.exp_ram_size + 0x200000 - 1)) && (newAddr >= 0x200000))
1109 return RD8(state.exp_ram, newAddr - 0x200000, state.exp_ram_size - 1);
1110 else
1111 return EMPTY & 0xff;
1112 }
1113 } else {
1114 printf(">>> WARNING Disassembler RD8 out of range 0x%08X\n", addr);
1115 return EMPTY & 0xff;
1116 }
1117 }