Tue, 15 Nov 2011 10:12:37 +0000
[musashi] Fix handling of bus errors
Patch-Author: Andrew Warkentin <andreww591!gmail>
Patch-MessageID: <4EC200CE.2020304@gmail.com>
I have fixed the first page fault test failure in FreeBee (the page fault test now hangs rather than errors out, because it is trying to read from the hard drive to test DMA page faults).
There were actually two bugs (the first bug was masking the second one).
First, the ancient version of Musashi that you used is unable to properly resume from bus errors that happen in the middle of certain instructions (some instructions are fetched in stages, with the PC being advanced to each part of the instruction, so basically what happens is the CPU core attempts to read the memory location referenced by the first operand, the bus error occurs, causing the PC to jump to the exception vector, but the faulting instruction is still in the middle of being fetched, so the PC is then advanced past the beginning of the exception handler). I fixed this by delaying the jump to the bus error vector until after the faulting instruction finishes.
The second bug is simpler - you had the UDS and LDS bits in BSR0 inverted (they are supposed to be active low).
src/musashi/m68kcpu.c | file | annotate | diff | revisions | |
src/musashi/m68kcpu.h | file | annotate | diff | revisions |
1.1 --- a/src/musashi/m68kcpu.c Tue Nov 15 09:30:57 2011 +0000 1.2 +++ b/src/musashi/m68kcpu.c Tue Nov 15 10:12:37 2011 +0000 1.3 @@ -641,6 +641,10 @@ 1.4 /* Main loop. Keep going until we run out of clock cycles */ 1.5 do 1.6 { 1.7 + if (BUS_ERROR_OCCURRED){ 1.8 + m68ki_jump_bus_error_vector(); 1.9 + BUS_ERROR_OCCURRED = 0; 1.10 + } 1.11 /* Set tracing accodring to T1. (T0 is done inside instruction) */ 1.12 m68ki_trace_t1(); /* auto-disable (see m68kcpu.h) */ 1.13
2.1 --- a/src/musashi/m68kcpu.h Tue Nov 15 09:30:57 2011 +0000 2.2 +++ b/src/musashi/m68kcpu.h Tue Nov 15 10:12:37 2011 +0000 2.3 @@ -322,6 +322,8 @@ 2.4 #define CPU_ADDRESS_MASK m68ki_cpu.address_mask 2.5 #define CPU_SR_MASK m68ki_cpu.sr_mask 2.6 2.7 +#define BUS_ERROR_OCCURRED m68ki_cpu.bus_error_occurred 2.8 + 2.9 #define CYC_INSTRUCTION m68ki_cpu.cyc_instruction 2.10 #define CYC_EXCEPTION m68ki_cpu.cyc_exception 2.11 #define CYC_BCC_NOTAKE_B m68ki_cpu.cyc_bcc_notake_b 2.12 @@ -776,6 +778,8 @@ 2.13 uint address_mask; /* Available address pins */ 2.14 uint sr_mask; /* Implemented status register bits */ 2.15 2.16 + uint bus_error_occurred; 2.17 + 2.18 /* Clocks required for instructions / exceptions */ 2.19 uint cyc_bcc_notake_b; 2.20 uint cyc_bcc_notake_w; 2.21 @@ -1688,14 +1692,17 @@ 2.22 /* Exception for bus error */ 2.23 INLINE void m68ki_exception_bus_error(void) 2.24 { 2.25 - uint sr = m68ki_init_exception(); 2.26 - m68ki_stack_frame_0000(REG_PC, sr, EXCEPTION_BUS_ERROR); 2.27 - m68ki_jump_vector(EXCEPTION_BUS_ERROR); 2.28 - 2.29 + BUS_ERROR_OCCURRED = 1; 2.30 /* Use up some clock cycles and undo the instruction's cycles */ 2.31 USE_CYCLES(CYC_EXCEPTION[EXCEPTION_BUS_ERROR] - CYC_INSTRUCTION[REG_IR]); 2.32 } 2.33 2.34 +INLINE void m68ki_jump_bus_error_vector(void) 2.35 +{ 2.36 + uint sr = m68ki_init_exception(); 2.37 + m68ki_stack_frame_0000(REG_PPC, sr, EXCEPTION_BUS_ERROR); 2.38 + m68ki_jump_vector(EXCEPTION_BUS_ERROR); 2.39 +} 2.40 2.41 /* Exception for A-Line instructions */ 2.42 INLINE void m68ki_exception_1010(void)