Fri, 04 Mar 2011 00:44:36 +0000
more verbose bus error logging
| src/memory.c | file | annotate | diff | revisions |
1.1 --- a/src/memory.c Fri Mar 04 00:44:06 2011 +0000 1.2 +++ b/src/memory.c Fri Mar 04 00:44:36 2011 +0000 1.3 @@ -117,8 +117,8 @@ 1.4 #define ACCESS_CHECK_WR(address, bits) \ 1.5 do { \ 1.6 bool fault = false; \ 1.7 - /* MEM_STATUS st; */ \ 1.8 - switch (checkMemoryAccess(address, true)) { \ 1.9 + MEM_STATUS st; \ 1.10 + switch (st = checkMemoryAccess(address, true)) { \ 1.11 case MEM_ALLOWED: \ 1.12 /* Access allowed */ \ 1.13 break; \ 1.14 @@ -147,8 +147,8 @@ 1.15 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \ 1.16 state.bsr0 |= (address >> 16); \ 1.17 state.bsr1 = address & 0xffff; \ 1.18 - printf("ERR: BusError WR\n"); \ 1.19 - m68k_pulse_bus_error(); \ 1.20 + LOG("Bus Error while writing, addr %08X, statcode %d", address, st); \ 1.21 + if (state.ee) m68k_pulse_bus_error(); \ 1.22 return; \ 1.23 } \ 1.24 } while (0) 1.25 @@ -167,8 +167,8 @@ 1.26 #define ACCESS_CHECK_RD(address, bits) \ 1.27 do { \ 1.28 bool fault = false; \ 1.29 - /* MEM_STATUS st; */ \ 1.30 - switch (checkMemoryAccess(address, false)) { \ 1.31 + MEM_STATUS st; \ 1.32 + switch (st = checkMemoryAccess(address, false)) { \ 1.33 case MEM_ALLOWED: \ 1.34 /* Access allowed */ \ 1.35 break; \ 1.36 @@ -197,8 +197,8 @@ 1.37 state.bsr0 = (address & 1) ? 0x7D00 : 0x7E00; \ 1.38 state.bsr0 |= (address >> 16); \ 1.39 state.bsr1 = address & 0xffff; \ 1.40 - printf("ERR: BusError RD\n"); \ 1.41 - m68k_pulse_bus_error(); \ 1.42 + LOG("Bus Error while reading, addr %08X, statcode %d", address, st); \ 1.43 + if (state.ee) m68k_pulse_bus_error(); \ 1.44 return 0xFFFFFFFF; \ 1.45 } \ 1.46 } while (0)