Sun, 06 Mar 2011 21:04:44 +0000
Fix file modes
philpem@18 | 1 | module lm32_dp_ram( |
philpem@18 | 2 | clk_i, |
philpem@18 | 3 | rst_i, |
philpem@18 | 4 | we_i, |
philpem@18 | 5 | waddr_i, |
philpem@18 | 6 | wdata_i, |
philpem@18 | 7 | raddr_i, |
philpem@18 | 8 | rdata_o); |
philpem@18 | 9 | |
philpem@18 | 10 | parameter addr_width = 32; |
philpem@18 | 11 | parameter addr_depth = 1024; |
philpem@18 | 12 | parameter data_width = 8; |
philpem@18 | 13 | |
philpem@18 | 14 | input clk_i; |
philpem@18 | 15 | input rst_i; |
philpem@18 | 16 | input we_i; |
philpem@18 | 17 | input [addr_width-1:0] waddr_i; |
philpem@18 | 18 | input [data_width-1:0] wdata_i; |
philpem@18 | 19 | input [addr_width-1:0] raddr_i; |
philpem@18 | 20 | output [data_width-1:0] rdata_o; |
philpem@18 | 21 | |
philpem@18 | 22 | reg [data_width-1:0] ram[addr_depth-1:0]; |
philpem@18 | 23 | |
philpem@18 | 24 | reg [addr_width-1:0] raddr_r; |
philpem@18 | 25 | assign rdata_o = ram[raddr_r]; |
philpem@18 | 26 | |
philpem@18 | 27 | always @ (posedge clk_i) |
philpem@18 | 28 | begin |
philpem@18 | 29 | if (we_i) |
philpem@18 | 30 | ram[waddr_i] <= wdata_i; |
philpem@18 | 31 | raddr_r <= raddr_i; |
philpem@18 | 32 | end |
philpem@18 | 33 | |
philpem@18 | 34 | endmodule |
philpem@18 | 35 |