IPCores/lm32_cpu / changelog

Added tag LM32_V3_5_BASELINE for changeset 07be9df9fee8

• Fri, 13 Aug 2010 01:16:05 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Fri, 13 Aug 2010 01:16:05 +0100] rev 10
• Added tag LM32_V3_5_BASELINE for changeset 07be9df9fee8

[MERGE] Merge in changes from Lattice LM32 v3.5 LM32_V3_5_WITH_PATCHES

• Fri, 13 Aug 2010 01:15:02 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Fri, 13 Aug 2010 01:15:02 +0100] rev 9
• [MERGE] Merge in changes from Lattice LM32 v3.5

[UPSTREAM PULL] update baseline to LatticeMico32 v3.5 and add documentation LM32_V3_5_BASELINE

• Fri, 13 Aug 2010 01:13:04 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Fri, 13 Aug 2010 01:13:04 +0100] rev 8
• [UPSTREAM PULL] update baseline to LatticeMico32 v3.5 and add documentation
  
  Update baseline head to LatticeMico32 v3.5, from "LatticeMico32 System for
  ispLEVER on Linux" v8.1 (Jun 2010). Downloaded from:
  http://www.latticesemi.com/dynamic/index.cfm?fuseaction=view_documents&document_type=65&sloc=01-01-08-11-48&source=sidebar

Make cache 2-way associative

• Tue, 06 Apr 2010 18:27:55 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Tue, 06 Apr 2010 18:27:55 +0100] rev 7
• Make cache 2-way associative
  
  Switched from Direct Mapped to 2-Way Set Associative caches. Should boost speed
  a bit.

reduce size of caches to fit in DE1 FPGA

• Mon, 05 Apr 2010 21:00:31 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Mon, 05 Apr 2010 21:00:31 +0100] rev 6
• reduce size of caches to fit in DE1 FPGA
  
  The default cache size makes the Icache and Dcache "just a bit" too big to
  fit in the EP2C20 FPGA on the DE1 board. This commit reduces the Icache and
  Dcache sizes to the defaults shown in the LatticeMico32 Processor Reference
  Manual (pages 36 and 37).

disable caches, they use too much RAM :(

• Mon, 05 Apr 2010 20:25:37 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Mon, 05 Apr 2010 20:25:37 +0100] rev 5
• disable caches, they use too much RAM :(

add better comment re Xilinx Xst cache issues

• Mon, 05 Apr 2010 20:23:04 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Mon, 05 Apr 2010 20:23:04 +0100] rev 4
• add better comment re Xilinx Xst cache issues

remove more Lattice-specific fluff

• Sun, 04 Apr 2010 22:05:07 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Sun, 04 Apr 2010 22:05:07 +0100] rev 3
• remove more Lattice-specific fluff
  
  Code now synthesizes properly on Altera Quartus 9.0 build 235