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IPCores/lm32_cpu / changelog

changelog

Enable Spartan 6 JTAG TAP only if selected (Michael Walle)

  • Sun, 06 Mar 2011 19:49:17 +0000
  • by Philip Pemberton <philpem@philpem.me.uk> [Sun, 06 Mar 2011 19:49:17 +0000] rev 17
  • Enable Spartan 6 JTAG TAP only if selected (Michael Walle)

    Original-Author: Michael Walle <michael walle.cc>
    Original-Source: milkymist e7d77749236d73fcdc65

Add JTAG interface for Xilinx Spartan 6 (Michael Walle)

  • Sun, 06 Mar 2011 19:48:34 +0000
  • by Philip Pemberton <philpem@philpem.me.uk> [Sun, 06 Mar 2011 19:48:34 +0000] rev 16
  • Add JTAG interface for Xilinx Spartan 6 (Michael Walle)

    Original-Source: Milkymist mailing list posting, 2010-09-23
    Original-Message-Id: <201009232334.04219.michael@walle.cc>
    Original-Author: Michael Walle <michael walle.cc>

fix jtag_cores typo

  • Sun, 06 Mar 2011 19:32:57 +0000
  • by Philip Pemberton <philpem@philpem.me.uk> [Sun, 06 Mar 2011 19:32:57 +0000] rev 15
  • fix jtag_cores typo

    Original-Author: lekernel
    Original-Source: milkymist 96d0e3995ce0c9d7cbb7

Clean up LM32 sources and enable debugging. Remove monitor ROM.

  • Sun, 06 Mar 2011 19:31:09 +0000
  • by Philip Pemberton <philpem@philpem.me.uk> [Sun, 06 Mar 2011 19:31:09 +0000] rev 14
  • Clean up LM32 sources and enable debugging. Remove monitor ROM.

    Original-Author: lekernel
    Original-Source: milkymist 2dc88f973cfdd7ad5aa4

Rename interrupt unit module instance to 'interrupt_unit'

  • Sun, 06 Mar 2011 19:23:51 +0000
  • by Philip Pemberton <philpem@philpem.me.uk> [Sun, 06 Mar 2011 19:23:51 +0000] rev 13
  • Rename interrupt unit module instance to 'interrupt_unit'

    Original-Author: lekernel
    Original-Source: milkymist f061a3098702da3b8a81

Make interrupts active high

  • Sun, 06 Mar 2011 19:22:27 +0000
  • by Philip Pemberton <philpem@philpem.me.uk> [Sun, 06 Mar 2011 19:22:27 +0000] rev 12
  • Make interrupts active high

    Original-Author: lekernel
    Original-Source: milkymist 5e8c03b53aaa820f3b43

Added tag LM32_V3_5_WITH_PATCHES for changeset 0eb235b23d55

  • Fri, 13 Aug 2010 01:16:35 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Fri, 13 Aug 2010 01:16:35 +0100] rev 11
  • Added tag LM32_V3_5_WITH_PATCHES for changeset 0eb235b23d55

Added tag LM32_V3_5_BASELINE for changeset 07be9df9fee8

  • Fri, 13 Aug 2010 01:16:05 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Fri, 13 Aug 2010 01:16:05 +0100] rev 10
  • Added tag LM32_V3_5_BASELINE for changeset 07be9df9fee8

[MERGE] Merge in changes from Lattice LM32 v3.5 LM32_V3_5_WITH_PATCHES

  • Fri, 13 Aug 2010 01:15:02 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Fri, 13 Aug 2010 01:15:02 +0100] rev 9
  • [MERGE] Merge in changes from Lattice LM32 v3.5

[UPSTREAM PULL] update baseline to LatticeMico32 v3.5 and add documentation LM32_V3_5_BASELINE

  • Fri, 13 Aug 2010 01:13:04 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Fri, 13 Aug 2010 01:13:04 +0100] rev 8
  • [UPSTREAM PULL] update baseline to LatticeMico32 v3.5 and add documentation

    Update baseline head to LatticeMico32 v3.5, from "LatticeMico32 System for
    ispLEVER on Linux" v8.1 (Jun 2010). Downloaded from:
    http://www.latticesemi.com/dynamic/index.cfm?fuseaction=view_documents&document_type=65&sloc=01-01-08-11-48&source=sidebar

Make cache 2-way associative

  • Tue, 06 Apr 2010 18:27:55 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Tue, 06 Apr 2010 18:27:55 +0100] rev 7
  • Make cache 2-way associative

    Switched from Direct Mapped to 2-Way Set Associative caches. Should boost speed
    a bit.

reduce size of caches to fit in DE1 FPGA

  • Mon, 05 Apr 2010 21:00:31 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Mon, 05 Apr 2010 21:00:31 +0100] rev 6
  • reduce size of caches to fit in DE1 FPGA

    The default cache size makes the Icache and Dcache "just a bit" too big to
    fit in the EP2C20 FPGA on the DE1 board. This commit reduces the Icache and
    Dcache sizes to the defaults shown in the LatticeMico32 Processor Reference
    Manual (pages 36 and 37).

disable caches, they use too much RAM :(

  • Mon, 05 Apr 2010 20:25:37 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Mon, 05 Apr 2010 20:25:37 +0100] rev 5
  • disable caches, they use too much RAM :(

add better comment re Xilinx Xst cache issues

  • Mon, 05 Apr 2010 20:23:04 +0100
  • by Philip Pemberton <philpem@philpem.me.uk> [Mon, 05 Apr 2010 20:23:04 +0100] rev 4
  • add better comment re Xilinx Xst cache issues
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