IPCores/lm32_cpu / file diff

     1.1 --- a/lm32_monitor.v	Fri Aug 13 01:13:04 2010 +0100
     1.2 +++ b/lm32_monitor.v	Sun Mar 06 21:14:43 2011 +0000
     1.3 @@ -130,13 +130,7 @@
     1.4      end
     1.5      else
     1.6      begin
     1.7 -        case (state)
     1.8 -        2'b00:
     1.9 -        begin
    1.10 -            // Wait for a Wishbone access
    1.11 -            if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE))
    1.12 -                state <= 2'b01;
    1.13 -        end
    1.14 +        casez (state)
    1.15          2'b01:
    1.16          begin
    1.17              // Output read data to Wishbone
    1.18 @@ -160,6 +154,14 @@
    1.19              MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
    1.20              state <= 2'b00;
    1.21          end
    1.22 +        default:
    1.23 +        begin
    1.24 +           write_enable <= `FALSE;
    1.25 +           MON_ACK_O <= `FALSE;
    1.26 +            // Wait for a Wishbone access
    1.27 +            if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE))
    1.28 +                state <= 2'b01;
    1.29 +        end
    1.30          endcase        
    1.31      end
    1.32  end