1.1 --- a/lm32_debug.v Sun Mar 06 21:14:43 2011 +0000 1.2 +++ b/lm32_debug.v Sat Aug 06 00:02:46 2011 +0100 1.3 @@ -1,18 +1,39 @@ 1.4 -// ============================================================================= 1.5 -// COPYRIGHT NOTICE 1.6 -// Copyright 2006 (c) Lattice Semiconductor Corporation 1.7 -// ALL RIGHTS RESERVED 1.8 -// This confidential and proprietary software may be used only as authorised by 1.9 -// a licensing agreement from Lattice Semiconductor Corporation. 1.10 -// The entire notice above must be reproduced on all authorized copies and 1.11 -// copies may only be made to the extent permitted by a licensing agreement from 1.12 -// Lattice Semiconductor Corporation. 1.13 +// ================================================================== 1.14 +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 1.15 +// ------------------------------------------------------------------ 1.16 +// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation 1.17 +// ALL RIGHTS RESERVED 1.18 +// ------------------------------------------------------------------ 1.19 +// 1.20 +// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. 1.21 +// 1.22 +// Permission: 1.23 +// 1.24 +// Lattice Semiconductor grants permission to use this code 1.25 +// pursuant to the terms of the Lattice Semiconductor Corporation 1.26 +// Open Source License Agreement. 1.27 +// 1.28 +// Disclaimer: 1.29 // 1.30 -// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.31 -// 5555 NE Moore Court 408-826-6000 (other locations) 1.32 -// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.33 -// U.S.A email: techsupport@latticesemi.com 1.34 -// =============================================================================/ 1.35 +// Lattice Semiconductor provides no warranty regarding the use or 1.36 +// functionality of this code. It is the user's responsibility to 1.37 +// verify the user’s design for consistency and functionality through 1.38 +// the use of formal verification methods. 1.39 +// 1.40 +// -------------------------------------------------------------------- 1.41 +// 1.42 +// Lattice Semiconductor Corporation 1.43 +// 5555 NE Moore Court 1.44 +// Hillsboro, OR 97214 1.45 +// U.S.A 1.46 +// 1.47 +// TEL: 1-800-Lattice (USA and Canada) 1.48 +// 503-286-8001 (other locations) 1.49 +// 1.50 +// web: http://www.latticesemi.com/ 1.51 +// email: techsupport@latticesemi.com 1.52 +// 1.53 +// -------------------------------------------------------------------- 1.54 // FILE DETAILS 1.55 // Project : LatticeMico32 1.56 // File : lm32_debug.v 1.57 @@ -226,15 +247,15 @@ 1.58 begin 1.59 if (rst_i == `TRUE) 1.60 begin 1.61 - bp_a[i] <= {`LM32_PC_WIDTH{1'bx}}; 1.62 - bp_e[i] <= `FALSE; 1.63 + bp_a[i] <= #1 {`LM32_PC_WIDTH{1'bx}}; 1.64 + bp_e[i] <= #1 `FALSE; 1.65 end 1.66 else 1.67 begin 1.68 if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i)) 1.69 begin 1.70 - bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG]; 1.71 - bp_e[i] <= debug_csr_write_data[0]; 1.72 + bp_a[i] <= #1 debug_csr_write_data[`LM32_PC_RNG]; 1.73 + bp_e[i] <= #1 debug_csr_write_data[0]; 1.74 end 1.75 end 1.76 end 1.77 @@ -249,17 +270,17 @@ 1.78 begin 1.79 if (rst_i == `TRUE) 1.80 begin 1.81 - wp[i] <= {`LM32_WORD_WIDTH{1'bx}}; 1.82 - wpc_c[i] <= `LM32_WPC_C_DISABLED; 1.83 + wp[i] <= #1 {`LM32_WORD_WIDTH{1'bx}}; 1.84 + wpc_c[i] <= #1 `LM32_WPC_C_DISABLED; 1.85 end 1.86 else 1.87 begin 1.88 if (debug_csr_write_enable == `TRUE) 1.89 begin 1.90 if (debug_csr == `LM32_CSR_DC) 1.91 - wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2]; 1.92 + wpc_c[i] <= #1 debug_csr_write_data[3+i*2:2+i*2]; 1.93 if (debug_csr == `LM32_CSR_WP0 + i) 1.94 - wp[i] <= debug_csr_write_data; 1.95 + wp[i] <= #1 debug_csr_write_data; 1.96 end 1.97 end 1.98 end 1.99 @@ -270,11 +291,11 @@ 1.100 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.101 begin 1.102 if (rst_i == `TRUE) 1.103 - dc_re <= `FALSE; 1.104 + dc_re <= #1 `FALSE; 1.105 else 1.106 begin 1.107 if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC)) 1.108 - dc_re <= debug_csr_write_data[1]; 1.109 + dc_re <= #1 debug_csr_write_data[1]; 1.110 end 1.111 end 1.112 1.113 @@ -284,18 +305,18 @@ 1.114 begin 1.115 if (rst_i == `TRUE) 1.116 begin 1.117 - state <= `LM32_DEBUG_SS_STATE_IDLE; 1.118 - dc_ss <= `FALSE; 1.119 + state <= #1 `LM32_DEBUG_SS_STATE_IDLE; 1.120 + dc_ss <= #1 `FALSE; 1.121 end 1.122 else 1.123 begin 1.124 if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC)) 1.125 begin 1.126 - dc_ss <= debug_csr_write_data[0]; 1.127 + dc_ss <= #1 debug_csr_write_data[0]; 1.128 if (debug_csr_write_data[0] == `FALSE) 1.129 - state <= `LM32_DEBUG_SS_STATE_IDLE; 1.130 + state <= #1 `LM32_DEBUG_SS_STATE_IDLE; 1.131 else 1.132 - state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET; 1.133 + state <= #1 `LM32_DEBUG_SS_STATE_WAIT_FOR_RET; 1.134 end 1.135 case (state) 1.136 `LM32_DEBUG_SS_STATE_WAIT_FOR_RET: 1.137 @@ -306,26 +327,26 @@ 1.138 ) 1.139 && (stall_x == `FALSE) 1.140 ) 1.141 - state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 1.142 + state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 1.143 end 1.144 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN: 1.145 begin 1.146 // Wait for an instruction to be executed 1.147 if ((q_x == `TRUE) && (stall_x == `FALSE)) 1.148 - state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT; 1.149 + state <= #1 `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT; 1.150 end 1.151 `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT: 1.152 begin 1.153 // Wait for exception to be raised 1.154 `ifdef CFG_DCACHE_ENABLED 1.155 if (dcache_refill_request == `TRUE) 1.156 - state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 1.157 + state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 1.158 else 1.159 `endif 1.160 if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE)) 1.161 begin 1.162 - dc_ss <= `FALSE; 1.163 - state <= `LM32_DEBUG_SS_STATE_RESTART; 1.164 + dc_ss <= #1 `FALSE; 1.165 + state <= #1 `LM32_DEBUG_SS_STATE_RESTART; 1.166 end 1.167 end 1.168 `LM32_DEBUG_SS_STATE_RESTART: 1.169 @@ -333,10 +354,10 @@ 1.170 // Watch to see if stepped instruction is restarted due to a cache miss 1.171 `ifdef CFG_DCACHE_ENABLED 1.172 if (dcache_refill_request == `TRUE) 1.173 - state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 1.174 + state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 1.175 else 1.176 `endif 1.177 - state <= `LM32_DEBUG_SS_STATE_IDLE; 1.178 + state <= #1 `LM32_DEBUG_SS_STATE_IDLE; 1.179 end 1.180 endcase 1.181 end