Sun, 06 Mar 2011 21:14:43 +0000
[UPSTREAM PULL] Update baseline to LatticeMico32 v3.6 from Diamond 1.1-lm32 distribution package (datestamp Nov 2010)
1 // =============================================================================
2 // COPYRIGHT NOTICE
3 // Copyright 2006 (c) Lattice Semiconductor Corporation
4 // ALL RIGHTS RESERVED
5 // This confidential and proprietary software may be used only as authorised by
6 // a licensing agreement from Lattice Semiconductor Corporation.
7 // The entire notice above must be reproduced on all authorized copies and
8 // copies may only be made to the extent permitted by a licensing agreement from
9 // Lattice Semiconductor Corporation.
10 //
11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12 // 5555 NE Moore Court 408-826-6000 (other locations)
13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
14 // U.S.A email: techsupport@latticesemi.com
15 // =============================================================================/
16 // FILE DETAILS
17 // Project : LatticeMico32
18 // File : lm32_cpu.v
19 // Title : Top-level of CPU.
20 // Dependencies : lm32_include.v
21 //
22 // Version 3.4
23 // 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were
24 // never serviced.
25 //
26 // Version 3.3
27 // 1. Feature: Support for memory that is tightly coupled to processor core, and
28 // has a single-cycle access latency (same as caches). Instruction port has
29 // access to a dedicated physically-mapped memory. Data port has access to
30 // a dedicated physically-mapped memory. In order to be able to manipulate
31 // values in both these memories via the debugger, these memories also
32 // interface with the data port of LM32.
33 // 2. Feature: Extended Configuration Register
34 // 3. Bug Fix: Removed port names that conflict with keywords reserved in System-
35 // Verilog.
36 //
37 // Version 3.2
38 // 1. Bug Fix: Single-stepping a load/store to invalid address causes debugger to
39 // hang. At the same time CPU fails to register data bus error exception. Bug
40 // is caused because (a) data bus error exception occurs after load/store has
41 // passed X stage and next sequential instruction (e.g., brk) is already in X
42 // stage, and (b) data bus error exception had lower priority than, say, brk
43 // exception.
44 // 2. Bug Fix: If a brk (or scall/eret/bret) sequentially follows a load/store to
45 // invalid location, CPU will fail to register data bus error exception. The
46 // solution is to stall scall/eret/bret/brk instructions in D pipeline stage
47 // until load/store has completed.
48 // 3. Feature: Enable precise identification of load/store that causes seg fault.
49 // 4. SYNC resets used for register file when implemented in EBRs.
50 //
51 // Version 3.1
52 // 1. Feature: LM32 Register File can now be mapped in to on-chip block RAM (EBR)
53 // instead of distributed memory by enabling the option in LM32 GUI.
54 // 2. Feature: LM32 also adds a static branch predictor to improve branch
55 // performance. All immediate-based forward-pointing branches are predicted
56 // not-taken. All immediate-based backward-pointing branches are predicted taken.
57 //
58 // Version 7.0SP2, 3.0
59 // No Change
60 //
61 // Version 6.1.17
62 // Initial Release
63 // =============================================================================
65 `include "lm32_include.v"
67 /////////////////////////////////////////////////////
68 // Module interface
69 /////////////////////////////////////////////////////
71 module lm32_cpu (
72 // ----- Inputs -------
73 clk_i,
74 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
75 clk_n_i,
76 `endif
77 rst_i,
78 // From external devices
79 `ifdef CFG_INTERRUPTS_ENABLED
80 interrupt_n,
81 `endif
82 // From user logic
83 `ifdef CFG_USER_ENABLED
84 user_result,
85 user_complete,
86 `endif
87 `ifdef CFG_JTAG_ENABLED
88 // From JTAG
89 jtag_clk,
90 jtag_update,
91 jtag_reg_q,
92 jtag_reg_addr_q,
93 `endif
94 `ifdef CFG_IWB_ENABLED
95 // Instruction Wishbone master
96 I_DAT_I,
97 I_ACK_I,
98 I_ERR_I,
99 I_RTY_I,
100 `endif
101 // Data Wishbone master
102 D_DAT_I,
103 D_ACK_I,
104 D_ERR_I,
105 D_RTY_I,
106 // ----- Outputs -------
107 `ifdef CFG_TRACE_ENABLED
108 trace_pc,
109 trace_pc_valid,
110 trace_exception,
111 trace_eid,
112 trace_eret,
113 `ifdef CFG_DEBUG_ENABLED
114 trace_bret,
115 `endif
116 `endif
117 `ifdef CFG_JTAG_ENABLED
118 jtag_reg_d,
119 jtag_reg_addr_d,
120 `endif
121 `ifdef CFG_USER_ENABLED
122 user_valid,
123 user_opcode,
124 user_operand_0,
125 user_operand_1,
126 `endif
127 `ifdef CFG_IWB_ENABLED
128 // Instruction Wishbone master
129 I_DAT_O,
130 I_ADR_O,
131 I_CYC_O,
132 I_SEL_O,
133 I_STB_O,
134 I_WE_O,
135 I_CTI_O,
136 I_LOCK_O,
137 I_BTE_O,
138 `endif
139 // Data Wishbone master
140 D_DAT_O,
141 D_ADR_O,
142 D_CYC_O,
143 D_SEL_O,
144 D_STB_O,
145 D_WE_O,
146 D_CTI_O,
147 D_LOCK_O,
148 D_BTE_O
149 );
151 /////////////////////////////////////////////////////
152 // Parameters
153 /////////////////////////////////////////////////////
155 parameter eba_reset = `CFG_EBA_RESET; // Reset value for EBA CSR
156 `ifdef CFG_DEBUG_ENABLED
157 parameter deba_reset = `CFG_DEBA_RESET; // Reset value for DEBA CSR
158 `endif
160 `ifdef CFG_ICACHE_ENABLED
161 parameter icache_associativity = `CFG_ICACHE_ASSOCIATIVITY; // Associativity of the cache (Number of ways)
162 parameter icache_sets = `CFG_ICACHE_SETS; // Number of sets
163 parameter icache_bytes_per_line = `CFG_ICACHE_BYTES_PER_LINE; // Number of bytes per cache line
164 parameter icache_base_address = `CFG_ICACHE_BASE_ADDRESS; // Base address of cachable memory
165 parameter icache_limit = `CFG_ICACHE_LIMIT; // Limit (highest address) of cachable memory
166 `else
167 parameter icache_associativity = 1;
168 parameter icache_sets = 512;
169 parameter icache_bytes_per_line = 16;
170 parameter icache_base_address = 0;
171 parameter icache_limit = 0;
172 `endif
174 `ifdef CFG_DCACHE_ENABLED
175 parameter dcache_associativity = `CFG_DCACHE_ASSOCIATIVITY; // Associativity of the cache (Number of ways)
176 parameter dcache_sets = `CFG_DCACHE_SETS; // Number of sets
177 parameter dcache_bytes_per_line = `CFG_DCACHE_BYTES_PER_LINE; // Number of bytes per cache line
178 parameter dcache_base_address = `CFG_DCACHE_BASE_ADDRESS; // Base address of cachable memory
179 parameter dcache_limit = `CFG_DCACHE_LIMIT; // Limit (highest address) of cachable memory
180 `else
181 parameter dcache_associativity = 1;
182 parameter dcache_sets = 512;
183 parameter dcache_bytes_per_line = 16;
184 parameter dcache_base_address = 0;
185 parameter dcache_limit = 0;
186 `endif
188 `ifdef CFG_DEBUG_ENABLED
189 parameter watchpoints = `CFG_WATCHPOINTS; // Number of h/w watchpoint CSRs
190 `else
191 parameter watchpoints = 0;
192 `endif
193 `ifdef CFG_ROM_DEBUG_ENABLED
194 parameter breakpoints = `CFG_BREAKPOINTS; // Number of h/w breakpoint CSRs
195 `else
196 parameter breakpoints = 0;
197 `endif
199 `ifdef CFG_INTERRUPTS_ENABLED
200 parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts
201 `else
202 parameter interrupts = 0;
203 `endif
205 /////////////////////////////////////////////////////
206 // Inputs
207 /////////////////////////////////////////////////////
209 input clk_i; // Clock
210 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
211 input clk_n_i; // Inverted clock
212 `endif
213 input rst_i; // Reset
215 `ifdef CFG_INTERRUPTS_ENABLED
216 input [`LM32_INTERRUPT_RNG] interrupt_n; // Interrupt pins, active-low
217 `endif
219 `ifdef CFG_USER_ENABLED
220 input [`LM32_WORD_RNG] user_result; // User-defined instruction result
221 input user_complete; // User-defined instruction execution is complete
222 `endif
224 `ifdef CFG_JTAG_ENABLED
225 input jtag_clk; // JTAG clock
226 input jtag_update; // JTAG state machine is in data register update state
227 input [`LM32_BYTE_RNG] jtag_reg_q;
228 input [2:0] jtag_reg_addr_q;
229 `endif
231 `ifdef CFG_IWB_ENABLED
232 input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data
233 input I_ACK_I; // Instruction Wishbone interface acknowledgement
234 input I_ERR_I; // Instruction Wishbone interface error
235 input I_RTY_I; // Instruction Wishbone interface retry
236 `endif
238 input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
239 input D_ACK_I; // Data Wishbone interface acknowledgement
240 input D_ERR_I; // Data Wishbone interface error
241 input D_RTY_I; // Data Wishbone interface retry
243 /////////////////////////////////////////////////////
244 // Outputs
245 /////////////////////////////////////////////////////
247 `ifdef CFG_TRACE_ENABLED
248 output [`LM32_PC_RNG] trace_pc; // PC to trace
249 reg [`LM32_PC_RNG] trace_pc;
250 output trace_pc_valid; // Indicates that a new trace PC is valid
251 reg trace_pc_valid;
252 output trace_exception; // Indicates an exception has occured
253 reg trace_exception;
254 output [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured
255 reg [`LM32_EID_RNG] trace_eid;
256 output trace_eret; // Indicates an eret instruction has been executed
257 reg trace_eret;
258 `ifdef CFG_DEBUG_ENABLED
259 output trace_bret; // Indicates a bret instruction has been executed
260 reg trace_bret;
261 `endif
262 `endif
264 `ifdef CFG_JTAG_ENABLED
265 output [`LM32_BYTE_RNG] jtag_reg_d;
266 wire [`LM32_BYTE_RNG] jtag_reg_d;
267 output [2:0] jtag_reg_addr_d;
268 wire [2:0] jtag_reg_addr_d;
269 `endif
271 `ifdef CFG_USER_ENABLED
272 output user_valid; // Indicates if user_opcode is valid
273 wire user_valid;
274 output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode
275 reg [`LM32_USER_OPCODE_RNG] user_opcode;
276 output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction
277 wire [`LM32_WORD_RNG] user_operand_0;
278 output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction
279 wire [`LM32_WORD_RNG] user_operand_1;
280 `endif
282 `ifdef CFG_IWB_ENABLED
283 output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data
284 wire [`LM32_WORD_RNG] I_DAT_O;
285 output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address
286 wire [`LM32_WORD_RNG] I_ADR_O;
287 output I_CYC_O; // Instruction Wishbone interface cycle
288 wire I_CYC_O;
289 output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select
290 wire [`LM32_BYTE_SELECT_RNG] I_SEL_O;
291 output I_STB_O; // Instruction Wishbone interface strobe
292 wire I_STB_O;
293 output I_WE_O; // Instruction Wishbone interface write enable
294 wire I_WE_O;
295 output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type
296 wire [`LM32_CTYPE_RNG] I_CTI_O;
297 output I_LOCK_O; // Instruction Wishbone interface lock bus
298 wire I_LOCK_O;
299 output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type
300 wire [`LM32_BTYPE_RNG] I_BTE_O;
301 `endif
303 output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
304 wire [`LM32_WORD_RNG] D_DAT_O;
305 output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
306 wire [`LM32_WORD_RNG] D_ADR_O;
307 output D_CYC_O; // Data Wishbone interface cycle
308 wire D_CYC_O;
309 output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select
310 wire [`LM32_BYTE_SELECT_RNG] D_SEL_O;
311 output D_STB_O; // Data Wishbone interface strobe
312 wire D_STB_O;
313 output D_WE_O; // Data Wishbone interface write enable
314 wire D_WE_O;
315 output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type
316 wire [`LM32_CTYPE_RNG] D_CTI_O;
317 output D_LOCK_O; // Date Wishbone interface lock bus
318 wire D_LOCK_O;
319 output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
320 wire [`LM32_BTYPE_RNG] D_BTE_O;
322 /////////////////////////////////////////////////////
323 // Internal nets and registers
324 /////////////////////////////////////////////////////
326 // Pipeline registers
328 `ifdef LM32_CACHE_ENABLED
329 reg valid_a; // Instruction in A stage is valid
330 `endif
331 reg valid_f; // Instruction in F stage is valid
332 reg valid_d; // Instruction in D stage is valid
333 reg valid_x; // Instruction in X stage is valid
334 reg valid_m; // Instruction in M stage is valid
335 reg valid_w; // Instruction in W stage is valid
337 wire q_x;
338 wire [`LM32_WORD_RNG] immediate_d; // Immediate operand
339 wire load_d; // Indicates a load instruction
340 reg load_x;
341 reg load_m;
342 wire load_q_x;
343 wire store_q_x;
344 wire store_d; // Indicates a store instruction
345 reg store_x;
346 reg store_m;
347 wire [`LM32_SIZE_RNG] size_d; // Size of load/store (byte, hword, word)
348 reg [`LM32_SIZE_RNG] size_x;
349 wire branch_d; // Indicates a branch instruction
350 wire branch_predict_d; // Indicates a branch is predicted
351 wire branch_predict_taken_d; // Indicates a branch is predicted taken
352 wire [`LM32_PC_RNG] branch_predict_address_d; // Address to which predicted branch jumps
353 wire [`LM32_PC_RNG] branch_target_d;
354 wire bi_unconditional;
355 wire bi_conditional;
356 reg branch_x;
357 reg branch_predict_x;
358 reg branch_predict_taken_x;
359 reg branch_m;
360 reg branch_predict_m;
361 reg branch_predict_taken_m;
362 wire branch_mispredict_taken_m; // Indicates a branch was mispredicted as taken
363 wire branch_flushX_m; // Indicates that instruction in X stage must be squashed
364 wire branch_reg_d; // Branch to register or immediate
365 wire [`LM32_PC_RNG] branch_offset_d; // Branch offset for immediate branches
366 reg [`LM32_PC_RNG] branch_target_x; // Address to branch to
367 reg [`LM32_PC_RNG] branch_target_m;
368 wire [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0_d; // Which result should be selected in D stage for operand 0
369 wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be selected in D stage for operand 1
371 wire x_result_sel_csr_d; // Select X stage result from CSRs
372 reg x_result_sel_csr_x;
373 `ifdef LM32_MC_ARITHMETIC_ENABLED
374 wire x_result_sel_mc_arith_d; // Select X stage result from multi-cycle arithmetic unit
375 reg x_result_sel_mc_arith_x;
376 `endif
377 `ifdef LM32_NO_BARREL_SHIFT
378 wire x_result_sel_shift_d; // Select X stage result from shifter
379 reg x_result_sel_shift_x;
380 `endif
381 `ifdef CFG_SIGN_EXTEND_ENABLED
382 wire x_result_sel_sext_d; // Select X stage result from sign-extend logic
383 reg x_result_sel_sext_x;
384 `endif
385 wire x_result_sel_logic_d; // Select X stage result from logic op unit
386 reg x_result_sel_logic_x;
387 `ifdef CFG_USER_ENABLED
388 wire x_result_sel_user_d; // Select X stage result from user-defined logic
389 reg x_result_sel_user_x;
390 `endif
391 wire x_result_sel_add_d; // Select X stage result from adder
392 reg x_result_sel_add_x;
393 wire m_result_sel_compare_d; // Select M stage result from comparison logic
394 reg m_result_sel_compare_x;
395 reg m_result_sel_compare_m;
396 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
397 wire m_result_sel_shift_d; // Select M stage result from shifter
398 reg m_result_sel_shift_x;
399 reg m_result_sel_shift_m;
400 `endif
401 wire w_result_sel_load_d; // Select W stage result from load/store unit
402 reg w_result_sel_load_x;
403 reg w_result_sel_load_m;
404 reg w_result_sel_load_w;
405 `ifdef CFG_PL_MULTIPLY_ENABLED
406 wire w_result_sel_mul_d; // Select W stage result from multiplier
407 reg w_result_sel_mul_x;
408 reg w_result_sel_mul_m;
409 reg w_result_sel_mul_w;
410 `endif
411 wire x_bypass_enable_d; // Whether result is bypassable in X stage
412 reg x_bypass_enable_x;
413 wire m_bypass_enable_d; // Whether result is bypassable in M stage
414 reg m_bypass_enable_x;
415 reg m_bypass_enable_m;
416 wire sign_extend_d; // Whether to sign-extend or zero-extend
417 reg sign_extend_x;
418 wire write_enable_d; // Register file write enable
419 reg write_enable_x;
420 wire write_enable_q_x;
421 reg write_enable_m;
422 wire write_enable_q_m;
423 reg write_enable_w;
424 wire write_enable_q_w;
425 wire read_enable_0_d; // Register file read enable 0
426 wire [`LM32_REG_IDX_RNG] read_idx_0_d; // Register file read index 0
427 wire read_enable_1_d; // Register file read enable 1
428 wire [`LM32_REG_IDX_RNG] read_idx_1_d; // Register file read index 1
429 wire [`LM32_REG_IDX_RNG] write_idx_d; // Register file write index
430 reg [`LM32_REG_IDX_RNG] write_idx_x;
431 reg [`LM32_REG_IDX_RNG] write_idx_m;
432 reg [`LM32_REG_IDX_RNG] write_idx_w;
433 wire [`LM32_CSR_RNG] csr_d; // CSR read/write index
434 reg [`LM32_CSR_RNG] csr_x;
435 wire [`LM32_CONDITION_RNG] condition_d; // Branch condition
436 reg [`LM32_CONDITION_RNG] condition_x;
437 `ifdef CFG_DEBUG_ENABLED
438 wire break_d; // Indicates a break instruction
439 reg break_x;
440 `endif
441 wire scall_d; // Indicates a scall instruction
442 reg scall_x;
443 wire eret_d; // Indicates an eret instruction
444 reg eret_x;
445 wire eret_q_x;
446 reg eret_m;
447 `ifdef CFG_TRACE_ENABLED
448 reg eret_w;
449 `endif
450 `ifdef CFG_DEBUG_ENABLED
451 wire bret_d; // Indicates a bret instruction
452 reg bret_x;
453 wire bret_q_x;
454 reg bret_m;
455 `ifdef CFG_TRACE_ENABLED
456 reg bret_w;
457 `endif
458 `endif
459 wire csr_write_enable_d; // CSR write enable
460 reg csr_write_enable_x;
461 wire csr_write_enable_q_x;
462 `ifdef CFG_USER_ENABLED
463 wire [`LM32_USER_OPCODE_RNG] user_opcode_d; // User-defined instruction opcode
464 `endif
466 `ifdef CFG_BUS_ERRORS_ENABLED
467 wire bus_error_d; // Indicates an bus error occured while fetching the instruction in this pipeline stage
468 reg bus_error_x;
469 reg data_bus_error_exception_m;
470 reg [`LM32_PC_RNG] memop_pc_w;
471 `endif
473 reg [`LM32_WORD_RNG] d_result_0; // Result of instruction in D stage (operand 0)
474 reg [`LM32_WORD_RNG] d_result_1; // Result of instruction in D stage (operand 1)
475 reg [`LM32_WORD_RNG] x_result; // Result of instruction in X stage
476 reg [`LM32_WORD_RNG] m_result; // Result of instruction in M stage
477 reg [`LM32_WORD_RNG] w_result; // Result of instruction in W stage
479 reg [`LM32_WORD_RNG] operand_0_x; // Operand 0 for X stage instruction
480 reg [`LM32_WORD_RNG] operand_1_x; // Operand 1 for X stage instruction
481 reg [`LM32_WORD_RNG] store_operand_x; // Data read from register to store
482 reg [`LM32_WORD_RNG] operand_m; // Operand for M stage instruction
483 reg [`LM32_WORD_RNG] operand_w; // Operand for W stage instruction
485 // To/from register file
486 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
487 reg [`LM32_WORD_RNG] reg_data_live_0;
488 reg [`LM32_WORD_RNG] reg_data_live_1;
489 reg use_buf; // Whether to use reg_data_live or reg_data_buf
490 reg [`LM32_WORD_RNG] reg_data_buf_0;
491 reg [`LM32_WORD_RNG] reg_data_buf_1;
492 `endif
493 `ifdef LM32_EBR_REGISTER_FILE
494 `else
495 reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1]; // Register file
496 `endif
497 wire [`LM32_WORD_RNG] reg_data_0; // Register file read port 0 data
498 wire [`LM32_WORD_RNG] reg_data_1; // Register file read port 1 data
499 reg [`LM32_WORD_RNG] bypass_data_0; // Register value 0 after bypassing
500 reg [`LM32_WORD_RNG] bypass_data_1; // Register value 1 after bypassing
501 wire reg_write_enable_q_w;
503 reg interlock; // Indicates pipeline should be stalled because of a read-after-write hazzard
505 wire stall_a; // Stall instruction in A pipeline stage
506 wire stall_f; // Stall instruction in F pipeline stage
507 wire stall_d; // Stall instruction in D pipeline stage
508 wire stall_x; // Stall instruction in X pipeline stage
509 wire stall_m; // Stall instruction in M pipeline stage
511 // To/from adder
512 wire adder_op_d; // Whether to add or subtract
513 reg adder_op_x;
514 reg adder_op_x_n; // Inverted version of adder_op_x
515 wire [`LM32_WORD_RNG] adder_result_x; // Result from adder
516 wire adder_overflow_x; // Whether a signed overflow occured
517 wire adder_carry_n_x; // Whether a carry was generated
519 // To/from logical operations unit
520 wire [`LM32_LOGIC_OP_RNG] logic_op_d; // Which operation to perform
521 reg [`LM32_LOGIC_OP_RNG] logic_op_x;
522 wire [`LM32_WORD_RNG] logic_result_x; // Result of logical operation
524 `ifdef CFG_SIGN_EXTEND_ENABLED
525 // From sign-extension unit
526 wire [`LM32_WORD_RNG] sextb_result_x; // Result of byte sign-extension
527 wire [`LM32_WORD_RNG] sexth_result_x; // Result of half-word sign-extenstion
528 wire [`LM32_WORD_RNG] sext_result_x; // Result of sign-extension specified by instruction
529 `endif
531 // To/from shifter
532 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
533 `ifdef CFG_ROTATE_ENABLED
534 wire rotate_d; // Whether we should rotate or shift
535 reg rotate_x;
536 `endif
537 wire direction_d; // Which direction to shift in
538 reg direction_x;
539 wire [`LM32_WORD_RNG] shifter_result_m; // Result of shifter
540 `endif
541 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
542 wire shift_left_d; // Indicates whether to perform a left shift or not
543 wire shift_left_q_d;
544 wire shift_right_d; // Indicates whether to perform a right shift or not
545 wire shift_right_q_d;
546 `endif
547 `ifdef LM32_NO_BARREL_SHIFT
548 wire [`LM32_WORD_RNG] shifter_result_x; // Result of single-bit right shifter
549 `endif
551 // To/from multiplier
552 `ifdef LM32_MULTIPLY_ENABLED
553 wire [`LM32_WORD_RNG] multiplier_result_w; // Result from multiplier
554 `endif
555 `ifdef CFG_MC_MULTIPLY_ENABLED
556 wire multiply_d; // Indicates whether to perform a multiply or not
557 wire multiply_q_d;
558 `endif
560 // To/from divider
561 `ifdef CFG_MC_DIVIDE_ENABLED
562 wire divide_d; // Indicates whether to perform a divider or not
563 wire divide_q_d;
564 wire modulus_d;
565 wire modulus_q_d;
566 wire divide_by_zero_x; // Indicates an attempt was made to divide by zero
567 `endif
569 // To from multi-cycle arithmetic unit
570 `ifdef LM32_MC_ARITHMETIC_ENABLED
571 wire mc_stall_request_x; // Multi-cycle arithmetic unit stall request
572 wire [`LM32_WORD_RNG] mc_result_x;
573 `endif
575 // From CSRs
576 `ifdef CFG_INTERRUPTS_ENABLED
577 wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs
578 `endif
579 wire [`LM32_WORD_RNG] cfg; // Configuration CSR
580 wire [`LM32_WORD_RNG] cfg2; // Extended Configuration CSR
581 `ifdef CFG_CYCLE_COUNTER_ENABLED
582 reg [`LM32_WORD_RNG] cc; // Cycle counter CSR
583 `endif
584 reg [`LM32_WORD_RNG] csr_read_data_x; // Data read from CSRs
586 // To/from instruction unit
587 wire [`LM32_PC_RNG] pc_f; // PC of instruction in F stage
588 wire [`LM32_PC_RNG] pc_d; // PC of instruction in D stage
589 wire [`LM32_PC_RNG] pc_x; // PC of instruction in X stage
590 wire [`LM32_PC_RNG] pc_m; // PC of instruction in M stage
591 wire [`LM32_PC_RNG] pc_w; // PC of instruction in W stage
592 `ifdef CFG_TRACE_ENABLED
593 reg [`LM32_PC_RNG] pc_c; // PC of last commited instruction
594 `endif
595 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
596 wire [`LM32_INSTRUCTION_RNG] instruction_f; // Instruction in F stage
597 `endif
598 //pragma attribute instruction_d preserve_signal true
599 //pragma attribute instruction_d preserve_driver true
600 wire [`LM32_INSTRUCTION_RNG] instruction_d; // Instruction in D stage
601 `ifdef CFG_ICACHE_ENABLED
602 wire iflush; // Flush instruction cache
603 wire icache_stall_request; // Stall pipeline because instruction cache is busy
604 wire icache_restart_request; // Restart instruction that caused an instruction cache miss
605 wire icache_refill_request; // Request to refill instruction cache
606 wire icache_refilling; // Indicates the instruction cache is being refilled
607 `endif
608 `ifdef CFG_IROM_ENABLED
609 wire [`LM32_WORD_RNG] irom_store_data_m; // Store data to instruction ROM
610 wire [`LM32_WORD_RNG] irom_address_xm; // Address to instruction ROM from load-store unit
611 wire [`LM32_WORD_RNG] irom_data_m; // Load data from instruction ROM
612 wire irom_we_xm; // Indicates data needs to be written to instruction ROM
613 wire irom_stall_request_x; // Indicates D stage needs to be stalled on a store to instruction ROM
614 `endif
616 // To/from load/store unit
617 `ifdef CFG_DCACHE_ENABLED
618 wire dflush_x; // Flush data cache
619 reg dflush_m;
620 wire dcache_stall_request; // Stall pipeline because data cache is busy
621 wire dcache_restart_request; // Restart instruction that caused a data cache miss
622 wire dcache_refill_request; // Request to refill data cache
623 wire dcache_refilling; // Indicates the data cache is being refilled
624 `endif
625 wire [`LM32_WORD_RNG] load_data_w; // Result of a load instruction
626 wire stall_wb_load; // Stall pipeline because of a load via the data Wishbone interface
628 // To/from JTAG interface
629 `ifdef CFG_JTAG_ENABLED
630 `ifdef CFG_JTAG_UART_ENABLED
631 wire [`LM32_WORD_RNG] jtx_csr_read_data; // Read data for JTX CSR
632 wire [`LM32_WORD_RNG] jrx_csr_read_data; // Read data for JRX CSR
633 `endif
634 `ifdef CFG_HW_DEBUG_ENABLED
635 wire jtag_csr_write_enable; // Debugger CSR write enable
636 wire [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR
637 wire [`LM32_CSR_RNG] jtag_csr; // Which CSR to write
638 wire jtag_read_enable;
639 wire [`LM32_BYTE_RNG] jtag_read_data;
640 wire jtag_write_enable;
641 wire [`LM32_BYTE_RNG] jtag_write_data;
642 wire [`LM32_WORD_RNG] jtag_address;
643 wire jtag_access_complete;
644 `endif
645 `ifdef CFG_DEBUG_ENABLED
646 wire jtag_break; // Request from debugger to raise a breakpoint
647 `endif
648 `endif
650 // Hazzard detection
651 wire raw_x_0; // RAW hazzard between instruction in X stage and read port 0
652 wire raw_x_1; // RAW hazzard between instruction in X stage and read port 1
653 wire raw_m_0; // RAW hazzard between instruction in M stage and read port 0
654 wire raw_m_1; // RAW hazzard between instruction in M stage and read port 1
655 wire raw_w_0; // RAW hazzard between instruction in W stage and read port 0
656 wire raw_w_1; // RAW hazzard between instruction in W stage and read port 1
658 // Control flow
659 wire cmp_zero; // Result of comparison is zero
660 wire cmp_negative; // Result of comparison is negative
661 wire cmp_overflow; // Comparison produced an overflow
662 wire cmp_carry_n; // Comparison produced a carry, inverted
663 reg condition_met_x; // Condition of branch instruction is met
664 reg condition_met_m;
665 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
666 wire branch_taken_x; // Branch is taken in X stage
667 `endif
668 wire branch_taken_m; // Branch is taken in M stage
670 wire kill_f; // Kill instruction in F stage
671 wire kill_d; // Kill instruction in D stage
672 wire kill_x; // Kill instruction in X stage
673 wire kill_m; // Kill instruction in M stage
674 wire kill_w; // Kill instruction in W stage
676 reg [`LM32_PC_WIDTH+2-1:8] eba; // Exception Base Address (EBA) CSR
677 `ifdef CFG_DEBUG_ENABLED
678 reg [`LM32_PC_WIDTH+2-1:8] deba; // Debug Exception Base Address (DEBA) CSR
679 `endif
680 reg [`LM32_EID_RNG] eid_x; // Exception ID in X stage
681 `ifdef CFG_TRACE_ENABLED
682 reg [`LM32_EID_RNG] eid_m; // Exception ID in M stage
683 reg [`LM32_EID_RNG] eid_w; // Exception ID in W stage
684 `endif
686 `ifdef CFG_DEBUG_ENABLED
687 `ifdef LM32_SINGLE_STEP_ENABLED
688 wire dc_ss; // Is single-step enabled
689 `endif
690 wire dc_re; // Remap all exceptions
691 wire exception_x; // An exception occured in the X stage
692 reg exception_m; // An instruction that caused an exception is in the M stage
693 wire debug_exception_x; // Indicates if a debug exception has occured
694 reg debug_exception_m;
695 reg debug_exception_w;
696 wire debug_exception_q_w;
697 wire non_debug_exception_x; // Indicates if a non debug exception has occured
698 reg non_debug_exception_m;
699 reg non_debug_exception_w;
700 wire non_debug_exception_q_w;
701 `else
702 wire exception_x; // Indicates if a debug exception has occured
703 reg exception_m;
704 reg exception_w;
705 wire exception_q_w;
706 `endif
708 `ifdef CFG_DEBUG_ENABLED
709 `ifdef CFG_JTAG_ENABLED
710 wire reset_exception; // Indicates if a reset exception has occured
711 `endif
712 `endif
713 `ifdef CFG_INTERRUPTS_ENABLED
714 wire interrupt_exception; // Indicates if an interrupt exception has occured
715 `endif
716 `ifdef CFG_DEBUG_ENABLED
717 wire breakpoint_exception; // Indicates if a breakpoint exception has occured
718 wire watchpoint_exception; // Indicates if a watchpoint exception has occured
719 `endif
720 `ifdef CFG_BUS_ERRORS_ENABLED
721 wire instruction_bus_error_exception; // Indicates if an instruction bus error exception has occured
722 wire data_bus_error_exception; // Indicates if a data bus error exception has occured
723 `endif
724 `ifdef CFG_MC_DIVIDE_ENABLED
725 wire divide_by_zero_exception; // Indicates if a divide by zero exception has occured
726 `endif
727 wire system_call_exception; // Indicates if a system call exception has occured
729 `ifdef CFG_BUS_ERRORS_ENABLED
730 reg data_bus_error_seen; // Indicates if a data bus error was seen
731 `endif
733 /////////////////////////////////////////////////////
734 // Functions
735 /////////////////////////////////////////////////////
737 `include "lm32_functions.v"
739 /////////////////////////////////////////////////////
740 // Instantiations
741 /////////////////////////////////////////////////////
743 // Instruction unit
744 lm32_instruction_unit #(
745 .associativity (icache_associativity),
746 .sets (icache_sets),
747 .bytes_per_line (icache_bytes_per_line),
748 .base_address (icache_base_address),
749 .limit (icache_limit)
750 ) instruction_unit (
751 // ----- Inputs -------
752 .clk_i (clk_i),
753 .rst_i (rst_i),
754 // From pipeline
755 .stall_a (stall_a),
756 .stall_f (stall_f),
757 .stall_d (stall_d),
758 .stall_x (stall_x),
759 .stall_m (stall_m),
760 .valid_f (valid_f),
761 .valid_d (valid_d),
762 .kill_f (kill_f),
763 .branch_predict_taken_d (branch_predict_taken_d),
764 .branch_predict_address_d (branch_predict_address_d),
765 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
766 .branch_taken_x (branch_taken_x),
767 .branch_target_x (branch_target_x),
768 `endif
769 .exception_m (exception_m),
770 .branch_taken_m (branch_taken_m),
771 .branch_mispredict_taken_m (branch_mispredict_taken_m),
772 .branch_target_m (branch_target_m),
773 `ifdef CFG_ICACHE_ENABLED
774 .iflush (iflush),
775 `endif
776 `ifdef CFG_IROM_ENABLED
777 .irom_store_data_m (irom_store_data_m),
778 .irom_address_xm (irom_address_xm),
779 .irom_we_xm (irom_we_xm),
780 `endif
781 `ifdef CFG_DCACHE_ENABLED
782 .dcache_restart_request (dcache_restart_request),
783 .dcache_refill_request (dcache_refill_request),
784 .dcache_refilling (dcache_refilling),
785 `endif
786 `ifdef CFG_IWB_ENABLED
787 // From Wishbone
788 .i_dat_i (I_DAT_I),
789 .i_ack_i (I_ACK_I),
790 .i_err_i (I_ERR_I),
791 `endif
792 `ifdef CFG_HW_DEBUG_ENABLED
793 .jtag_read_enable (jtag_read_enable),
794 .jtag_write_enable (jtag_write_enable),
795 .jtag_write_data (jtag_write_data),
796 .jtag_address (jtag_address),
797 `endif
798 // ----- Outputs -------
799 // To pipeline
800 .pc_f (pc_f),
801 .pc_d (pc_d),
802 .pc_x (pc_x),
803 .pc_m (pc_m),
804 .pc_w (pc_w),
805 `ifdef CFG_ICACHE_ENABLED
806 .icache_stall_request (icache_stall_request),
807 .icache_restart_request (icache_restart_request),
808 .icache_refill_request (icache_refill_request),
809 .icache_refilling (icache_refilling),
810 `endif
811 `ifdef CFG_IROM_ENABLED
812 .irom_data_m (irom_data_m),
813 `endif
814 `ifdef CFG_IWB_ENABLED
815 // To Wishbone
816 .i_dat_o (I_DAT_O),
817 .i_adr_o (I_ADR_O),
818 .i_cyc_o (I_CYC_O),
819 .i_sel_o (I_SEL_O),
820 .i_stb_o (I_STB_O),
821 .i_we_o (I_WE_O),
822 .i_cti_o (I_CTI_O),
823 .i_lock_o (I_LOCK_O),
824 .i_bte_o (I_BTE_O),
825 `endif
826 `ifdef CFG_HW_DEBUG_ENABLED
827 .jtag_read_data (jtag_read_data),
828 .jtag_access_complete (jtag_access_complete),
829 `endif
830 `ifdef CFG_BUS_ERRORS_ENABLED
831 .bus_error_d (bus_error_d),
832 `endif
833 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
834 .instruction_f (instruction_f),
835 `endif
836 .instruction_d (instruction_d)
837 );
839 // Instruction decoder
840 lm32_decoder decoder (
841 // ----- Inputs -------
842 .instruction (instruction_d),
843 // ----- Outputs -------
844 .d_result_sel_0 (d_result_sel_0_d),
845 .d_result_sel_1 (d_result_sel_1_d),
846 .x_result_sel_csr (x_result_sel_csr_d),
847 `ifdef LM32_MC_ARITHMETIC_ENABLED
848 .x_result_sel_mc_arith (x_result_sel_mc_arith_d),
849 `endif
850 `ifdef LM32_NO_BARREL_SHIFT
851 .x_result_sel_shift (x_result_sel_shift_d),
852 `endif
853 `ifdef CFG_SIGN_EXTEND_ENABLED
854 .x_result_sel_sext (x_result_sel_sext_d),
855 `endif
856 .x_result_sel_logic (x_result_sel_logic_d),
857 `ifdef CFG_USER_ENABLED
858 .x_result_sel_user (x_result_sel_user_d),
859 `endif
860 .x_result_sel_add (x_result_sel_add_d),
861 .m_result_sel_compare (m_result_sel_compare_d),
862 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
863 .m_result_sel_shift (m_result_sel_shift_d),
864 `endif
865 .w_result_sel_load (w_result_sel_load_d),
866 `ifdef CFG_PL_MULTIPLY_ENABLED
867 .w_result_sel_mul (w_result_sel_mul_d),
868 `endif
869 .x_bypass_enable (x_bypass_enable_d),
870 .m_bypass_enable (m_bypass_enable_d),
871 .read_enable_0 (read_enable_0_d),
872 .read_idx_0 (read_idx_0_d),
873 .read_enable_1 (read_enable_1_d),
874 .read_idx_1 (read_idx_1_d),
875 .write_enable (write_enable_d),
876 .write_idx (write_idx_d),
877 .immediate (immediate_d),
878 .branch_offset (branch_offset_d),
879 .load (load_d),
880 .store (store_d),
881 .size (size_d),
882 .sign_extend (sign_extend_d),
883 .adder_op (adder_op_d),
884 .logic_op (logic_op_d),
885 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
886 .direction (direction_d),
887 `endif
888 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
889 .shift_left (shift_left_d),
890 .shift_right (shift_right_d),
891 `endif
892 `ifdef CFG_MC_MULTIPLY_ENABLED
893 .multiply (multiply_d),
894 `endif
895 `ifdef CFG_MC_DIVIDE_ENABLED
896 .divide (divide_d),
897 .modulus (modulus_d),
898 `endif
899 .branch (branch_d),
900 .bi_unconditional (bi_unconditional),
901 .bi_conditional (bi_conditional),
902 .branch_reg (branch_reg_d),
903 .condition (condition_d),
904 `ifdef CFG_DEBUG_ENABLED
905 .break_opcode (break_d),
906 `endif
907 .scall (scall_d),
908 .eret (eret_d),
909 `ifdef CFG_DEBUG_ENABLED
910 .bret (bret_d),
911 `endif
912 `ifdef CFG_USER_ENABLED
913 .user_opcode (user_opcode_d),
914 `endif
915 .csr_write_enable (csr_write_enable_d)
916 );
918 // Load/store unit
919 lm32_load_store_unit #(
920 .associativity (dcache_associativity),
921 .sets (dcache_sets),
922 .bytes_per_line (dcache_bytes_per_line),
923 .base_address (dcache_base_address),
924 .limit (dcache_limit)
925 ) load_store_unit (
926 // ----- Inputs -------
927 .clk_i (clk_i),
928 .rst_i (rst_i),
929 // From pipeline
930 .stall_a (stall_a),
931 .stall_x (stall_x),
932 .stall_m (stall_m),
933 .kill_m (kill_m),
934 .exception_m (exception_m),
935 .store_operand_x (store_operand_x),
936 .load_store_address_x (adder_result_x),
937 .load_store_address_m (operand_m),
938 .load_store_address_w (operand_w[1:0]),
939 .load_x (load_x),
940 .store_x (store_x),
941 .load_q_x (load_q_x),
942 .store_q_x (store_q_x),
943 .load_q_m (load_q_m),
944 .store_q_m (store_q_m),
945 .sign_extend_x (sign_extend_x),
946 .size_x (size_x),
947 `ifdef CFG_DCACHE_ENABLED
948 .dflush (dflush_m),
949 `endif
950 `ifdef CFG_IROM_ENABLED
951 .irom_data_m (irom_data_m),
952 `endif
953 // From Wishbone
954 .d_dat_i (D_DAT_I),
955 .d_ack_i (D_ACK_I),
956 .d_err_i (D_ERR_I),
957 .d_rty_i (D_RTY_I),
958 // ----- Outputs -------
959 // To pipeline
960 `ifdef CFG_DCACHE_ENABLED
961 .dcache_refill_request (dcache_refill_request),
962 .dcache_restart_request (dcache_restart_request),
963 .dcache_stall_request (dcache_stall_request),
964 .dcache_refilling (dcache_refilling),
965 `endif
966 `ifdef CFG_IROM_ENABLED
967 .irom_store_data_m (irom_store_data_m),
968 .irom_address_xm (irom_address_xm),
969 .irom_we_xm (irom_we_xm),
970 .irom_stall_request_x (irom_stall_request_x),
971 `endif
972 .load_data_w (load_data_w),
973 .stall_wb_load (stall_wb_load),
974 // To Wishbone
975 .d_dat_o (D_DAT_O),
976 .d_adr_o (D_ADR_O),
977 .d_cyc_o (D_CYC_O),
978 .d_sel_o (D_SEL_O),
979 .d_stb_o (D_STB_O),
980 .d_we_o (D_WE_O),
981 .d_cti_o (D_CTI_O),
982 .d_lock_o (D_LOCK_O),
983 .d_bte_o (D_BTE_O)
984 );
986 // Adder
987 lm32_adder adder (
988 // ----- Inputs -------
989 .adder_op_x (adder_op_x),
990 .adder_op_x_n (adder_op_x_n),
991 .operand_0_x (operand_0_x),
992 .operand_1_x (operand_1_x),
993 // ----- Outputs -------
994 .adder_result_x (adder_result_x),
995 .adder_carry_n_x (adder_carry_n_x),
996 .adder_overflow_x (adder_overflow_x)
997 );
999 // Logic operations
1000 lm32_logic_op logic_op (
1001 // ----- Inputs -------
1002 .logic_op_x (logic_op_x),
1003 .operand_0_x (operand_0_x),
1005 .operand_1_x (operand_1_x),
1006 // ----- Outputs -------
1007 .logic_result_x (logic_result_x)
1008 );
1010 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
1011 // Pipelined barrel-shifter
1012 lm32_shifter shifter (
1013 // ----- Inputs -------
1014 .clk_i (clk_i),
1015 .rst_i (rst_i),
1016 .stall_x (stall_x),
1017 .direction_x (direction_x),
1018 .sign_extend_x (sign_extend_x),
1019 .operand_0_x (operand_0_x),
1020 .operand_1_x (operand_1_x),
1021 // ----- Outputs -------
1022 .shifter_result_m (shifter_result_m)
1023 );
1024 `endif
1026 `ifdef CFG_PL_MULTIPLY_ENABLED
1027 // Pipeline fixed-point multiplier
1028 lm32_multiplier multiplier (
1029 // ----- Inputs -------
1030 .clk_i (clk_i),
1031 .rst_i (rst_i),
1032 .stall_x (stall_x),
1033 .stall_m (stall_m),
1034 .operand_0 (d_result_0),
1035 .operand_1 (d_result_1),
1036 // ----- Outputs -------
1037 .result (multiplier_result_w)
1038 );
1039 `endif
1041 `ifdef LM32_MC_ARITHMETIC_ENABLED
1042 // Multi-cycle arithmetic
1043 lm32_mc_arithmetic mc_arithmetic (
1044 // ----- Inputs -------
1045 .clk_i (clk_i),
1046 .rst_i (rst_i),
1047 .stall_d (stall_d),
1048 .kill_x (kill_x),
1049 `ifdef CFG_MC_DIVIDE_ENABLED
1050 .divide_d (divide_q_d),
1051 .modulus_d (modulus_q_d),
1052 `endif
1053 `ifdef CFG_MC_MULTIPLY_ENABLED
1054 .multiply_d (multiply_q_d),
1055 `endif
1056 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
1057 .shift_left_d (shift_left_q_d),
1058 .shift_right_d (shift_right_q_d),
1059 .sign_extend_d (sign_extend_d),
1060 `endif
1061 .operand_0_d (d_result_0),
1062 .operand_1_d (d_result_1),
1063 // ----- Outputs -------
1064 .result_x (mc_result_x),
1065 `ifdef CFG_MC_DIVIDE_ENABLED
1066 .divide_by_zero_x (divide_by_zero_x),
1067 `endif
1068 .stall_request_x (mc_stall_request_x)
1069 );
1070 `endif
1072 `ifdef CFG_INTERRUPTS_ENABLED
1073 // Interrupt unit
1074 lm32_interrupt interrupt (
1075 // ----- Inputs -------
1076 .clk_i (clk_i),
1077 .rst_i (rst_i),
1078 // From external devices
1079 .interrupt_n (interrupt_n),
1080 // From pipeline
1081 .stall_x (stall_x),
1082 `ifdef CFG_DEBUG_ENABLED
1083 .non_debug_exception (non_debug_exception_q_w),
1084 .debug_exception (debug_exception_q_w),
1085 `else
1086 .exception (exception_q_w),
1087 `endif
1088 .eret_q_x (eret_q_x),
1089 `ifdef CFG_DEBUG_ENABLED
1090 .bret_q_x (bret_q_x),
1091 `endif
1092 .csr (csr_x),
1093 .csr_write_data (operand_1_x),
1094 .csr_write_enable (csr_write_enable_q_x),
1095 // ----- Outputs -------
1096 .interrupt_exception (interrupt_exception),
1097 // To pipeline
1098 .csr_read_data (interrupt_csr_read_data_x)
1099 );
1100 `endif
1102 `ifdef CFG_JTAG_ENABLED
1103 // JTAG interface
1104 lm32_jtag jtag (
1105 // ----- Inputs -------
1106 .clk_i (clk_i),
1107 .rst_i (rst_i),
1108 // From JTAG
1109 .jtag_clk (jtag_clk),
1110 .jtag_update (jtag_update),
1111 .jtag_reg_q (jtag_reg_q),
1112 .jtag_reg_addr_q (jtag_reg_addr_q),
1113 // From pipeline
1114 `ifdef CFG_JTAG_UART_ENABLED
1115 .csr (csr_x),
1116 .csr_write_data (operand_1_x),
1117 .csr_write_enable (csr_write_enable_q_x),
1118 .stall_x (stall_x),
1119 `endif
1120 `ifdef CFG_HW_DEBUG_ENABLED
1121 .jtag_read_data (jtag_read_data),
1122 .jtag_access_complete (jtag_access_complete),
1123 `endif
1124 `ifdef CFG_DEBUG_ENABLED
1125 .exception_q_w (debug_exception_q_w || non_debug_exception_q_w),
1126 `endif
1127 // ----- Outputs -------
1128 // To pipeline
1129 `ifdef CFG_JTAG_UART_ENABLED
1130 .jtx_csr_read_data (jtx_csr_read_data),
1131 .jrx_csr_read_data (jrx_csr_read_data),
1132 `endif
1133 `ifdef CFG_HW_DEBUG_ENABLED
1134 .jtag_csr_write_enable (jtag_csr_write_enable),
1135 .jtag_csr_write_data (jtag_csr_write_data),
1136 .jtag_csr (jtag_csr),
1137 .jtag_read_enable (jtag_read_enable),
1138 .jtag_write_enable (jtag_write_enable),
1139 .jtag_write_data (jtag_write_data),
1140 .jtag_address (jtag_address),
1141 `endif
1142 `ifdef CFG_DEBUG_ENABLED
1143 .jtag_break (jtag_break),
1144 .jtag_reset (reset_exception),
1145 `endif
1146 // To JTAG
1147 .jtag_reg_d (jtag_reg_d),
1148 .jtag_reg_addr_d (jtag_reg_addr_d)
1149 );
1150 `endif
1152 `ifdef CFG_DEBUG_ENABLED
1153 // Debug unit
1154 lm32_debug #(
1155 .breakpoints (breakpoints),
1156 .watchpoints (watchpoints)
1157 ) hw_debug (
1158 // ----- Inputs -------
1159 .clk_i (clk_i),
1160 .rst_i (rst_i),
1161 .pc_x (pc_x),
1162 .load_x (load_x),
1163 .store_x (store_x),
1164 .load_store_address_x (adder_result_x),
1165 .csr_write_enable_x (csr_write_enable_q_x),
1166 .csr_write_data (operand_1_x),
1167 .csr_x (csr_x),
1168 `ifdef CFG_HW_DEBUG_ENABLED
1169 .jtag_csr_write_enable (jtag_csr_write_enable),
1170 .jtag_csr_write_data (jtag_csr_write_data),
1171 .jtag_csr (jtag_csr),
1172 `endif
1173 `ifdef LM32_SINGLE_STEP_ENABLED
1174 .eret_q_x (eret_q_x),
1175 .bret_q_x (bret_q_x),
1176 .stall_x (stall_x),
1177 .exception_x (exception_x),
1178 .q_x (q_x),
1179 `ifdef CFG_DCACHE_ENABLED
1180 .dcache_refill_request (dcache_refill_request),
1181 `endif
1182 `endif
1183 // ----- Outputs -------
1184 `ifdef LM32_SINGLE_STEP_ENABLED
1185 .dc_ss (dc_ss),
1186 `endif
1187 .dc_re (dc_re),
1188 .bp_match (bp_match),
1189 .wp_match (wp_match)
1190 );
1191 `endif
1193 // Register file
1195 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
1196 /*----------------------------------------------------------------------
1197 Register File is implemented using EBRs. There can be three accesses to
1198 the register file in each cycle: two reads and one write. On-chip block
1199 RAM has two read/write ports. To accomodate three accesses, two on-chip
1200 block RAMs are used (each register file "write" is made to both block
1201 RAMs).
1203 One limitation of the on-chip block RAMs is that one cannot perform a
1204 read and write to same location in a cycle (if this is done, then the
1205 data read out is indeterminate).
1206 ----------------------------------------------------------------------*/
1207 wire [31:0] regfile_data_0, regfile_data_1;
1208 reg [31:0] w_result_d;
1209 reg regfile_raw_0, regfile_raw_0_nxt;
1210 reg regfile_raw_1, regfile_raw_1_nxt;
1212 /*----------------------------------------------------------------------
1213 Check if read and write is being performed to same register in current
1214 cycle? This is done by comparing the read and write IDXs.
1215 ----------------------------------------------------------------------*/
1216 always @(reg_write_enable_q_w or write_idx_w or instruction_f)
1217 begin
1218 if (reg_write_enable_q_w
1219 && (write_idx_w == instruction_f[25:21]))
1220 regfile_raw_0_nxt = 1'b1;
1221 else
1222 regfile_raw_0_nxt = 1'b0;
1224 if (reg_write_enable_q_w
1225 && (write_idx_w == instruction_f[20:16]))
1226 regfile_raw_1_nxt = 1'b1;
1227 else
1228 regfile_raw_1_nxt = 1'b0;
1229 end
1231 /*----------------------------------------------------------------------
1232 Select latched (delayed) write value or data from register file. If
1233 read in previous cycle was performed to register written to in same
1234 cycle, then latched (delayed) write value is selected.
1235 ----------------------------------------------------------------------*/
1236 always @(regfile_raw_0 or w_result_d or regfile_data_0)
1237 if (regfile_raw_0)
1238 reg_data_live_0 = w_result_d;
1239 else
1240 reg_data_live_0 = regfile_data_0;
1242 /*----------------------------------------------------------------------
1243 Select latched (delayed) write value or data from register file. If
1244 read in previous cycle was performed to register written to in same
1245 cycle, then latched (delayed) write value is selected.
1246 ----------------------------------------------------------------------*/
1247 always @(regfile_raw_1 or w_result_d or regfile_data_1)
1248 if (regfile_raw_1)
1249 reg_data_live_1 = w_result_d;
1250 else
1251 reg_data_live_1 = regfile_data_1;
1253 /*----------------------------------------------------------------------
1254 Latch value written to register file
1255 ----------------------------------------------------------------------*/
1256 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
1257 if (rst_i == `TRUE)
1258 begin
1259 regfile_raw_0 <= 1'b0;
1260 regfile_raw_1 <= 1'b0;
1261 w_result_d <= 32'b0;
1262 end
1263 else
1264 begin
1265 regfile_raw_0 <= regfile_raw_0_nxt;
1266 regfile_raw_1 <= regfile_raw_1_nxt;
1267 w_result_d <= w_result;
1268 end
1270 /*----------------------------------------------------------------------
1271 Register file instantiation as Pseudo-Dual Port EBRs.
1272 ----------------------------------------------------------------------*/
1273 pmi_ram_dp
1274 #(
1275 // ----- Parameters -----
1276 .pmi_wr_addr_depth(1<<5),
1277 .pmi_wr_addr_width(5),
1278 .pmi_wr_data_width(32),
1279 .pmi_rd_addr_depth(1<<5),
1280 .pmi_rd_addr_width(5),
1281 .pmi_rd_data_width(32),
1282 .pmi_regmode("noreg"),
1283 .pmi_gsr("enable"),
1284 .pmi_resetmode("sync"),
1285 .pmi_init_file("none"),
1286 .pmi_init_file_format("binary"),
1287 .pmi_family(`LATTICE_FAMILY),
1288 .module_type("pmi_ram_dp")
1289 )
1290 reg_0
1291 (
1292 // ----- Inputs -----
1293 .Data(w_result),
1294 .WrAddress(write_idx_w),
1295 .RdAddress(instruction_f[25:21]),
1296 .WrClock(clk_i),
1297 .RdClock(clk_i),
1298 .WrClockEn(`TRUE),
1299 .RdClockEn(`TRUE),
1300 .WE(reg_write_enable_q_w),
1301 .Reset(rst_i),
1302 // ----- Outputs -----
1303 .Q(regfile_data_0)
1304 );
1306 pmi_ram_dp
1307 #(
1308 // ----- Parameters -----
1309 .pmi_wr_addr_depth(1<<5),
1310 .pmi_wr_addr_width(5),
1311 .pmi_wr_data_width(32),
1312 .pmi_rd_addr_depth(1<<5),
1313 .pmi_rd_addr_width(5),
1314 .pmi_rd_data_width(32),
1315 .pmi_regmode("noreg"),
1316 .pmi_gsr("enable"),
1317 .pmi_resetmode("sync"),
1318 .pmi_init_file("none"),
1319 .pmi_init_file_format("binary"),
1320 .pmi_family(`LATTICE_FAMILY),
1321 .module_type("pmi_ram_dp")
1322 )
1323 reg_1
1324 (
1325 // ----- Inputs -----
1326 .Data(w_result),
1327 .WrAddress(write_idx_w),
1328 .RdAddress(instruction_f[20:16]),
1329 .WrClock(clk_i),
1330 .RdClock(clk_i),
1331 .WrClockEn(`TRUE),
1332 .RdClockEn(`TRUE),
1333 .WE(reg_write_enable_q_w),
1334 .Reset(rst_i),
1335 // ----- Outputs -----
1336 .Q(regfile_data_1)
1337 );
1338 `endif
1340 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
1341 pmi_ram_dp
1342 #(
1343 // ----- Parameters -----
1344 .pmi_wr_addr_depth(1<<5),
1345 .pmi_wr_addr_width(5),
1346 .pmi_wr_data_width(32),
1347 .pmi_rd_addr_depth(1<<5),
1348 .pmi_rd_addr_width(5),
1349 .pmi_rd_data_width(32),
1350 .pmi_regmode("noreg"),
1351 .pmi_gsr("enable"),
1352 .pmi_resetmode("sync"),
1353 .pmi_init_file("none"),
1354 .pmi_init_file_format("binary"),
1355 .pmi_family(`LATTICE_FAMILY),
1356 .module_type("pmi_ram_dp")
1357 )
1358 reg_0
1359 (
1360 // ----- Inputs -----
1361 .Data(w_result),
1362 .WrAddress(write_idx_w),
1363 .RdAddress(read_idx_0_d),
1364 .WrClock(clk_i),
1365 .RdClock(clk_n_i),
1366 .WrClockEn(`TRUE),
1367 .RdClockEn(stall_f == `FALSE),
1368 .WE(reg_write_enable_q_w),
1369 .Reset(rst_i),
1370 // ----- Outputs -----
1371 .Q(reg_data_0)
1372 );
1374 pmi_ram_dp
1375 #(
1376 // ----- Parameters -----
1377 .pmi_wr_addr_depth(1<<5),
1378 .pmi_wr_addr_width(5),
1379 .pmi_wr_data_width(32),
1380 .pmi_rd_addr_depth(1<<5),
1381 .pmi_rd_addr_width(5),
1382 .pmi_rd_data_width(32),
1383 .pmi_regmode("noreg"),
1384 .pmi_gsr("enable"),
1385 .pmi_resetmode("sync"),
1386 .pmi_init_file("none"),
1387 .pmi_init_file_format("binary"),
1388 .pmi_family(`LATTICE_FAMILY),
1389 .module_type("pmi_ram_dp")
1390 )
1391 reg_1
1392 (
1393 // ----- Inputs -----
1394 .Data(w_result),
1395 .WrAddress(write_idx_w),
1396 .RdAddress(read_idx_1_d),
1397 .WrClock(clk_i),
1398 .RdClock(clk_n_i),
1399 .WrClockEn(`TRUE),
1400 .RdClockEn(stall_f == `FALSE),
1401 .WE(reg_write_enable_q_w),
1402 .Reset(rst_i),
1403 // ----- Outputs -----
1404 .Q(reg_data_1)
1405 );
1406 `endif
1409 /////////////////////////////////////////////////////
1410 // Combinational Logic
1411 /////////////////////////////////////////////////////
1413 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
1414 // Select between buffered and live data from register file
1415 assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
1416 assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
1417 `endif
1418 `ifdef LM32_EBR_REGISTER_FILE
1419 `else
1420 // Register file read ports
1421 assign reg_data_0 = registers[read_idx_0_d];
1422 assign reg_data_1 = registers[read_idx_1_d];
1423 `endif
1425 // Detect read-after-write hazzards
1426 assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == `TRUE);
1427 assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == `TRUE);
1428 assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == `TRUE);
1429 assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == `TRUE);
1430 assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == `TRUE);
1431 assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == `TRUE);
1433 // Interlock detection - Raise an interlock for RAW hazzards
1434 always @(*)
1435 begin
1436 if ( ( (x_bypass_enable_x == `FALSE)
1437 && ( ((read_enable_0_d == `TRUE) && (raw_x_0 == `TRUE))
1438 || ((read_enable_1_d == `TRUE) && (raw_x_1 == `TRUE))
1439 )
1440 )
1441 || ( (m_bypass_enable_m == `FALSE)
1442 && ( ((read_enable_0_d == `TRUE) && (raw_m_0 == `TRUE))
1443 || ((read_enable_1_d == `TRUE) && (raw_m_1 == `TRUE))
1444 )
1445 )
1446 )
1447 interlock = `TRUE;
1448 else
1449 interlock = `FALSE;
1450 end
1452 // Bypass for reg port 0
1453 always @(*)
1454 begin
1455 if (raw_x_0 == `TRUE)
1456 bypass_data_0 = x_result;
1457 else if (raw_m_0 == `TRUE)
1458 bypass_data_0 = m_result;
1459 else if (raw_w_0 == `TRUE)
1460 bypass_data_0 = w_result;
1461 else
1462 bypass_data_0 = reg_data_0;
1463 end
1465 // Bypass for reg port 1
1466 always @(*)
1467 begin
1468 if (raw_x_1 == `TRUE)
1469 bypass_data_1 = x_result;
1470 else if (raw_m_1 == `TRUE)
1471 bypass_data_1 = m_result;
1472 else if (raw_w_1 == `TRUE)
1473 bypass_data_1 = w_result;
1474 else
1475 bypass_data_1 = reg_data_1;
1476 end
1478 /*----------------------------------------------------------------------
1479 Branch prediction is performed in D stage of pipeline. Only PC-relative
1480 branches are predicted: forward-pointing conditional branches are not-
1481 taken, while backward-pointing conditional branches are taken.
1482 Unconditional branches are always predicted taken!
1483 ----------------------------------------------------------------------*/
1484 assign branch_predict_d = bi_unconditional | bi_conditional;
1485 assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
1487 // Compute branch target address: Branch PC PLUS Offset
1488 assign branch_target_d = pc_d + branch_offset_d;
1490 // Compute fetch address. Address of instruction sequentially after the
1491 // branch if branch is not taken. Target address of branch is branch is
1492 // taken
1493 assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
1495 // D stage result selection
1496 always @(*)
1497 begin
1498 d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0;
1499 case (d_result_sel_1_d)
1500 `LM32_D_RESULT_SEL_1_ZERO: d_result_1 = {`LM32_WORD_WIDTH{1'b0}};
1501 `LM32_D_RESULT_SEL_1_REG_1: d_result_1 = bypass_data_1;
1502 `LM32_D_RESULT_SEL_1_IMMEDIATE: d_result_1 = immediate_d;
1503 default: d_result_1 = {`LM32_WORD_WIDTH{1'bx}};
1504 endcase
1505 end
1507 `ifdef CFG_USER_ENABLED
1508 // Operands for user-defined instructions
1509 assign user_operand_0 = operand_0_x;
1510 assign user_operand_1 = operand_1_x;
1511 `endif
1513 `ifdef CFG_SIGN_EXTEND_ENABLED
1514 // Sign-extension
1515 assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
1516 assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
1517 assign sext_result_x = size_x == `LM32_SIZE_BYTE ? sextb_result_x : sexth_result_x;
1518 `endif
1520 `ifdef LM32_NO_BARREL_SHIFT
1521 // Only single bit shift operations are supported when barrel-shifter isn't implemented
1522 assign shifter_result_x = {operand_0_x[`LM32_WORD_WIDTH-1] & sign_extend_x, operand_0_x[`LM32_WORD_WIDTH-1:1]};
1523 `endif
1525 // Condition evaluation
1526 assign cmp_zero = operand_0_x == operand_1_x;
1527 assign cmp_negative = adder_result_x[`LM32_WORD_WIDTH-1];
1528 assign cmp_overflow = adder_overflow_x;
1529 assign cmp_carry_n = adder_carry_n_x;
1530 always @(*)
1531 begin
1532 case (condition_x)
1533 `LM32_CONDITION_U1: condition_met_x = `TRUE;
1534 `LM32_CONDITION_U2: condition_met_x = `TRUE;
1535 `LM32_CONDITION_E: condition_met_x = cmp_zero;
1536 `LM32_CONDITION_NE: condition_met_x = !cmp_zero;
1537 `LM32_CONDITION_G: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
1538 `LM32_CONDITION_GU: condition_met_x = cmp_carry_n && !cmp_zero;
1539 `LM32_CONDITION_GE: condition_met_x = cmp_negative == cmp_overflow;
1540 `LM32_CONDITION_GEU: condition_met_x = cmp_carry_n;
1541 default: condition_met_x = 1'bx;
1542 endcase
1543 end
1545 // X stage result selection
1546 always @(*)
1547 begin
1548 x_result = x_result_sel_add_x ? adder_result_x
1549 : x_result_sel_csr_x ? csr_read_data_x
1550 `ifdef CFG_SIGN_EXTEND_ENABLED
1551 : x_result_sel_sext_x ? sext_result_x
1552 `endif
1553 `ifdef CFG_USER_ENABLED
1554 : x_result_sel_user_x ? user_result
1555 `endif
1556 `ifdef LM32_NO_BARREL_SHIFT
1557 : x_result_sel_shift_x ? shifter_result_x
1558 `endif
1559 `ifdef LM32_MC_ARITHMETIC_ENABLED
1560 : x_result_sel_mc_arith_x ? mc_result_x
1561 `endif
1562 : logic_result_x;
1563 end
1565 // M stage result selection
1566 always @(*)
1567 begin
1568 m_result = m_result_sel_compare_m ? {{`LM32_WORD_WIDTH-1{1'b0}}, condition_met_m}
1569 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
1570 : m_result_sel_shift_m ? shifter_result_m
1571 `endif
1572 : operand_m;
1573 end
1575 // W stage result selection
1576 always @(*)
1577 begin
1578 w_result = w_result_sel_load_w ? load_data_w
1579 `ifdef CFG_PL_MULTIPLY_ENABLED
1580 : w_result_sel_mul_w ? multiplier_result_w
1581 `endif
1582 : operand_w;
1583 end
1585 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
1586 // Indicate when a branch should be taken in X stage
1587 assign branch_taken_x = (stall_x == `FALSE)
1588 && ( (branch_x == `TRUE)
1589 && ((condition_x == `LM32_CONDITION_U1) || (condition_x == `LM32_CONDITION_U2))
1590 && (valid_x == `TRUE)
1591 && (branch_predict_x == `FALSE)
1592 );
1593 `endif
1595 // Indicate when a branch should be taken in M stage (exceptions are a type of branch)
1596 assign branch_taken_m = (stall_m == `FALSE)
1597 && ( ( (branch_m == `TRUE)
1598 && (valid_m == `TRUE)
1599 && ( ( (condition_met_m == `TRUE)
1600 && (branch_predict_taken_m == `FALSE)
1601 )
1602 || ( (condition_met_m == `FALSE)
1603 && (branch_predict_m == `TRUE)
1604 && (branch_predict_taken_m == `TRUE)
1605 )
1606 )
1607 )
1608 || (exception_m == `TRUE)
1609 );
1611 // Indicate when a branch in M stage is mispredicted as being taken
1612 assign branch_mispredict_taken_m = (condition_met_m == `FALSE)
1613 && (branch_predict_m == `TRUE)
1614 && (branch_predict_taken_m == `TRUE);
1616 // Indicate when a branch in M stage will cause flush in X stage
1617 assign branch_flushX_m = (stall_m == `FALSE)
1618 && ( ( (branch_m == `TRUE)
1619 && (valid_m == `TRUE)
1620 && ( (condition_met_m == `TRUE)
1621 || ( (condition_met_m == `FALSE)
1622 && (branch_predict_m == `TRUE)
1623 && (branch_predict_taken_m == `TRUE)
1624 )
1625 )
1626 )
1627 || (exception_m == `TRUE)
1628 );
1630 // Generate signal that will kill instructions in each pipeline stage when necessary
1631 assign kill_f = ( (valid_d == `TRUE)
1632 && (branch_predict_taken_d == `TRUE)
1633 )
1634 || (branch_taken_m == `TRUE)
1635 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
1636 || (branch_taken_x == `TRUE)
1637 `endif
1638 `ifdef CFG_ICACHE_ENABLED
1639 || (icache_refill_request == `TRUE)
1640 `endif
1641 `ifdef CFG_DCACHE_ENABLED
1642 || (dcache_refill_request == `TRUE)
1643 `endif
1644 ;
1645 assign kill_d = (branch_taken_m == `TRUE)
1646 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
1647 || (branch_taken_x == `TRUE)
1648 `endif
1649 `ifdef CFG_ICACHE_ENABLED
1650 || (icache_refill_request == `TRUE)
1651 `endif
1652 `ifdef CFG_DCACHE_ENABLED
1653 || (dcache_refill_request == `TRUE)
1654 `endif
1655 ;
1656 assign kill_x = (branch_flushX_m == `TRUE)
1657 `ifdef CFG_DCACHE_ENABLED
1658 || (dcache_refill_request == `TRUE)
1659 `endif
1660 ;
1661 assign kill_m = `FALSE
1662 `ifdef CFG_DCACHE_ENABLED
1663 || (dcache_refill_request == `TRUE)
1664 `endif
1665 ;
1666 assign kill_w = `FALSE
1667 `ifdef CFG_DCACHE_ENABLED
1668 || (dcache_refill_request == `TRUE)
1669 `endif
1670 ;
1672 // Exceptions
1674 `ifdef CFG_DEBUG_ENABLED
1675 assign breakpoint_exception = ( ( (break_x == `TRUE)
1676 || (bp_match == `TRUE)
1677 )
1678 && (valid_x == `TRUE)
1679 )
1680 `ifdef CFG_JTAG_ENABLED
1681 || (jtag_break == `TRUE)
1682 `endif
1683 ;
1684 `endif
1686 `ifdef CFG_DEBUG_ENABLED
1687 assign watchpoint_exception = wp_match == `TRUE;
1688 `endif
1690 `ifdef CFG_BUS_ERRORS_ENABLED
1691 assign instruction_bus_error_exception = ( (bus_error_x == `TRUE)
1692 && (valid_x == `TRUE)
1693 );
1694 assign data_bus_error_exception = data_bus_error_seen == `TRUE;
1695 `endif
1697 `ifdef CFG_MC_DIVIDE_ENABLED
1698 assign divide_by_zero_exception = divide_by_zero_x == `TRUE;
1699 `endif
1701 assign system_call_exception = ( (scall_x == `TRUE)
1702 `ifdef CFG_BUS_ERRORS_ENABLED
1703 && (valid_x == `TRUE)
1704 `endif
1705 );
1707 `ifdef CFG_DEBUG_ENABLED
1708 assign debug_exception_x = (breakpoint_exception == `TRUE)
1709 || (watchpoint_exception == `TRUE)
1710 ;
1712 assign non_debug_exception_x = (system_call_exception == `TRUE)
1713 `ifdef CFG_JTAG_ENABLED
1714 || (reset_exception == `TRUE)
1715 `endif
1716 `ifdef CFG_BUS_ERRORS_ENABLED
1717 || (instruction_bus_error_exception == `TRUE)
1718 || (data_bus_error_exception == `TRUE)
1719 `endif
1720 `ifdef CFG_MC_DIVIDE_ENABLED
1721 || (divide_by_zero_exception == `TRUE)
1722 `endif
1723 `ifdef CFG_INTERRUPTS_ENABLED
1724 || ( (interrupt_exception == `TRUE)
1725 `ifdef LM32_SINGLE_STEP_ENABLED
1726 && (dc_ss == `FALSE)
1727 `endif
1728 `ifdef CFG_BUS_ERRORS_ENABLED
1729 && (store_q_m == `FALSE)
1730 && (D_CYC_O == `FALSE)
1731 `endif
1732 )
1733 `endif
1734 ;
1736 assign exception_x = (debug_exception_x == `TRUE) || (non_debug_exception_x == `TRUE);
1737 `else
1738 assign exception_x = (system_call_exception == `TRUE)
1739 `ifdef CFG_BUS_ERRORS_ENABLED
1740 || (instruction_bus_error_exception == `TRUE)
1741 || (data_bus_error_exception == `TRUE)
1742 `endif
1743 `ifdef CFG_MC_DIVIDE_ENABLED
1744 || (divide_by_zero_exception == `TRUE)
1745 `endif
1746 `ifdef CFG_INTERRUPTS_ENABLED
1747 || ( (interrupt_exception == `TRUE)
1748 `ifdef LM32_SINGLE_STEP_ENABLED
1749 && (dc_ss == `FALSE)
1750 `endif
1751 `ifdef CFG_BUS_ERRORS_ENABLED
1752 && (store_q_m == `FALSE)
1753 && (D_CYC_O == `FALSE)
1754 `endif
1755 )
1756 `endif
1757 ;
1758 `endif
1760 // Exception ID
1761 always @(*)
1762 begin
1763 `ifdef CFG_DEBUG_ENABLED
1764 `ifdef CFG_JTAG_ENABLED
1765 if (reset_exception == `TRUE)
1766 eid_x = `LM32_EID_RESET;
1767 else
1768 `endif
1769 `ifdef CFG_BUS_ERRORS_ENABLED
1770 if (data_bus_error_exception == `TRUE)
1771 eid_x = `LM32_EID_DATA_BUS_ERROR;
1772 else
1773 `endif
1774 if (breakpoint_exception == `TRUE)
1775 eid_x = `LM32_EID_BREAKPOINT;
1776 else
1777 `endif
1778 `ifdef CFG_BUS_ERRORS_ENABLED
1779 if (data_bus_error_exception == `TRUE)
1780 eid_x = `LM32_EID_DATA_BUS_ERROR;
1781 else
1782 if (instruction_bus_error_exception == `TRUE)
1783 eid_x = `LM32_EID_INST_BUS_ERROR;
1784 else
1785 `endif
1786 `ifdef CFG_DEBUG_ENABLED
1787 if (watchpoint_exception == `TRUE)
1788 eid_x = `LM32_EID_WATCHPOINT;
1789 else
1790 `endif
1791 `ifdef CFG_MC_DIVIDE_ENABLED
1792 if (divide_by_zero_exception == `TRUE)
1793 eid_x = `LM32_EID_DIVIDE_BY_ZERO;
1794 else
1795 `endif
1796 `ifdef CFG_INTERRUPTS_ENABLED
1797 if ( (interrupt_exception == `TRUE)
1798 `ifdef LM32_SINGLE_STEP_ENABLED
1799 && (dc_ss == `FALSE)
1800 `endif
1801 )
1802 eid_x = `LM32_EID_INTERRUPT;
1803 else
1804 `endif
1805 eid_x = `LM32_EID_SCALL;
1806 end
1808 // Stall generation
1810 assign stall_a = (stall_f == `TRUE);
1812 assign stall_f = (stall_d == `TRUE);
1814 assign stall_d = (stall_x == `TRUE)
1815 || ( (interlock == `TRUE)
1816 && (kill_d == `FALSE)
1817 )
1818 || ( ( (eret_d == `TRUE)
1819 || (scall_d == `TRUE)
1820 || (bus_error_d == `TRUE)
1821 )
1822 && ( (load_q_x == `TRUE)
1823 || (load_q_m == `TRUE)
1824 || (store_q_x == `TRUE)
1825 || (store_q_m == `TRUE)
1826 || (D_CYC_O == `TRUE)
1827 )
1828 && (kill_d == `FALSE)
1829 )
1830 `ifdef CFG_DEBUG_ENABLED
1831 || ( ( (break_d == `TRUE)
1832 || (bret_d == `TRUE)
1833 )
1834 && ( (load_q_x == `TRUE)
1835 || (store_q_x == `TRUE)
1836 || (load_q_m == `TRUE)
1837 || (store_q_m == `TRUE)
1838 || (D_CYC_O == `TRUE)
1839 )
1840 && (kill_d == `FALSE)
1841 )
1842 `endif
1843 || ( (csr_write_enable_d == `TRUE)
1844 && (load_q_x == `TRUE)
1845 )
1846 ;
1848 assign stall_x = (stall_m == `TRUE)
1849 `ifdef LM32_MC_ARITHMETIC_ENABLED
1850 || ( (mc_stall_request_x == `TRUE)
1851 && (kill_x == `FALSE)
1852 )
1853 `endif
1854 `ifdef CFG_IROM_ENABLED
1855 // Stall load/store instruction in D stage if there is an ongoing store
1856 // operation to instruction ROM in M stage
1857 || ( (irom_stall_request_x == `TRUE)
1858 && ( (load_d == `TRUE)
1859 || (store_d == `TRUE)
1860 )
1861 )
1862 `endif
1863 ;
1865 assign stall_m = (stall_wb_load == `TRUE)
1866 `ifdef CFG_SIZE_OVER_SPEED
1867 || (D_CYC_O == `TRUE)
1868 `else
1869 || ( (D_CYC_O == `TRUE)
1870 && ( (store_m == `TRUE)
1871 /*
1872 Bug: Following loop does not allow interrupts to be services since
1873 either D_CYC_O or store_m is always high during entire duration of
1874 loop.
1875 L1: addi r1, r1, 1
1876 sw (r2,0), r1
1877 bi L1
1879 Introduce a single-cycle stall when a wishbone cycle is in progress
1880 and a new store instruction is in Execute stage and a interrupt
1881 exception has occured. This stall will ensure that D_CYC_O and
1882 store_m will both be low for one cycle.
1883 */
1884 || ((store_x == `TRUE) && (interrupt_exception == `TRUE))
1885 || (load_m == `TRUE)
1886 || (load_x == `TRUE)
1887 )
1888 )
1889 `endif
1890 `ifdef CFG_DCACHE_ENABLED
1891 || (dcache_stall_request == `TRUE) // Need to stall in case a taken branch is in M stage and data cache is only being flush, so wont be restarted
1892 `endif
1893 `ifdef CFG_ICACHE_ENABLED
1894 || (icache_stall_request == `TRUE) // Pipeline needs to be stalled otherwise branches may be lost
1895 || ((I_CYC_O == `TRUE) && ((branch_m == `TRUE) || (exception_m == `TRUE)))
1896 `else
1897 `ifdef CFG_IWB_ENABLED
1898 || (I_CYC_O == `TRUE)
1899 `endif
1900 `endif
1901 `ifdef CFG_USER_ENABLED
1902 || ( (user_valid == `TRUE) // Stall whole pipeline, rather than just X stage, where the instruction is, so we don't have to worry about exceptions (maybe)
1903 && (user_complete == `FALSE)
1904 )
1905 `endif
1906 ;
1908 // Qualify state changing control signals
1909 `ifdef LM32_MC_ARITHMETIC_ENABLED
1910 assign q_d = (valid_d == `TRUE) && (kill_d == `FALSE);
1911 `endif
1912 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
1913 assign shift_left_q_d = (shift_left_d == `TRUE) && (q_d == `TRUE);
1914 assign shift_right_q_d = (shift_right_d == `TRUE) && (q_d == `TRUE);
1915 `endif
1916 `ifdef CFG_MC_MULTIPLY_ENABLED
1917 assign multiply_q_d = (multiply_d == `TRUE) && (q_d == `TRUE);
1918 `endif
1919 `ifdef CFG_MC_DIVIDE_ENABLED
1920 assign divide_q_d = (divide_d == `TRUE) && (q_d == `TRUE);
1921 assign modulus_q_d = (modulus_d == `TRUE) && (q_d == `TRUE);
1922 `endif
1923 assign q_x = (valid_x == `TRUE) && (kill_x == `FALSE);
1924 assign csr_write_enable_q_x = (csr_write_enable_x == `TRUE) && (q_x == `TRUE);
1925 assign eret_q_x = (eret_x == `TRUE) && (q_x == `TRUE);
1926 `ifdef CFG_DEBUG_ENABLED
1927 assign bret_q_x = (bret_x == `TRUE) && (q_x == `TRUE);
1928 `endif
1929 assign load_q_x = (load_x == `TRUE)
1930 && (q_x == `TRUE)
1931 `ifdef CFG_DEBUG_ENABLED
1932 && (bp_match == `FALSE)
1933 `endif
1934 ;
1935 assign store_q_x = (store_x == `TRUE)
1936 && (q_x == `TRUE)
1937 `ifdef CFG_DEBUG_ENABLED
1938 && (bp_match == `FALSE)
1939 `endif
1940 ;
1941 `ifdef CFG_USER_ENABLED
1942 assign user_valid = (x_result_sel_user_x == `TRUE) && (q_x == `TRUE);
1943 `endif
1944 assign q_m = (valid_m == `TRUE) && (kill_m == `FALSE) && (exception_m == `FALSE);
1945 assign load_q_m = (load_m == `TRUE) && (q_m == `TRUE);
1946 assign store_q_m = (store_m == `TRUE) && (q_m == `TRUE);
1947 `ifdef CFG_DEBUG_ENABLED
1948 assign debug_exception_q_w = ((debug_exception_w == `TRUE) && (valid_w == `TRUE));
1949 assign non_debug_exception_q_w = ((non_debug_exception_w == `TRUE) && (valid_w == `TRUE));
1950 `else
1951 assign exception_q_w = ((exception_w == `TRUE) && (valid_w == `TRUE));
1952 `endif
1953 // Don't qualify register write enables with kill, as the signal is needed early, and it doesn't matter if the instruction is killed (except for the actual write - but that is handled separately)
1954 assign write_enable_q_x = (write_enable_x == `TRUE) && (valid_x == `TRUE) && (branch_flushX_m == `FALSE);
1955 assign write_enable_q_m = (write_enable_m == `TRUE) && (valid_m == `TRUE);
1956 assign write_enable_q_w = (write_enable_w == `TRUE) && (valid_w == `TRUE);
1957 // The enable that actually does write the registers needs to be qualified with kill
1958 assign reg_write_enable_q_w = (write_enable_w == `TRUE) && (kill_w == `FALSE) && (valid_w == `TRUE);
1960 // Configuration (CFG) CSR
1961 assign cfg = {
1962 `LM32_REVISION,
1963 watchpoints[3:0],
1964 breakpoints[3:0],
1965 interrupts[5:0],
1966 `ifdef CFG_JTAG_UART_ENABLED
1967 `TRUE,
1968 `else
1969 `FALSE,
1970 `endif
1971 `ifdef CFG_ROM_DEBUG_ENABLED
1972 `TRUE,
1973 `else
1974 `FALSE,
1975 `endif
1976 `ifdef CFG_HW_DEBUG_ENABLED
1977 `TRUE,
1978 `else
1979 `FALSE,
1980 `endif
1981 `ifdef CFG_DEBUG_ENABLED
1982 `TRUE,
1983 `else
1984 `FALSE,
1985 `endif
1986 `ifdef CFG_ICACHE_ENABLED
1987 `TRUE,
1988 `else
1989 `FALSE,
1990 `endif
1991 `ifdef CFG_DCACHE_ENABLED
1992 `TRUE,
1993 `else
1994 `FALSE,
1995 `endif
1996 `ifdef CFG_CYCLE_COUNTER_ENABLED
1997 `TRUE,
1998 `else
1999 `FALSE,
2000 `endif
2001 `ifdef CFG_USER_ENABLED
2002 `TRUE,
2003 `else
2004 `FALSE,
2005 `endif
2006 `ifdef CFG_SIGN_EXTEND_ENABLED
2007 `TRUE,
2008 `else
2009 `FALSE,
2010 `endif
2011 `ifdef LM32_BARREL_SHIFT_ENABLED
2012 `TRUE,
2013 `else
2014 `FALSE,
2015 `endif
2016 `ifdef CFG_MC_DIVIDE_ENABLED
2017 `TRUE,
2018 `else
2019 `FALSE,
2020 `endif
2021 `ifdef LM32_MULTIPLY_ENABLED
2022 `TRUE
2023 `else
2024 `FALSE
2025 `endif
2026 };
2028 assign cfg2 = {
2029 30'b0,
2030 `ifdef CFG_IROM_ENABLED
2031 `TRUE,
2032 `else
2033 `FALSE,
2034 `endif
2035 `ifdef CFG_DRAM_ENABLED
2036 `TRUE
2037 `else
2038 `FALSE
2039 `endif
2040 };
2042 // Cache flush
2043 `ifdef CFG_ICACHE_ENABLED
2044 assign iflush = (csr_write_enable_d == `TRUE)
2045 && (csr_d == `LM32_CSR_ICC)
2046 && (stall_d == `FALSE)
2047 && (kill_d == `FALSE)
2048 && (valid_d == `TRUE);
2049 `endif
2050 `ifdef CFG_DCACHE_ENABLED
2051 assign dflush_x = (csr_write_enable_q_x == `TRUE)
2052 && (csr_x == `LM32_CSR_DCC);
2053 `endif
2055 // Extract CSR index
2056 assign csr_d = read_idx_0_d[`LM32_CSR_RNG];
2058 // CSR reads
2059 always @(*)
2060 begin
2061 case (csr_x)
2062 `ifdef CFG_INTERRUPTS_ENABLED
2063 `LM32_CSR_IE,
2064 `LM32_CSR_IM,
2065 `LM32_CSR_IP: csr_read_data_x = interrupt_csr_read_data_x;
2066 `endif
2067 `ifdef CFG_CYCLE_COUNTER_ENABLED
2068 `LM32_CSR_CC: csr_read_data_x = cc;
2069 `endif
2070 `LM32_CSR_CFG: csr_read_data_x = cfg;
2071 `LM32_CSR_EBA: csr_read_data_x = {eba, 8'h00};
2072 `ifdef CFG_DEBUG_ENABLED
2073 `LM32_CSR_DEBA: csr_read_data_x = {deba, 8'h00};
2074 `endif
2075 `ifdef CFG_JTAG_UART_ENABLED
2076 `LM32_CSR_JTX: csr_read_data_x = jtx_csr_read_data;
2077 `LM32_CSR_JRX: csr_read_data_x = jrx_csr_read_data;
2078 `endif
2079 `LM32_CSR_CFG2: csr_read_data_x = cfg2;
2081 default: csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
2082 endcase
2083 end
2085 /////////////////////////////////////////////////////
2086 // Sequential Logic
2087 /////////////////////////////////////////////////////
2089 // Exception Base Address (EBA) CSR
2090 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2091 begin
2092 if (rst_i == `TRUE)
2093 eba <= eba_reset[`LM32_PC_WIDTH+2-1:8];
2094 else
2095 begin
2096 if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE))
2097 eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
2098 `ifdef CFG_HW_DEBUG_ENABLED
2099 if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA))
2100 eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
2101 `endif
2102 end
2103 end
2105 `ifdef CFG_DEBUG_ENABLED
2106 // Debug Exception Base Address (DEBA) CSR
2107 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2108 begin
2109 if (rst_i == `TRUE)
2110 deba <= deba_reset[`LM32_PC_WIDTH+2-1:8];
2111 else
2112 begin
2113 if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE))
2114 deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
2115 `ifdef CFG_HW_DEBUG_ENABLED
2116 if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA))
2117 deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
2118 `endif
2119 end
2120 end
2121 `endif
2123 // Cycle Counter (CC) CSR
2124 `ifdef CFG_CYCLE_COUNTER_ENABLED
2125 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2126 begin
2127 if (rst_i == `TRUE)
2128 cc <= {`LM32_WORD_WIDTH{1'b0}};
2129 else
2130 cc <= cc + 1'b1;
2131 end
2132 `endif
2134 `ifdef CFG_BUS_ERRORS_ENABLED
2135 // Watch for data bus errors
2136 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2137 begin
2138 if (rst_i == `TRUE)
2139 data_bus_error_seen <= `FALSE;
2140 else
2141 begin
2142 // Set flag when bus error is detected
2143 if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE))
2144 data_bus_error_seen <= `TRUE;
2145 // Clear flag when exception is taken
2146 if ((exception_m == `TRUE) && (kill_m == `FALSE))
2147 data_bus_error_seen <= `FALSE;
2148 end
2149 end
2150 `endif
2152 // Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not
2154 `ifdef CFG_ICACHE_ENABLED
2155 `ifdef CFG_DCACHE_ENABLED
2156 always @(*)
2157 begin
2158 if ( (icache_refill_request == `TRUE)
2159 || (dcache_refill_request == `TRUE)
2160 )
2161 valid_a = `FALSE;
2162 else if ( (icache_restart_request == `TRUE)
2163 || (dcache_restart_request == `TRUE)
2164 )
2165 valid_a = `TRUE;
2166 else
2167 valid_a = !icache_refilling && !dcache_refilling;
2168 end
2169 `else
2170 always @(*)
2171 begin
2172 if (icache_refill_request == `TRUE)
2173 valid_a = `FALSE;
2174 else if (icache_restart_request == `TRUE)
2175 valid_a = `TRUE;
2176 else
2177 valid_a = !icache_refilling;
2178 end
2179 `endif
2180 `else
2181 `ifdef CFG_DCACHE_ENABLED
2182 always @(*)
2183 begin
2184 if (dcache_refill_request == `TRUE)
2185 valid_a = `FALSE;
2186 else if (dcache_restart_request == `TRUE)
2187 valid_a = `TRUE;
2188 else
2189 valid_a = !dcache_refilling;
2190 end
2191 `endif
2192 `endif
2194 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2195 begin
2196 if (rst_i == `TRUE)
2197 begin
2198 valid_f <= `FALSE;
2199 valid_d <= `FALSE;
2200 valid_x <= `FALSE;
2201 valid_m <= `FALSE;
2202 valid_w <= `FALSE;
2203 end
2204 else
2205 begin
2206 if ((kill_f == `TRUE) || (stall_a == `FALSE))
2207 `ifdef LM32_CACHE_ENABLED
2208 valid_f <= valid_a;
2209 `else
2210 valid_f <= `TRUE;
2211 `endif
2212 else if (stall_f == `FALSE)
2213 valid_f <= `FALSE;
2215 if (kill_d == `TRUE)
2216 valid_d <= `FALSE;
2217 else if (stall_f == `FALSE)
2218 valid_d <= valid_f & !kill_f;
2219 else if (stall_d == `FALSE)
2220 valid_d <= `FALSE;
2222 if (stall_d == `FALSE)
2223 valid_x <= valid_d & !kill_d;
2224 else if (kill_x == `TRUE)
2225 valid_x <= `FALSE;
2226 else if (stall_x == `FALSE)
2227 valid_x <= `FALSE;
2229 if (kill_m == `TRUE)
2230 valid_m <= `FALSE;
2231 else if (stall_x == `FALSE)
2232 valid_m <= valid_x & !kill_x;
2233 else if (stall_m == `FALSE)
2234 valid_m <= `FALSE;
2236 if (stall_m == `FALSE)
2237 valid_w <= valid_m & !kill_m;
2238 else
2239 valid_w <= `FALSE;
2240 end
2241 end
2243 // Microcode pipeline registers
2244 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2245 begin
2246 if (rst_i == `TRUE)
2247 begin
2248 `ifdef CFG_USER_ENABLED
2249 user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}};
2250 `endif
2251 operand_0_x <= {`LM32_WORD_WIDTH{1'b0}};
2252 operand_1_x <= {`LM32_WORD_WIDTH{1'b0}};
2253 store_operand_x <= {`LM32_WORD_WIDTH{1'b0}};
2254 branch_target_x <= {`LM32_WORD_WIDTH{1'b0}};
2255 x_result_sel_csr_x <= `FALSE;
2256 `ifdef LM32_MC_ARITHMETIC_ENABLED
2257 x_result_sel_mc_arith_x <= `FALSE;
2258 `endif
2259 `ifdef LM32_NO_BARREL_SHIFT
2260 x_result_sel_shift_x <= `FALSE;
2261 `endif
2262 `ifdef CFG_SIGN_EXTEND_ENABLED
2263 x_result_sel_sext_x <= `FALSE;
2264 `endif
2265 x_result_sel_logic_x <= `FALSE;
2266 `ifdef CFG_USER_ENABLED
2267 x_result_sel_user_x <= `FALSE;
2268 `endif
2269 x_result_sel_add_x <= `FALSE;
2270 m_result_sel_compare_x <= `FALSE;
2271 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2272 m_result_sel_shift_x <= `FALSE;
2273 `endif
2274 w_result_sel_load_x <= `FALSE;
2275 `ifdef CFG_PL_MULTIPLY_ENABLED
2276 w_result_sel_mul_x <= `FALSE;
2277 `endif
2278 x_bypass_enable_x <= `FALSE;
2279 m_bypass_enable_x <= `FALSE;
2280 write_enable_x <= `FALSE;
2281 write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}};
2282 csr_x <= {`LM32_CSR_WIDTH{1'b0}};
2283 load_x <= `FALSE;
2284 store_x <= `FALSE;
2285 size_x <= {`LM32_SIZE_WIDTH{1'b0}};
2286 sign_extend_x <= `FALSE;
2287 adder_op_x <= `FALSE;
2288 adder_op_x_n <= `FALSE;
2289 logic_op_x <= 4'h0;
2290 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2291 direction_x <= `FALSE;
2292 `endif
2293 `ifdef CFG_ROTATE_ENABLED
2294 rotate_x <= `FALSE;
2296 `endif
2297 branch_x <= `FALSE;
2298 branch_predict_x <= `FALSE;
2299 branch_predict_taken_x <= `FALSE;
2300 condition_x <= `LM32_CONDITION_U1;
2301 `ifdef CFG_DEBUG_ENABLED
2302 break_x <= `FALSE;
2303 `endif
2304 scall_x <= `FALSE;
2305 eret_x <= `FALSE;
2306 `ifdef CFG_DEBUG_ENABLED
2307 bret_x <= `FALSE;
2308 `endif
2309 `ifdef CFG_BUS_ERRORS_ENABLED
2310 bus_error_x <= `FALSE;
2311 data_bus_error_exception_m <= `FALSE;
2312 `endif
2313 csr_write_enable_x <= `FALSE;
2314 operand_m <= {`LM32_WORD_WIDTH{1'b0}};
2315 branch_target_m <= {`LM32_WORD_WIDTH{1'b0}};
2316 m_result_sel_compare_m <= `FALSE;
2317 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2318 m_result_sel_shift_m <= `FALSE;
2319 `endif
2320 w_result_sel_load_m <= `FALSE;
2321 `ifdef CFG_PL_MULTIPLY_ENABLED
2322 w_result_sel_mul_m <= `FALSE;
2323 `endif
2324 m_bypass_enable_m <= `FALSE;
2325 branch_m <= `FALSE;
2326 branch_predict_m <= `FALSE;
2327 branch_predict_taken_m <= `FALSE;
2328 exception_m <= `FALSE;
2329 load_m <= `FALSE;
2330 store_m <= `FALSE;
2331 write_enable_m <= `FALSE;
2332 write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}};
2333 condition_met_m <= `FALSE;
2334 `ifdef CFG_DCACHE_ENABLED
2335 dflush_m <= `FALSE;
2336 `endif
2337 `ifdef CFG_DEBUG_ENABLED
2338 debug_exception_m <= `FALSE;
2339 non_debug_exception_m <= `FALSE;
2340 `endif
2341 operand_w <= {`LM32_WORD_WIDTH{1'b0}};
2342 w_result_sel_load_w <= `FALSE;
2343 `ifdef CFG_PL_MULTIPLY_ENABLED
2344 w_result_sel_mul_w <= `FALSE;
2345 `endif
2346 write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}};
2347 write_enable_w <= `FALSE;
2348 `ifdef CFG_DEBUG_ENABLED
2349 debug_exception_w <= `FALSE;
2350 non_debug_exception_w <= `FALSE;
2351 `else
2352 exception_w <= `FALSE;
2353 `endif
2354 `ifdef CFG_BUS_ERRORS_ENABLED
2355 memop_pc_w <= {`LM32_PC_WIDTH{1'b0}};
2356 `endif
2357 end
2358 else
2359 begin
2360 // D/X stage registers
2362 if (stall_x == `FALSE)
2363 begin
2364 `ifdef CFG_USER_ENABLED
2365 user_opcode <= user_opcode_d;
2366 `endif
2367 operand_0_x <= d_result_0;
2368 operand_1_x <= d_result_1;
2369 store_operand_x <= bypass_data_1;
2370 branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d;
2371 x_result_sel_csr_x <= x_result_sel_csr_d;
2372 `ifdef LM32_MC_ARITHMETIC_ENABLED
2373 x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
2374 `endif
2375 `ifdef LM32_NO_BARREL_SHIFT
2376 x_result_sel_shift_x <= x_result_sel_shift_d;
2377 `endif
2378 `ifdef CFG_SIGN_EXTEND_ENABLED
2379 x_result_sel_sext_x <= x_result_sel_sext_d;
2380 `endif
2381 x_result_sel_logic_x <= x_result_sel_logic_d;
2382 `ifdef CFG_USER_ENABLED
2383 x_result_sel_user_x <= x_result_sel_user_d;
2384 `endif
2385 x_result_sel_add_x <= x_result_sel_add_d;
2386 m_result_sel_compare_x <= m_result_sel_compare_d;
2387 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2388 m_result_sel_shift_x <= m_result_sel_shift_d;
2389 `endif
2390 w_result_sel_load_x <= w_result_sel_load_d;
2391 `ifdef CFG_PL_MULTIPLY_ENABLED
2392 w_result_sel_mul_x <= w_result_sel_mul_d;
2393 `endif
2394 x_bypass_enable_x <= x_bypass_enable_d;
2395 m_bypass_enable_x <= m_bypass_enable_d;
2396 load_x <= load_d;
2397 store_x <= store_d;
2398 branch_x <= branch_d;
2399 branch_predict_x <= branch_predict_d;
2400 branch_predict_taken_x <= branch_predict_taken_d;
2401 write_idx_x <= write_idx_d;
2402 csr_x <= csr_d;
2403 size_x <= size_d;
2404 sign_extend_x <= sign_extend_d;
2405 adder_op_x <= adder_op_d;
2406 adder_op_x_n <= ~adder_op_d;
2407 logic_op_x <= logic_op_d;
2408 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2409 direction_x <= direction_d;
2410 `endif
2411 `ifdef CFG_ROTATE_ENABLED
2412 rotate_x <= rotate_d;
2413 `endif
2414 condition_x <= condition_d;
2415 csr_write_enable_x <= csr_write_enable_d;
2416 `ifdef CFG_DEBUG_ENABLED
2417 break_x <= break_d;
2418 `endif
2419 scall_x <= scall_d;
2420 `ifdef CFG_BUS_ERRORS_ENABLED
2421 bus_error_x <= bus_error_d;
2422 `endif
2423 eret_x <= eret_d;
2424 `ifdef CFG_DEBUG_ENABLED
2425 bret_x <= bret_d;
2426 `endif
2427 write_enable_x <= write_enable_d;
2428 end
2430 // X/M stage registers
2432 if (stall_m == `FALSE)
2433 begin
2434 operand_m <= x_result;
2435 m_result_sel_compare_m <= m_result_sel_compare_x;
2436 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2437 m_result_sel_shift_m <= m_result_sel_shift_x;
2438 `endif
2439 if (exception_x == `TRUE)
2440 begin
2441 w_result_sel_load_m <= `FALSE;
2442 `ifdef CFG_PL_MULTIPLY_ENABLED
2443 w_result_sel_mul_m <= `FALSE;
2444 `endif
2445 end
2446 else
2447 begin
2448 w_result_sel_load_m <= w_result_sel_load_x;
2449 `ifdef CFG_PL_MULTIPLY_ENABLED
2450 w_result_sel_mul_m <= w_result_sel_mul_x;
2451 `endif
2452 end
2453 m_bypass_enable_m <= m_bypass_enable_x;
2454 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2455 `endif
2456 load_m <= load_x;
2457 store_m <= store_x;
2458 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
2459 branch_m <= branch_x && !branch_taken_x;
2460 `else
2461 branch_m <= branch_x;
2462 branch_predict_m <= branch_predict_x;
2463 branch_predict_taken_m <= branch_predict_taken_x;
2464 `endif
2465 `ifdef CFG_DEBUG_ENABLED
2466 // Data bus errors are generated by the wishbone and are
2467 // made known to the processor only in next cycle (as a
2468 // non-debug exception). A break instruction can be seen
2469 // in same cycle (causing a debug exception). Handle non
2470 // -debug exception first!
2471 if (non_debug_exception_x == `TRUE)
2472 write_idx_m <= `LM32_EA_REG;
2473 else if (debug_exception_x == `TRUE)
2474 write_idx_m <= `LM32_BA_REG;
2475 else
2476 write_idx_m <= write_idx_x;
2477 `else
2478 if (exception_x == `TRUE)
2479 write_idx_m <= `LM32_EA_REG;
2480 else
2481 write_idx_m <= write_idx_x;
2482 `endif
2483 condition_met_m <= condition_met_x;
2484 `ifdef CFG_DEBUG_ENABLED
2485 if (exception_x == `TRUE)
2486 if ((dc_re == `TRUE)
2487 || ((debug_exception_x == `TRUE)
2488 && (non_debug_exception_x == `FALSE)))
2489 branch_target_m <= {deba, eid_x, {3{1'b0}}};
2490 else
2491 branch_target_m <= {eba, eid_x, {3{1'b0}}};
2492 else
2493 branch_target_m <= branch_target_x;
2494 `else
2495 branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
2496 `endif
2497 `ifdef CFG_TRACE_ENABLED
2498 eid_m <= eid_x;
2499 `endif
2500 `ifdef CFG_DCACHE_ENABLED
2501 dflush_m <= dflush_x;
2502 `endif
2503 eret_m <= eret_q_x;
2504 `ifdef CFG_DEBUG_ENABLED
2505 bret_m <= bret_q_x;
2506 `endif
2507 write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x;
2508 `ifdef CFG_DEBUG_ENABLED
2509 debug_exception_m <= debug_exception_x;
2510 non_debug_exception_m <= non_debug_exception_x;
2511 `endif
2512 end
2514 // State changing regs
2515 if (stall_m == `FALSE)
2516 begin
2517 if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
2518 exception_m <= `TRUE;
2519 else
2520 exception_m <= `FALSE;
2521 `ifdef CFG_BUS_ERRORS_ENABLED
2522 data_bus_error_exception_m <= (data_bus_error_exception == `TRUE)
2523 `ifdef CFG_DEBUG_ENABLED
2524 && (reset_exception == `FALSE)
2525 `endif
2526 ;
2527 `endif
2528 end
2530 // M/W stage registers
2531 `ifdef CFG_BUS_ERRORS_ENABLED
2532 operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
2533 `else
2534 operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result;
2535 `endif
2536 w_result_sel_load_w <= w_result_sel_load_m;
2537 `ifdef CFG_PL_MULTIPLY_ENABLED
2538 w_result_sel_mul_w <= w_result_sel_mul_m;
2539 `endif
2540 write_idx_w <= write_idx_m;
2541 `ifdef CFG_TRACE_ENABLED
2542 eid_w <= eid_m;
2543 eret_w <= eret_m;
2544 `ifdef CFG_DEBUG_ENABLED
2545 bret_w <= bret_m;
2546 `endif
2547 `endif
2548 write_enable_w <= write_enable_m;
2549 `ifdef CFG_DEBUG_ENABLED
2550 debug_exception_w <= debug_exception_m;
2551 non_debug_exception_w <= non_debug_exception_m;
2552 `else
2553 exception_w <= exception_m;
2554 `endif
2555 `ifdef CFG_BUS_ERRORS_ENABLED
2556 if ( (stall_m == `FALSE)
2557 && ( (load_q_m == `TRUE)
2558 || (store_q_m == `TRUE)
2559 )
2560 )
2561 memop_pc_w <= pc_m;
2562 `endif
2563 end
2564 end
2566 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
2567 // Buffer data read from register file, in case a stall occurs, and watch for
2568 // any writes to the modified registers
2569 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2570 begin
2571 if (rst_i == `TRUE)
2572 begin
2573 use_buf <= `FALSE;
2574 reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}};
2575 reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}};
2576 end
2577 else
2578 begin
2579 if (stall_d == `FALSE)
2580 use_buf <= `FALSE;
2581 else if (use_buf == `FALSE)
2582 begin
2583 reg_data_buf_0 <= reg_data_live_0;
2584 reg_data_buf_1 <= reg_data_live_1;
2585 use_buf <= `TRUE;
2586 end
2587 if (reg_write_enable_q_w == `TRUE)
2588 begin
2589 if (write_idx_w == read_idx_0_d)
2590 reg_data_buf_0 <= w_result;
2591 if (write_idx_w == read_idx_1_d)
2592 reg_data_buf_1 <= w_result;
2593 end
2594 end
2595 end
2596 `endif
2598 `ifdef LM32_EBR_REGISTER_FILE
2599 `else
2600 // Register file write port
2601 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2602 begin
2603 if (rst_i == `TRUE) begin
2604 registers[0] <= {`LM32_WORD_WIDTH{1'b0}};
2605 registers[1] <= {`LM32_WORD_WIDTH{1'b0}};
2606 registers[2] <= {`LM32_WORD_WIDTH{1'b0}};
2607 registers[3] <= {`LM32_WORD_WIDTH{1'b0}};
2608 registers[4] <= {`LM32_WORD_WIDTH{1'b0}};
2609 registers[5] <= {`LM32_WORD_WIDTH{1'b0}};
2610 registers[6] <= {`LM32_WORD_WIDTH{1'b0}};
2611 registers[7] <= {`LM32_WORD_WIDTH{1'b0}};
2612 registers[8] <= {`LM32_WORD_WIDTH{1'b0}};
2613 registers[9] <= {`LM32_WORD_WIDTH{1'b0}};
2614 registers[10] <= {`LM32_WORD_WIDTH{1'b0}};
2615 registers[11] <= {`LM32_WORD_WIDTH{1'b0}};
2616 registers[12] <= {`LM32_WORD_WIDTH{1'b0}};
2617 registers[13] <= {`LM32_WORD_WIDTH{1'b0}};
2618 registers[14] <= {`LM32_WORD_WIDTH{1'b0}};
2619 registers[15] <= {`LM32_WORD_WIDTH{1'b0}};
2620 registers[16] <= {`LM32_WORD_WIDTH{1'b0}};
2621 registers[17] <= {`LM32_WORD_WIDTH{1'b0}};
2622 registers[18] <= {`LM32_WORD_WIDTH{1'b0}};
2623 registers[19] <= {`LM32_WORD_WIDTH{1'b0}};
2624 registers[20] <= {`LM32_WORD_WIDTH{1'b0}};
2625 registers[21] <= {`LM32_WORD_WIDTH{1'b0}};
2626 registers[22] <= {`LM32_WORD_WIDTH{1'b0}};
2627 registers[23] <= {`LM32_WORD_WIDTH{1'b0}};
2628 registers[24] <= {`LM32_WORD_WIDTH{1'b0}};
2629 registers[25] <= {`LM32_WORD_WIDTH{1'b0}};
2630 registers[26] <= {`LM32_WORD_WIDTH{1'b0}};
2631 registers[27] <= {`LM32_WORD_WIDTH{1'b0}};
2632 registers[28] <= {`LM32_WORD_WIDTH{1'b0}};
2633 registers[29] <= {`LM32_WORD_WIDTH{1'b0}};
2634 registers[30] <= {`LM32_WORD_WIDTH{1'b0}};
2635 registers[31] <= {`LM32_WORD_WIDTH{1'b0}};
2636 end
2637 else begin
2638 if (reg_write_enable_q_w == `TRUE)
2639 registers[write_idx_w] <= w_result;
2640 end
2641 end
2642 `endif
2644 `ifdef CFG_TRACE_ENABLED
2645 // PC tracing logic
2646 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2647 begin
2648 if (rst_i == `TRUE)
2649 begin
2650 trace_pc_valid <= `FALSE;
2651 trace_pc <= {`LM32_PC_WIDTH{1'b0}};
2652 trace_exception <= `FALSE;
2653 trace_eid <= `LM32_EID_RESET;
2654 trace_eret <= `FALSE;
2655 `ifdef CFG_DEBUG_ENABLED
2656 trace_bret <= `FALSE;
2657 `endif
2658 pc_c <= `CFG_EBA_RESET/4;
2659 end
2660 else
2661 begin
2662 trace_pc_valid <= `FALSE;
2663 // Has an exception occured
2664 `ifdef CFG_DEBUG_ENABLED
2665 if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE))
2666 `else
2667 if (exception_q_w == `TRUE)
2668 `endif
2669 begin
2670 trace_exception <= `TRUE;
2671 trace_pc_valid <= `TRUE;
2672 trace_pc <= pc_w;
2673 trace_eid <= eid_w;
2674 end
2675 else
2676 trace_exception <= `FALSE;
2678 if ((valid_w == `TRUE) && (!kill_w))
2679 begin
2680 // An instruction is commiting. Determine if it is non-sequential
2681 if (pc_c + 1'b1 != pc_w)
2682 begin
2683 // Non-sequential instruction
2684 trace_pc_valid <= `TRUE;
2685 trace_pc <= pc_w;
2686 end
2687 // Record PC so we can determine if next instruction is sequential or not
2688 pc_c <= pc_w;
2689 // Indicate if it was an eret/bret instruction
2690 trace_eret <= eret_w;
2691 `ifdef CFG_DEBUG_ENABLED
2692 trace_bret <= bret_w;
2693 `endif
2694 end
2695 else
2696 begin
2697 trace_eret <= `FALSE;
2698 `ifdef CFG_DEBUG_ENABLED
2699 trace_bret <= `FALSE;
2700 `endif
2701 end
2702 end
2703 end
2704 `endif
2706 /////////////////////////////////////////////////////
2707 // Behavioural Logic
2708 /////////////////////////////////////////////////////
2710 // synthesis translate_off
2712 // Reset register 0. Only needed for simulation.
2713 initial
2714 begin
2715 `ifdef LM32_EBR_REGISTER_FILE
2716 reg_0.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
2717 reg_1.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
2718 `else
2719 registers[0] = {`LM32_WORD_WIDTH{1'b0}};
2720 `endif
2721 end
2723 // synthesis translate_on
2725 endmodule