Sat, 06 Aug 2011 01:34:41 +0100
Merge LM32 v3.8 docs in
1 // ==================================================================
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4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
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37 // FILE DETAILS
38 // Project : LatticeMico32
39 // File : lm32_dcache.v
40 // Title : Data cache
41 // Dependencies : lm32_include.v
42 // Version : 6.1.17
43 // : Initial Release
44 // Version : 7.0SP2, 3.0
45 // : No Change
46 // Version : 3.1
47 // : Support for user-selected resource usage when implementing
48 // : cache memory. Additional parameters must be defined when
49 // : invoking lm32_ram.v
50 // =============================================================================
52 `include "lm32_include.v"
54 `ifdef CFG_DCACHE_ENABLED
56 `define LM32_DC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb
57 `define LM32_DC_ADDR_SET_RNG addr_set_msb:addr_set_lsb
58 `define LM32_DC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb
59 `define LM32_DC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb
61 `define LM32_DC_TMEM_ADDR_WIDTH addr_set_width
62 `define LM32_DC_TMEM_ADDR_RNG (`LM32_DC_TMEM_ADDR_WIDTH-1):0
63 `define LM32_DC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width)
64 `define LM32_DC_DMEM_ADDR_RNG (`LM32_DC_DMEM_ADDR_WIDTH-1):0
66 `define LM32_DC_TAGS_WIDTH (addr_tag_width+1)
67 `define LM32_DC_TAGS_RNG (`LM32_DC_TAGS_WIDTH-1):0
68 `define LM32_DC_TAGS_TAG_RNG (`LM32_DC_TAGS_WIDTH-1):1
69 `define LM32_DC_TAGS_VALID_RNG 0
71 `define LM32_DC_STATE_RNG 2:0
72 `define LM32_DC_STATE_FLUSH 3'b001
73 `define LM32_DC_STATE_CHECK 3'b010
74 `define LM32_DC_STATE_REFILL 3'b100
76 /////////////////////////////////////////////////////
77 // Module interface
78 /////////////////////////////////////////////////////
80 module lm32_dcache (
81 // ----- Inputs -----
82 clk_i,
83 rst_i,
84 stall_a,
85 stall_x,
86 stall_m,
87 address_x,
88 address_m,
89 load_q_m,
90 store_q_m,
91 store_data,
92 store_byte_select,
93 refill_ready,
94 refill_data,
95 dflush,
96 // ----- Outputs -----
97 stall_request,
98 restart_request,
99 refill_request,
100 refill_address,
101 refilling,
102 load_data
103 );
105 /////////////////////////////////////////////////////
106 // Parameters
107 /////////////////////////////////////////////////////
109 parameter associativity = 1; // Associativity of the cache (Number of ways)
110 parameter sets = 512; // Number of sets
111 parameter bytes_per_line = 16; // Number of bytes per cache line
112 parameter base_address = 0; // Base address of cachable memory
113 parameter limit = 0; // Limit (highest address) of cachable memory
115 localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
116 localparam addr_set_width = clogb2(sets)-1;
117 localparam addr_offset_lsb = 2;
118 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
119 localparam addr_set_lsb = (addr_offset_msb+1);
120 localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
121 localparam addr_tag_lsb = (addr_set_msb+1);
122 localparam addr_tag_msb = clogb2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS)-1;
123 localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
125 /////////////////////////////////////////////////////
126 // Inputs
127 /////////////////////////////////////////////////////
129 input clk_i; // Clock
130 input rst_i; // Reset
132 input stall_a; // Stall A stage
133 input stall_x; // Stall X stage
134 input stall_m; // Stall M stage
136 input [`LM32_WORD_RNG] address_x; // X stage load/store address
137 input [`LM32_WORD_RNG] address_m; // M stage load/store address
138 input load_q_m; // Load instruction in M stage
139 input store_q_m; // Store instruction in M stage
140 input [`LM32_WORD_RNG] store_data; // Data to store
141 input [`LM32_BYTE_SELECT_RNG] store_byte_select; // Which bytes in store data should be modified
143 input refill_ready; // Indicates next word of refill data is ready
144 input [`LM32_WORD_RNG] refill_data; // Refill data
146 input dflush; // Indicates cache should be flushed
148 /////////////////////////////////////////////////////
149 // Outputs
150 /////////////////////////////////////////////////////
152 output stall_request; // Request pipeline be stalled because cache is busy
153 wire stall_request;
154 output restart_request; // Request to restart instruction that caused the cache miss
155 reg restart_request;
156 output refill_request; // Request a refill
157 reg refill_request;
158 output [`LM32_WORD_RNG] refill_address; // Address to refill from
159 reg [`LM32_WORD_RNG] refill_address;
160 output refilling; // Indicates if the cache is currently refilling
161 reg refilling;
162 output [`LM32_WORD_RNG] load_data; // Data read from cache
163 wire [`LM32_WORD_RNG] load_data;
165 /////////////////////////////////////////////////////
166 // Internal nets and registers
167 /////////////////////////////////////////////////////
169 wire read_port_enable; // Cache memory read port clock enable
170 wire write_port_enable; // Cache memory write port clock enable
171 wire [0:associativity-1] way_tmem_we; // Tag memory write enable
172 wire [0:associativity-1] way_dmem_we; // Data memory write enable
173 wire [`LM32_WORD_RNG] way_data[0:associativity-1]; // Data read from data memory
174 wire [`LM32_DC_TAGS_TAG_RNG] way_tag[0:associativity-1];// Tag read from tag memory
175 wire [0:associativity-1] way_valid; // Indicates which ways are valid
176 wire [0:associativity-1] way_match; // Indicates which ways matched
177 wire miss; // Indicates no ways matched
179 wire [`LM32_DC_TMEM_ADDR_RNG] tmem_read_address; // Tag memory read address
180 wire [`LM32_DC_TMEM_ADDR_RNG] tmem_write_address; // Tag memory write address
181 wire [`LM32_DC_DMEM_ADDR_RNG] dmem_read_address; // Data memory read address
182 wire [`LM32_DC_DMEM_ADDR_RNG] dmem_write_address; // Data memory write address
183 wire [`LM32_DC_TAGS_RNG] tmem_write_data; // Tag memory write data
184 reg [`LM32_WORD_RNG] dmem_write_data; // Data memory write data
186 reg [`LM32_DC_STATE_RNG] state; // Current state of FSM
187 wire flushing; // Indicates if cache is currently flushing
188 wire check; // Indicates if cache is currently checking for hits/misses
189 wire refill; // Indicates if cache is currently refilling
191 wire valid_store; // Indicates if there is a valid store instruction
192 reg [associativity-1:0] refill_way_select; // Which way should be refilled
193 reg [`LM32_DC_ADDR_OFFSET_RNG] refill_offset; // Which word in cache line should be refilled
194 wire last_refill; // Indicates when on last cycle of cache refill
195 reg [`LM32_DC_TMEM_ADDR_RNG] flush_set; // Which set is currently being flushed
197 genvar i, j;
199 /////////////////////////////////////////////////////
200 // Functions
201 /////////////////////////////////////////////////////
203 `include "lm32_functions.v"
205 /////////////////////////////////////////////////////
206 // Instantiations
207 /////////////////////////////////////////////////////
209 generate
210 for (i = 0; i < associativity; i = i + 1)
211 begin : memories
212 // Way data
213 if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
214 begin : data_memories
215 lm32_ram
216 #(
217 // ----- Parameters -------
218 .data_width (32),
219 .address_width (`LM32_DC_DMEM_ADDR_WIDTH)
220 `ifdef PLATFORM_LATTICE
221 ,
222 `ifdef CFG_DCACHE_DAT_USE_DP_TRUE
223 .RAM_IMPLEMENTATION ("EBR"),
224 .RAM_TYPE ("RAM_DP_TRUE")
225 `else
226 `ifdef CFG_DCACHE_DAT_USE_SLICE
227 .RAM_IMPLEMENTATION ("SLICE")
228 `else
229 .RAM_IMPLEMENTATION ("AUTO")
230 `endif
231 `endif
232 `endif
233 ) way_0_data_ram
234 (
235 // ----- Inputs -------
236 .read_clk (clk_i),
237 .write_clk (clk_i),
238 .reset (rst_i),
239 .read_address (dmem_read_address),
240 .enable_read (read_port_enable),
241 .write_address (dmem_write_address),
242 .enable_write (write_port_enable),
243 .write_enable (way_dmem_we[i]),
244 .write_data (dmem_write_data),
245 // ----- Outputs -------
246 .read_data (way_data[i])
247 );
248 end
249 else
250 begin
251 for (j = 0; j < 4; j = j + 1)
252 begin : byte_memories
253 lm32_ram
254 #(
255 // ----- Parameters -------
256 .data_width (8),
257 .address_width (`LM32_DC_DMEM_ADDR_WIDTH)
258 `ifdef PLATFORM_LATTICE
259 ,
260 `ifdef CFG_DCACHE_DAT_USE_DP_TRUE
261 .RAM_IMPLEMENTATION ("EBR"),
262 .RAM_TYPE ("RAM_DP_TRUE")
263 `else
264 `ifdef CFG_DCACHE_DAT_USE_SLICE
265 .RAM_IMPLEMENTATION ("SLICE")
266 `else
267 .RAM_IMPLEMENTATION ("AUTO")
268 `endif
269 `endif
270 `endif
271 ) way_0_data_ram
272 (
273 // ----- Inputs -------
274 .read_clk (clk_i),
275 .write_clk (clk_i),
276 .reset (rst_i),
277 .read_address (dmem_read_address),
278 .enable_read (read_port_enable),
279 .write_address (dmem_write_address),
280 .enable_write (write_port_enable),
281 .write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)),
282 .write_data (dmem_write_data[(j+1)*8-1:j*8]),
283 // ----- Outputs -------
284 .read_data (way_data[i][(j+1)*8-1:j*8])
285 );
286 end
287 end
289 // Way tags
290 lm32_ram
291 #(
292 // ----- Parameters -------
293 .data_width (`LM32_DC_TAGS_WIDTH),
294 .address_width (`LM32_DC_TMEM_ADDR_WIDTH)
295 `ifdef PLATFORM_LATTICE
296 ,
297 `ifdef CFG_DCACHE_DAT_USE_DP_TRUE
298 .RAM_IMPLEMENTATION ("EBR"),
299 .RAM_TYPE ("RAM_DP_TRUE")
300 `else
301 `ifdef CFG_DCACHE_DAT_USE_SLICE
302 .RAM_IMPLEMENTATION ("SLICE")
303 `else
304 .RAM_IMPLEMENTATION ("AUTO")
305 `endif
306 `endif
307 `endif
308 ) way_0_tag_ram
309 (
310 // ----- Inputs -------
311 .read_clk (clk_i),
312 .write_clk (clk_i),
313 .reset (rst_i),
314 .read_address (tmem_read_address),
315 .enable_read (read_port_enable),
316 .write_address (tmem_write_address),
317 .enable_write (`TRUE),
318 .write_enable (way_tmem_we[i]),
319 .write_data (tmem_write_data),
320 // ----- Outputs -------
321 .read_data ({way_tag[i], way_valid[i]})
322 );
323 end
325 endgenerate
327 /////////////////////////////////////////////////////
328 // Combinational logic
329 /////////////////////////////////////////////////////
331 // Compute which ways in the cache match the address being read
332 generate
333 for (i = 0; i < associativity; i = i + 1)
334 begin : match
335 assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE});
336 end
337 endgenerate
339 // Select data from way that matched the address being read
340 generate
341 if (associativity == 1)
342 begin : data_1
343 assign load_data = way_data[0];
344 end
345 else if (associativity == 2)
346 begin : data_2
347 assign load_data = way_match[0] ? way_data[0] : way_data[1];
348 end
349 endgenerate
351 generate
352 if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
353 begin
354 // Select data to write to data memories
355 always @(*)
356 begin
357 if (refill == `TRUE)
358 dmem_write_data = refill_data;
359 else
360 begin
361 dmem_write_data[`LM32_BYTE_0_RNG] = store_byte_select[0] ? store_data[`LM32_BYTE_0_RNG] : load_data[`LM32_BYTE_0_RNG];
362 dmem_write_data[`LM32_BYTE_1_RNG] = store_byte_select[1] ? store_data[`LM32_BYTE_1_RNG] : load_data[`LM32_BYTE_1_RNG];
363 dmem_write_data[`LM32_BYTE_2_RNG] = store_byte_select[2] ? store_data[`LM32_BYTE_2_RNG] : load_data[`LM32_BYTE_2_RNG];
364 dmem_write_data[`LM32_BYTE_3_RNG] = store_byte_select[3] ? store_data[`LM32_BYTE_3_RNG] : load_data[`LM32_BYTE_3_RNG];
365 end
366 end
367 end
368 else
369 begin
370 // Select data to write to data memories - FIXME: Should use different write ports on dual port RAMs, but they don't work
371 always @(*)
372 begin
373 if (refill == `TRUE)
374 dmem_write_data = refill_data;
375 else
376 dmem_write_data = store_data;
377 end
378 end
379 endgenerate
381 // Compute address to use to index into the data memories
382 generate
383 if (bytes_per_line > 4)
384 assign dmem_write_address = (refill == `TRUE)
385 ? {refill_address[`LM32_DC_ADDR_SET_RNG], refill_offset}
386 : address_m[`LM32_DC_ADDR_IDX_RNG];
387 else
388 assign dmem_write_address = (refill == `TRUE)
389 ? refill_address[`LM32_DC_ADDR_SET_RNG]
390 : address_m[`LM32_DC_ADDR_IDX_RNG];
391 endgenerate
392 assign dmem_read_address = address_x[`LM32_DC_ADDR_IDX_RNG];
393 // Compute address to use to index into the tag memories
394 assign tmem_write_address = (flushing == `TRUE)
395 ? flush_set
396 : refill_address[`LM32_DC_ADDR_SET_RNG];
397 assign tmem_read_address = address_x[`LM32_DC_ADDR_SET_RNG];
399 // Compute signal to indicate when we are on the last refill accesses
400 generate
401 if (bytes_per_line > 4)
402 assign last_refill = refill_offset == {addr_offset_width{1'b1}};
403 else
404 assign last_refill = `TRUE;
405 endgenerate
407 // Compute data and tag memory access enable
408 assign read_port_enable = (stall_x == `FALSE);
409 assign write_port_enable = (refill_ready == `TRUE) || !stall_m;
411 // Determine when we have a valid store
412 assign valid_store = (store_q_m == `TRUE) && (check == `TRUE);
414 // Compute data and tag memory write enables
415 generate
416 if (associativity == 1)
417 begin : we_1
418 assign way_dmem_we[0] = (refill_ready == `TRUE) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
419 assign way_tmem_we[0] = (refill_ready == `TRUE) || (flushing == `TRUE);
420 end
421 else
422 begin : we_2
423 assign way_dmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
424 assign way_dmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || ((valid_store == `TRUE) && (way_match[1] == `TRUE));
425 assign way_tmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || (flushing == `TRUE);
426 assign way_tmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || (flushing == `TRUE);
427 end
428 endgenerate
430 // On the last refill cycle set the valid bit, for all other writes it should be cleared
431 assign tmem_write_data[`LM32_DC_TAGS_VALID_RNG] = ((last_refill == `TRUE) || (valid_store == `TRUE)) && (flushing == `FALSE);
432 assign tmem_write_data[`LM32_DC_TAGS_TAG_RNG] = refill_address[`LM32_DC_ADDR_TAG_RNG];
434 // Signals that indicate which state we are in
435 assign flushing = state[0];
436 assign check = state[1];
437 assign refill = state[2];
439 assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE);
440 assign stall_request = (check == `FALSE);
442 /////////////////////////////////////////////////////
443 // Sequential logic
444 /////////////////////////////////////////////////////
446 // Record way selected for replacement on a cache miss
447 generate
448 if (associativity >= 2)
449 begin : way_select
450 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
451 begin
452 if (rst_i == `TRUE)
453 refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
454 else
455 begin
456 if (refill_request == `TRUE)
457 refill_way_select <= {refill_way_select[0], refill_way_select[1]};
458 end
459 end
460 end
461 endgenerate
463 // Record whether we are currently refilling
464 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
465 begin
466 if (rst_i == `TRUE)
467 refilling <= `FALSE;
468 else
469 refilling <= refill;
470 end
472 // Instruction cache control FSM
473 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
474 begin
475 if (rst_i == `TRUE)
476 begin
477 state <= `LM32_DC_STATE_FLUSH;
478 flush_set <= {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}};
479 refill_request <= `FALSE;
480 refill_address <= {`LM32_WORD_WIDTH{1'bx}};
481 restart_request <= `FALSE;
482 end
483 else
484 begin
485 case (state)
487 // Flush the cache
488 `LM32_DC_STATE_FLUSH:
489 begin
490 if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}})
491 state <= `LM32_DC_STATE_CHECK;
492 flush_set <= flush_set - 1'b1;
493 end
495 // Check for cache misses
496 `LM32_DC_STATE_CHECK:
497 begin
498 if (stall_a == `FALSE)
499 restart_request <= `FALSE;
500 if (miss == `TRUE)
501 begin
502 refill_request <= `TRUE;
503 refill_address <= address_m;
504 state <= `LM32_DC_STATE_REFILL;
505 end
506 else if (dflush == `TRUE)
507 state <= `LM32_DC_STATE_FLUSH;
508 end
510 // Refill a cache line
511 `LM32_DC_STATE_REFILL:
512 begin
513 refill_request <= `FALSE;
514 if (refill_ready == `TRUE)
515 begin
516 if (last_refill == `TRUE)
517 begin
518 restart_request <= `TRUE;
519 state <= `LM32_DC_STATE_CHECK;
520 end
521 end
522 end
524 endcase
525 end
526 end
528 generate
529 if (bytes_per_line > 4)
530 begin
531 // Refill offset
532 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
533 begin
534 if (rst_i == `TRUE)
535 refill_offset <= {addr_offset_width{1'b0}};
536 else
537 begin
538 case (state)
540 // Check for cache misses
541 `LM32_DC_STATE_CHECK:
542 begin
543 if (miss == `TRUE)
544 refill_offset <= {addr_offset_width{1'b0}};
545 end
547 // Refill a cache line
548 `LM32_DC_STATE_REFILL:
549 begin
550 if (refill_ready == `TRUE)
551 refill_offset <= refill_offset + 1'b1;
552 end
554 endcase
555 end
556 end
557 end
558 endgenerate
560 endmodule
562 `endif