Sat, 06 Aug 2011 01:34:41 +0100
Merge LM32 v3.8 docs in
1 // ==================================================================
2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
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4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
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7 //
8 // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
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36 // --------------------------------------------------------------------
37 // FILE DETAILS
38 // Project : LatticeMico32
39 // File : lm32_icache.v
40 // Title : Instruction cache
41 // Dependencies : lm32_include.v
42 //
43 // Version 3.5
44 // 1. Bug Fix: Instruction cache flushes issued from Instruction Inline Memory
45 // cause segmentation fault due to incorrect fetches.
46 //
47 // Version 3.1
48 // 1. Feature: Support for user-selected resource usage when implementing
49 // cache memory. Additional parameters must be defined when invoking module
50 // lm32_ram. Instruction cache miss mechanism is dependent on branch
51 // prediction being performed in D stage of pipeline.
52 //
53 // Version 7.0SP2, 3.0
54 // No change
55 // =============================================================================
57 `include "lm32_include.v"
59 `ifdef CFG_ICACHE_ENABLED
61 `define LM32_IC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb
62 `define LM32_IC_ADDR_SET_RNG addr_set_msb:addr_set_lsb
63 `define LM32_IC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb
64 `define LM32_IC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb
66 `define LM32_IC_TMEM_ADDR_WIDTH addr_set_width
67 `define LM32_IC_TMEM_ADDR_RNG (`LM32_IC_TMEM_ADDR_WIDTH-1):0
68 `define LM32_IC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width)
69 `define LM32_IC_DMEM_ADDR_RNG (`LM32_IC_DMEM_ADDR_WIDTH-1):0
71 `define LM32_IC_TAGS_WIDTH (addr_tag_width+1)
72 `define LM32_IC_TAGS_RNG (`LM32_IC_TAGS_WIDTH-1):0
73 `define LM32_IC_TAGS_TAG_RNG (`LM32_IC_TAGS_WIDTH-1):1
74 `define LM32_IC_TAGS_VALID_RNG 0
76 `define LM32_IC_STATE_RNG 3:0
77 `define LM32_IC_STATE_FLUSH_INIT 4'b0001
78 `define LM32_IC_STATE_FLUSH 4'b0010
79 `define LM32_IC_STATE_CHECK 4'b0100
80 `define LM32_IC_STATE_REFILL 4'b1000
82 /////////////////////////////////////////////////////
83 // Module interface
84 /////////////////////////////////////////////////////
86 module lm32_icache (
87 // ----- Inputs -----
88 clk_i,
89 rst_i,
90 stall_a,
91 stall_f,
92 address_a,
93 address_f,
94 read_enable_f,
95 refill_ready,
96 refill_data,
97 iflush,
98 `ifdef CFG_IROM_ENABLED
99 select_f,
100 `endif
101 valid_d,
102 branch_predict_taken_d,
103 // ----- Outputs -----
104 stall_request,
105 restart_request,
106 refill_request,
107 refill_address,
108 refilling,
109 inst
110 );
112 /////////////////////////////////////////////////////
113 // Parameters
114 /////////////////////////////////////////////////////
116 parameter associativity = 1; // Associativity of the cache (Number of ways)
117 parameter sets = 512; // Number of sets
118 parameter bytes_per_line = 16; // Number of bytes per cache line
119 parameter base_address = 0; // Base address of cachable memory
120 parameter limit = 0; // Limit (highest address) of cachable memory
122 localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
123 localparam addr_set_width = clogb2(sets)-1;
124 localparam addr_offset_lsb = 2;
125 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
126 localparam addr_set_lsb = (addr_offset_msb+1);
127 localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
128 localparam addr_tag_lsb = (addr_set_msb+1);
129 localparam addr_tag_msb = clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-1;
130 localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
132 /////////////////////////////////////////////////////
133 // Inputs
134 /////////////////////////////////////////////////////
136 input clk_i; // Clock
137 input rst_i; // Reset
139 input stall_a; // Stall instruction in A stage
140 input stall_f; // Stall instruction in F stage
142 input valid_d; // Valid instruction in D stage
143 input branch_predict_taken_d; // Instruction in D stage is a branch and is predicted taken
145 input [`LM32_PC_RNG] address_a; // Address of instruction in A stage
146 input [`LM32_PC_RNG] address_f; // Address of instruction in F stage
147 input read_enable_f; // Indicates if cache access is valid
149 input refill_ready; // Next word of refill data is ready
150 input [`LM32_INSTRUCTION_RNG] refill_data; // Data to refill the cache with
152 input iflush; // Flush the cache
153 `ifdef CFG_IROM_ENABLED
154 input select_f; // Instruction in F stage is mapped through instruction cache
155 `endif
157 /////////////////////////////////////////////////////
158 // Outputs
159 /////////////////////////////////////////////////////
161 output stall_request; // Request to stall the pipeline
162 wire stall_request;
163 output restart_request; // Request to restart instruction that caused the cache miss
164 reg restart_request;
165 output refill_request; // Request to refill a cache line
166 wire refill_request;
167 output [`LM32_PC_RNG] refill_address; // Base address of cache refill
168 reg [`LM32_PC_RNG] refill_address;
169 output refilling; // Indicates the instruction cache is currently refilling
170 reg refilling;
171 output [`LM32_INSTRUCTION_RNG] inst; // Instruction read from cache
172 wire [`LM32_INSTRUCTION_RNG] inst;
174 /////////////////////////////////////////////////////
175 // Internal nets and registers
176 /////////////////////////////////////////////////////
178 wire enable;
179 wire [0:associativity-1] way_mem_we;
180 wire [`LM32_INSTRUCTION_RNG] way_data[0:associativity-1];
181 wire [`LM32_IC_TAGS_TAG_RNG] way_tag[0:associativity-1];
182 wire [0:associativity-1] way_valid;
183 wire [0:associativity-1] way_match;
184 wire miss;
186 wire [`LM32_IC_TMEM_ADDR_RNG] tmem_read_address;
187 wire [`LM32_IC_TMEM_ADDR_RNG] tmem_write_address;
188 wire [`LM32_IC_DMEM_ADDR_RNG] dmem_read_address;
189 wire [`LM32_IC_DMEM_ADDR_RNG] dmem_write_address;
190 wire [`LM32_IC_TAGS_RNG] tmem_write_data;
192 reg [`LM32_IC_STATE_RNG] state;
193 wire flushing;
194 wire check;
195 wire refill;
197 reg [associativity-1:0] refill_way_select;
198 reg [`LM32_IC_ADDR_OFFSET_RNG] refill_offset;
199 wire last_refill;
200 reg [`LM32_IC_TMEM_ADDR_RNG] flush_set;
202 genvar i;
204 /////////////////////////////////////////////////////
205 // Functions
206 /////////////////////////////////////////////////////
208 `include "lm32_functions.v"
210 /////////////////////////////////////////////////////
211 // Instantiations
212 /////////////////////////////////////////////////////
214 generate
215 for (i = 0; i < associativity; i = i + 1)
216 begin : memories
218 lm32_ram
219 #(
220 // ----- Parameters -------
221 .data_width (32),
222 .address_width (`LM32_IC_DMEM_ADDR_WIDTH)
223 `ifdef PLATFORM_LATTICE
224 ,
225 `ifdef CFG_ICACHE_DAT_USE_DP_TRUE
226 .RAM_IMPLEMENTATION ("EBR"),
227 .RAM_TYPE ("RAM_DP_TRUE")
228 `else
229 `ifdef CFG_ICACHE_DAT_USE_DP
230 .RAM_IMPLEMENTATION ("EBR"),
231 .RAM_TYPE ("RAM_DP")
232 `else
233 `ifdef CFG_ICACHE_DAT_USE_SLICE
234 .RAM_IMPLEMENTATION ("SLICE")
235 `else
236 .RAM_IMPLEMENTATION ("AUTO")
237 `endif
238 `endif
239 `endif
240 `endif
241 )
242 way_0_data_ram
243 (
244 // ----- Inputs -------
245 .read_clk (clk_i),
246 .write_clk (clk_i),
247 .reset (rst_i),
248 .read_address (dmem_read_address),
249 .enable_read (enable),
250 .write_address (dmem_write_address),
251 .enable_write (`TRUE),
252 .write_enable (way_mem_we[i]),
253 .write_data (refill_data),
254 // ----- Outputs -------
255 .read_data (way_data[i])
256 );
258 lm32_ram
259 #(
260 // ----- Parameters -------
261 .data_width (`LM32_IC_TAGS_WIDTH),
262 .address_width (`LM32_IC_TMEM_ADDR_WIDTH)
263 `ifdef PLATFORM_LATTICE
264 ,
265 `ifdef CFG_ICACHE_DAT_USE_DP_TRUE
266 .RAM_IMPLEMENTATION ("EBR"),
267 .RAM_TYPE ("RAM_DP_TRUE")
268 `else
269 `ifdef CFG_ICACHE_DAT_USE_DP
270 .RAM_IMPLEMENTATION ("EBR"),
271 .RAM_TYPE ("RAM_DP")
272 `else
273 `ifdef CFG_ICACHE_DAT_USE_SLICE
274 .RAM_IMPLEMENTATION ("SLICE")
275 `else
276 .RAM_IMPLEMENTATION ("AUTO")
277 `endif
278 `endif
279 `endif
280 `endif
281 )
282 way_0_tag_ram
283 (
284 // ----- Inputs -------
285 .read_clk (clk_i),
286 .write_clk (clk_i),
287 .reset (rst_i),
288 .read_address (tmem_read_address),
289 .enable_read (enable),
290 .write_address (tmem_write_address),
291 .enable_write (`TRUE),
292 .write_enable (way_mem_we[i] | flushing),
293 .write_data (tmem_write_data),
294 // ----- Outputs -------
295 .read_data ({way_tag[i], way_valid[i]})
296 );
298 end
299 endgenerate
301 /////////////////////////////////////////////////////
302 // Combinational logic
303 /////////////////////////////////////////////////////
305 // Compute which ways in the cache match the address address being read
306 generate
307 for (i = 0; i < associativity; i = i + 1)
308 begin : match
309 assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE});
310 end
311 endgenerate
313 // Select data from way that matched the address being read
314 generate
315 if (associativity == 1)
316 begin : inst_1
317 assign inst = way_match[0] ? way_data[0] : 32'b0;
318 end
319 else if (associativity == 2)
320 begin : inst_2
321 assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0);
322 end
323 endgenerate
325 // Compute address to use to index into the data memories
326 generate
327 if (bytes_per_line > 4)
328 assign dmem_write_address = {refill_address[`LM32_IC_ADDR_SET_RNG], refill_offset};
329 else
330 assign dmem_write_address = refill_address[`LM32_IC_ADDR_SET_RNG];
331 endgenerate
333 assign dmem_read_address = address_a[`LM32_IC_ADDR_IDX_RNG];
335 // Compute address to use to index into the tag memories
336 assign tmem_read_address = address_a[`LM32_IC_ADDR_SET_RNG];
337 assign tmem_write_address = flushing
338 ? flush_set
339 : refill_address[`LM32_IC_ADDR_SET_RNG];
341 // Compute signal to indicate when we are on the last refill accesses
342 generate
343 if (bytes_per_line > 4)
344 assign last_refill = refill_offset == {addr_offset_width{1'b1}};
345 else
346 assign last_refill = `TRUE;
347 endgenerate
349 // Compute data and tag memory access enable
350 assign enable = (stall_a == `FALSE);
352 // Compute data and tag memory write enables
353 generate
354 if (associativity == 1)
355 begin : we_1
356 assign way_mem_we[0] = (refill_ready == `TRUE);
357 end
358 else
359 begin : we_2
360 assign way_mem_we[0] = (refill_ready == `TRUE) && (refill_way_select[0] == `TRUE);
361 assign way_mem_we[1] = (refill_ready == `TRUE) && (refill_way_select[1] == `TRUE);
362 end
363 endgenerate
365 // On the last refill cycle set the valid bit, for all other writes it should be cleared
366 assign tmem_write_data[`LM32_IC_TAGS_VALID_RNG] = last_refill & !flushing;
367 assign tmem_write_data[`LM32_IC_TAGS_TAG_RNG] = refill_address[`LM32_IC_ADDR_TAG_RNG];
369 // Signals that indicate which state we are in
370 assign flushing = |state[1:0];
371 assign check = state[2];
372 assign refill = state[3];
374 assign miss = (~(|way_match)) && (read_enable_f == `TRUE) && (stall_f == `FALSE) && !(valid_d && branch_predict_taken_d);
375 assign stall_request = (check == `FALSE);
376 assign refill_request = (refill == `TRUE);
378 /////////////////////////////////////////////////////
379 // Sequential logic
380 /////////////////////////////////////////////////////
382 // Record way selected for replacement on a cache miss
383 generate
384 if (associativity >= 2)
385 begin : way_select
386 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
387 begin
388 if (rst_i == `TRUE)
389 refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
390 else
391 begin
392 if (miss == `TRUE)
393 refill_way_select <= {refill_way_select[0], refill_way_select[1]};
394 end
395 end
396 end
397 endgenerate
399 // Record whether we are refilling
400 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
401 begin
402 if (rst_i == `TRUE)
403 refilling <= `FALSE;
404 else
405 refilling <= refill;
406 end
408 // Instruction cache control FSM
409 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
410 begin
411 if (rst_i == `TRUE)
412 begin
413 state <= `LM32_IC_STATE_FLUSH_INIT;
414 flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}};
415 refill_address <= {`LM32_PC_WIDTH{1'bx}};
416 restart_request <= `FALSE;
417 end
418 else
419 begin
420 case (state)
422 // Flush the cache for the first time after reset
423 `LM32_IC_STATE_FLUSH_INIT:
424 begin
425 if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
426 state <= `LM32_IC_STATE_CHECK;
427 flush_set <= flush_set - 1'b1;
428 end
430 // Flush the cache in response to an write to the ICC CSR
431 `LM32_IC_STATE_FLUSH:
432 begin
433 if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
434 `ifdef CFG_IROM_ENABLED
435 if (select_f)
436 state <= `LM32_IC_STATE_REFILL;
437 else
438 `endif
439 state <= `LM32_IC_STATE_CHECK;
441 flush_set <= flush_set - 1'b1;
442 end
444 // Check for cache misses
445 `LM32_IC_STATE_CHECK:
446 begin
447 if (stall_a == `FALSE)
448 restart_request <= `FALSE;
449 if (iflush == `TRUE)
450 begin
451 refill_address <= address_f;
452 state <= `LM32_IC_STATE_FLUSH;
453 end
454 else if (miss == `TRUE)
455 begin
456 refill_address <= address_f;
457 state <= `LM32_IC_STATE_REFILL;
458 end
459 end
461 // Refill a cache line
462 `LM32_IC_STATE_REFILL:
463 begin
464 if (refill_ready == `TRUE)
465 begin
466 if (last_refill == `TRUE)
467 begin
468 restart_request <= `TRUE;
469 state <= `LM32_IC_STATE_CHECK;
470 end
471 end
472 end
474 endcase
475 end
476 end
478 generate
479 if (bytes_per_line > 4)
480 begin
481 // Refill offset
482 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
483 begin
484 if (rst_i == `TRUE)
485 refill_offset <= {addr_offset_width{1'b0}};
486 else
487 begin
488 case (state)
490 // Check for cache misses
491 `LM32_IC_STATE_CHECK:
492 begin
493 if (iflush == `TRUE)
494 refill_offset <= {addr_offset_width{1'b0}};
495 else if (miss == `TRUE)
496 refill_offset <= {addr_offset_width{1'b0}};
497 end
499 // Refill a cache line
500 `LM32_IC_STATE_REFILL:
501 begin
502 if (refill_ready == `TRUE)
503 refill_offset <= refill_offset + 1'b1;
504 end
506 endcase
507 end
508 end
509 end
510 endgenerate
512 endmodule
514 `endif