Sat, 06 Aug 2011 01:34:41 +0100
Merge LM32 v3.8 docs in
1 // ==================================================================
2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
3 // ------------------------------------------------------------------
4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
5 // ALL RIGHTS RESERVED
6 // ------------------------------------------------------------------
7 //
8 // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
9 //
10 // Permission:
11 //
12 // Lattice Semiconductor grants permission to use this code
13 // pursuant to the terms of the Lattice Semiconductor Corporation
14 // Open Source License Agreement.
15 //
16 // Disclaimer:
17 //
18 // Lattice Semiconductor provides no warranty regarding the use or
19 // functionality of this code. It is the user's responsibility to
20 // verify the user’s design for consistency and functionality through
21 // the use of formal verification methods.
22 //
23 // --------------------------------------------------------------------
24 //
25 // Lattice Semiconductor Corporation
26 // 5555 NE Moore Court
27 // Hillsboro, OR 97214
28 // U.S.A
29 //
30 // TEL: 1-800-Lattice (USA and Canada)
31 // 503-286-8001 (other locations)
32 //
33 // web: http://www.latticesemi.com/
34 // email: techsupport@latticesemi.com
35 //
36 // --------------------------------------------------------------------
37 // FILE DETAILS
38 // Project : LatticeMico32
39 // File : lm32_top.v
40 // Title : Top-level of CPU.
41 // Dependencies : lm32_include.v
42 // Version : 6.1.17
43 // : removed SPI - 04/12/07
44 // Version : 7.0SP2, 3.0
45 // : No Change
46 // Version : 3.1
47 // : No Change
48 // =============================================================================
50 `include "lm32_include.v"
52 /////////////////////////////////////////////////////
53 // Module interface
54 /////////////////////////////////////////////////////
56 module lm32_top (
57 // ----- Inputs -------
58 clk_i,
59 rst_i,
60 `ifdef CFG_DEBUG_ENABLED
61 `ifdef CFG_ALTERNATE_EBA
62 at_debug,
63 `endif
64 `endif
65 // From external devices
66 `ifdef CFG_INTERRUPTS_ENABLED
67 interrupt,
68 `endif
69 // From user logic
70 `ifdef CFG_USER_ENABLED
71 user_result,
72 user_complete,
73 `endif
74 `ifdef CFG_IWB_ENABLED
75 // Instruction Wishbone master
76 I_DAT_I,
77 I_ACK_I,
78 I_ERR_I,
79 I_RTY_I,
80 `endif
81 // Data Wishbone master
82 D_DAT_I,
83 D_ACK_I,
84 D_ERR_I,
85 D_RTY_I,
86 // ----- Outputs -------
87 `ifdef CFG_USER_ENABLED
88 user_valid,
89 user_opcode,
90 user_operand_0,
91 user_operand_1,
92 `endif
93 `ifdef CFG_IWB_ENABLED
94 // Instruction Wishbone master
95 I_DAT_O,
96 I_ADR_O,
97 I_CYC_O,
98 I_SEL_O,
99 I_STB_O,
100 I_WE_O,
101 I_CTI_O,
102 I_LOCK_O,
103 I_BTE_O,
104 `endif
105 // Data Wishbone master
106 D_DAT_O,
107 D_ADR_O,
108 D_CYC_O,
109 D_SEL_O,
110 D_STB_O,
111 D_WE_O,
112 D_CTI_O,
113 D_LOCK_O,
114 D_BTE_O
115 );
117 /////////////////////////////////////////////////////
118 // Inputs
119 /////////////////////////////////////////////////////
121 input clk_i; // Clock
122 input rst_i; // Reset
124 `ifdef CFG_DEBUG_ENABLED
125 `ifdef CFG_ALTERNATE_EBA
126 input at_debug; // GPIO input that maps EBA to DEBA
127 `endif
128 `endif
130 `ifdef CFG_INTERRUPTS_ENABLED
131 input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins
132 `endif
134 `ifdef CFG_USER_ENABLED
135 input [`LM32_WORD_RNG] user_result; // User-defined instruction result
136 input user_complete; // Indicates the user-defined instruction result is valid
137 `endif
139 `ifdef CFG_IWB_ENABLED
140 input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data
141 input I_ACK_I; // Instruction Wishbone interface acknowledgement
142 input I_ERR_I; // Instruction Wishbone interface error
143 input I_RTY_I; // Instruction Wishbone interface retry
144 `endif
146 input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
147 input D_ACK_I; // Data Wishbone interface acknowledgement
148 input D_ERR_I; // Data Wishbone interface error
149 input D_RTY_I; // Data Wishbone interface retry
151 /////////////////////////////////////////////////////
152 // Outputs
153 /////////////////////////////////////////////////////
155 `ifdef CFG_USER_ENABLED
156 output user_valid; // Indicates that user_opcode and user_operand_* are valid
157 wire user_valid;
158 output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode
159 reg [`LM32_USER_OPCODE_RNG] user_opcode;
160 output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction
161 wire [`LM32_WORD_RNG] user_operand_0;
162 output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction
163 wire [`LM32_WORD_RNG] user_operand_1;
164 `endif
166 `ifdef CFG_IWB_ENABLED
167 output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data
168 wire [`LM32_WORD_RNG] I_DAT_O;
169 output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address
170 wire [`LM32_WORD_RNG] I_ADR_O;
171 output I_CYC_O; // Instruction Wishbone interface cycle
172 wire I_CYC_O;
173 output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select
174 wire [`LM32_BYTE_SELECT_RNG] I_SEL_O;
175 output I_STB_O; // Instruction Wishbone interface strobe
176 wire I_STB_O;
177 output I_WE_O; // Instruction Wishbone interface write enable
178 wire I_WE_O;
179 output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type
180 wire [`LM32_CTYPE_RNG] I_CTI_O;
181 output I_LOCK_O; // Instruction Wishbone interface lock bus
182 wire I_LOCK_O;
183 output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type
184 wire [`LM32_BTYPE_RNG] I_BTE_O;
185 `endif
187 output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
188 wire [`LM32_WORD_RNG] D_DAT_O;
189 output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
190 wire [`LM32_WORD_RNG] D_ADR_O;
191 output D_CYC_O; // Data Wishbone interface cycle
192 wire D_CYC_O;
193 output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select
194 wire [`LM32_BYTE_SELECT_RNG] D_SEL_O;
195 output D_STB_O; // Data Wishbone interface strobe
196 wire D_STB_O;
197 output D_WE_O; // Data Wishbone interface write enable
198 wire D_WE_O;
199 output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type
200 wire [`LM32_CTYPE_RNG] D_CTI_O;
201 output D_LOCK_O; // Date Wishbone interface lock bus
202 wire D_LOCK_O;
203 output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
204 wire [`LM32_BTYPE_RNG] D_BTE_O;
206 /////////////////////////////////////////////////////
207 // Internal nets and registers
208 /////////////////////////////////////////////////////
210 `ifdef CFG_JTAG_ENABLED
211 // Signals between JTAG interface and CPU
212 wire [`LM32_BYTE_RNG] jtag_reg_d;
213 wire [`LM32_BYTE_RNG] jtag_reg_q;
214 wire jtag_update;
215 wire [2:0] jtag_reg_addr_d;
216 wire [2:0] jtag_reg_addr_q;
217 wire jtck;
218 wire jrstn;
219 `endif
221 // TODO: get the trace signals out
222 `ifdef CFG_TRACE_ENABLED
223 // PC trace signals
224 wire [`LM32_PC_RNG] trace_pc; // PC to trace (address of next non-sequential instruction)
225 wire trace_pc_valid; // Indicates that a new trace PC is valid
226 wire trace_exception; // Indicates an exception has occured
227 wire [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured
228 wire trace_eret; // Indicates an eret instruction has been executed
229 `ifdef CFG_DEBUG_ENABLED
230 wire trace_bret; // Indicates a bret instruction has been executed
231 `endif
232 `endif
234 /////////////////////////////////////////////////////
235 // Functions
236 /////////////////////////////////////////////////////
238 `include "lm32_functions.v"
239 /////////////////////////////////////////////////////
240 // Instantiations
241 /////////////////////////////////////////////////////
243 // LM32 CPU
244 lm32_cpu cpu (
245 // ----- Inputs -------
246 .clk_i (clk_i),
247 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
248 .clk_n_i (clk_n),
249 `endif
250 .rst_i (rst_i),
251 `ifdef CFG_DEBUG_ENABLED
252 `ifdef CFG_ALTERNATE_EBA
253 .at_debug (at_debug),
254 `endif
255 `endif
256 // From external devices
257 `ifdef CFG_INTERRUPTS_ENABLED
258 .interrupt (interrupt),
259 `endif
260 // From user logic
261 `ifdef CFG_USER_ENABLED
262 .user_result (user_result),
263 .user_complete (user_complete),
264 `endif
265 `ifdef CFG_JTAG_ENABLED
266 // From JTAG
267 .jtag_clk (jtck),
268 .jtag_update (jtag_update),
269 .jtag_reg_q (jtag_reg_q),
270 .jtag_reg_addr_q (jtag_reg_addr_q),
271 `endif
272 `ifdef CFG_IWB_ENABLED
273 // Instruction Wishbone master
274 .I_DAT_I (I_DAT_I),
275 .I_ACK_I (I_ACK_I),
276 .I_ERR_I (I_ERR_I),
277 .I_RTY_I (I_RTY_I),
278 `endif
279 // Data Wishbone master
280 .D_DAT_I (D_DAT_I),
281 .D_ACK_I (D_ACK_I),
282 .D_ERR_I (D_ERR_I),
283 .D_RTY_I (D_RTY_I),
284 // ----- Outputs -------
285 `ifdef CFG_TRACE_ENABLED
286 .trace_pc (trace_pc),
287 .trace_pc_valid (trace_pc_valid),
288 .trace_exception (trace_exception),
289 .trace_eid (trace_eid),
290 .trace_eret (trace_eret),
291 `ifdef CFG_DEBUG_ENABLED
292 .trace_bret (trace_bret),
293 `endif
294 `endif
295 `ifdef CFG_JTAG_ENABLED
296 .jtag_reg_d (jtag_reg_d),
297 .jtag_reg_addr_d (jtag_reg_addr_d),
298 `endif
299 `ifdef CFG_USER_ENABLED
300 .user_valid (user_valid),
301 .user_opcode (user_opcode),
302 .user_operand_0 (user_operand_0),
303 .user_operand_1 (user_operand_1),
304 `endif
305 `ifdef CFG_IWB_ENABLED
306 // Instruction Wishbone master
307 .I_DAT_O (I_DAT_O),
308 .I_ADR_O (I_ADR_O),
309 .I_CYC_O (I_CYC_O),
310 .I_SEL_O (I_SEL_O),
311 .I_STB_O (I_STB_O),
312 .I_WE_O (I_WE_O),
313 .I_CTI_O (I_CTI_O),
314 .I_LOCK_O (I_LOCK_O),
315 .I_BTE_O (I_BTE_O),
316 `endif
317 // Data Wishbone master
318 .D_DAT_O (D_DAT_O),
319 .D_ADR_O (D_ADR_O),
320 .D_CYC_O (D_CYC_O),
321 .D_SEL_O (D_SEL_O),
322 .D_STB_O (D_STB_O),
323 .D_WE_O (D_WE_O),
324 .D_CTI_O (D_CTI_O),
325 .D_LOCK_O (D_LOCK_O),
326 .D_BTE_O (D_BTE_O)
327 );
329 wire TRACE_ACK_O;
330 wire [`LM32_WORD_RNG] TRACE_DAT_O;
331 `ifdef CFG_TRACE_ENABLED
332 lm32_trace trace_module (.clk_i (clk_i),
333 .rst_i (rst_i),
334 .stb_i (DEBUG_STB_I & DEBUG_ADR_I[13]),
335 .we_i (DEBUG_WE_I),
336 .sel_i (DEBUG_SEL_I),
337 .dat_i (DEBUG_DAT_I),
338 .adr_i (DEBUG_ADR_I),
339 .trace_pc (trace_pc),
340 .trace_eid (trace_eid),
341 .trace_eret (trace_eret),
342 .trace_bret (trace_bret),
343 .trace_pc_valid (trace_pc_valid),
344 .trace_exception (trace_exception),
345 .ack_o (TRACE_ACK_O),
346 .dat_o (TRACE_DAT_O));
347 `else
348 assign TRACE_ACK_O = 0;
349 assign TRACE_DAT_O = 0;
350 `endif
351 `ifdef DEBUG_ROM
352 wire ROM_ACK_O;
353 wire [`LM32_WORD_RNG] ROM_DAT_O;
355 assign DEBUG_ACK_O = DEBUG_ADR_I[13] ? TRACE_ACK_O : ROM_ACK_O;
356 assign DEBUG_DAT_O = DEBUG_ADR_I[13] ? TRACE_DAT_O : ROM_DAT_O;
358 // ROM monitor
359 lm32_monitor debug_rom (
360 // ----- Inputs -------
361 .clk_i (clk_i),
362 .rst_i (rst_i),
363 .MON_ADR_I (DEBUG_ADR_I[10:2]),
364 .MON_STB_I (DEBUG_STB_I & ~DEBUG_ADR_I[13]),
365 .MON_CYC_I (DEBUG_CYC_I & ~DEBUG_ADR_I[13]),
366 .MON_WE_I (DEBUG_WE_I),
367 .MON_SEL_I (DEBUG_SEL_I),
368 .MON_DAT_I (DEBUG_DAT_I),
369 // ----- Outputs ------
370 .MON_RTY_O (DEBUG_RTY_O),
371 .MON_ERR_O (DEBUG_ERR_O),
372 .MON_ACK_O (ROM_ACK_O),
373 .MON_DAT_O (ROM_DAT_O)
374 );
375 `endif
377 `ifdef CFG_JTAG_ENABLED
378 // JTAG cores
379 jtag_cores jtag_cores (
380 // ----- Inputs -----
381 .reg_d (jtag_reg_d),
382 .reg_addr_d (jtag_reg_addr_d),
383 // ----- Outputs -----
384 .reg_update (jtag_update),
385 .reg_q (jtag_reg_q),
386 .reg_addr_q (jtag_reg_addr_q),
387 .jtck (jtck),
388 .jrstn (jrstn)
389 );
390 `endif
392 endmodule