Sun, 04 Apr 2010 20:52:32 +0100
Disable Lattice-specific stuff by default
To build on Lattice platforms, `define PLATFORM_LATTICE in lm32_include.v.
Otherwise, non-optimal "platform independent" HDL will be used.
This means LM32 can now be built for non-Lattice FPGAs.
1 // =============================================================================
2 // COPYRIGHT NOTICE
3 // Copyright 2006 (c) Lattice Semiconductor Corporation
4 // ALL RIGHTS RESERVED
5 // This confidential and proprietary software may be used only as authorised by
6 // a licensing agreement from Lattice Semiconductor Corporation.
7 // The entire notice above must be reproduced on all authorized copies and
8 // copies may only be made to the extent permitted by a licensing agreement from
9 // Lattice Semiconductor Corporation.
10 //
11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12 // 5555 NE Moore Court 408-826-6000 (other locations)
13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
14 // U.S.A email: techsupport@latticesemi.com
15 // =============================================================================/
16 // FILE DETAILS
17 // Project : LatticeMico32
18 // File : lm32_dcache.v
19 // Title : Data cache
20 // Dependencies : lm32_include.v
21 // Version : 6.1.17
22 // : Initial Release
23 // Version : 7.0SP2, 3.0
24 // : No Change
25 // Version : 3.1
26 // : Support for user-selected resource usage when implementing
27 // : cache memory. Additional parameters must be defined when
28 // : invoking lm32_ram.v
29 // =============================================================================
31 `include "lm32_include.v"
33 `ifdef CFG_DCACHE_ENABLED
35 `define LM32_DC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb
36 `define LM32_DC_ADDR_SET_RNG addr_set_msb:addr_set_lsb
37 `define LM32_DC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb
38 `define LM32_DC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb
40 `define LM32_DC_TMEM_ADDR_WIDTH addr_set_width
41 `define LM32_DC_TMEM_ADDR_RNG (`LM32_DC_TMEM_ADDR_WIDTH-1):0
42 `define LM32_DC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width)
43 `define LM32_DC_DMEM_ADDR_RNG (`LM32_DC_DMEM_ADDR_WIDTH-1):0
45 `define LM32_DC_TAGS_WIDTH (addr_tag_width+1)
46 `define LM32_DC_TAGS_RNG (`LM32_DC_TAGS_WIDTH-1):0
47 `define LM32_DC_TAGS_TAG_RNG (`LM32_DC_TAGS_WIDTH-1):1
48 `define LM32_DC_TAGS_VALID_RNG 0
50 `define LM32_DC_STATE_RNG 2:0
51 `define LM32_DC_STATE_FLUSH 3'b001
52 `define LM32_DC_STATE_CHECK 3'b010
53 `define LM32_DC_STATE_REFILL 3'b100
55 /////////////////////////////////////////////////////
56 // Module interface
57 /////////////////////////////////////////////////////
59 module lm32_dcache (
60 // ----- Inputs -----
61 clk_i,
62 rst_i,
63 stall_a,
64 stall_x,
65 stall_m,
66 address_x,
67 address_m,
68 load_q_m,
69 store_q_m,
70 store_data,
71 store_byte_select,
72 refill_ready,
73 refill_data,
74 dflush,
75 // ----- Outputs -----
76 stall_request,
77 restart_request,
78 refill_request,
79 refill_address,
80 refilling,
81 load_data
82 );
84 /////////////////////////////////////////////////////
85 // Parameters
86 /////////////////////////////////////////////////////
88 parameter associativity = 1; // Associativity of the cache (Number of ways)
89 parameter sets = 512; // Number of sets
90 parameter bytes_per_line = 16; // Number of bytes per cache line
91 parameter base_address = 0; // Base address of cachable memory
92 parameter limit = 0; // Limit (highest address) of cachable memory
94 localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
95 localparam addr_set_width = clogb2(sets)-1;
96 localparam addr_offset_lsb = 2;
97 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
98 localparam addr_set_lsb = (addr_offset_msb+1);
99 localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
100 localparam addr_tag_lsb = (addr_set_msb+1);
101 localparam addr_tag_msb = clogb2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS)-1;
102 localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
104 /////////////////////////////////////////////////////
105 // Inputs
106 /////////////////////////////////////////////////////
108 input clk_i; // Clock
109 input rst_i; // Reset
111 input stall_a; // Stall A stage
112 input stall_x; // Stall X stage
113 input stall_m; // Stall M stage
115 input [`LM32_WORD_RNG] address_x; // X stage load/store address
116 input [`LM32_WORD_RNG] address_m; // M stage load/store address
117 input load_q_m; // Load instruction in M stage
118 input store_q_m; // Store instruction in M stage
119 input [`LM32_WORD_RNG] store_data; // Data to store
120 input [`LM32_BYTE_SELECT_RNG] store_byte_select; // Which bytes in store data should be modified
122 input refill_ready; // Indicates next word of refill data is ready
123 input [`LM32_WORD_RNG] refill_data; // Refill data
125 input dflush; // Indicates cache should be flushed
127 /////////////////////////////////////////////////////
128 // Outputs
129 /////////////////////////////////////////////////////
131 output stall_request; // Request pipeline be stalled because cache is busy
132 wire stall_request;
133 output restart_request; // Request to restart instruction that caused the cache miss
134 reg restart_request;
135 output refill_request; // Request a refill
136 reg refill_request;
137 output [`LM32_WORD_RNG] refill_address; // Address to refill from
138 reg [`LM32_WORD_RNG] refill_address;
139 output refilling; // Indicates if the cache is currently refilling
140 reg refilling;
141 output [`LM32_WORD_RNG] load_data; // Data read from cache
142 wire [`LM32_WORD_RNG] load_data;
144 /////////////////////////////////////////////////////
145 // Internal nets and registers
146 /////////////////////////////////////////////////////
148 wire read_port_enable; // Cache memory read port clock enable
149 wire write_port_enable; // Cache memory write port clock enable
150 wire [0:associativity-1] way_tmem_we; // Tag memory write enable
151 wire [0:associativity-1] way_dmem_we; // Data memory write enable
152 wire [`LM32_WORD_RNG] way_data[0:associativity-1]; // Data read from data memory
153 wire [`LM32_DC_TAGS_TAG_RNG] way_tag[0:associativity-1];// Tag read from tag memory
154 wire [0:associativity-1] way_valid; // Indicates which ways are valid
155 wire [0:associativity-1] way_match; // Indicates which ways matched
156 wire miss; // Indicates no ways matched
158 wire [`LM32_DC_TMEM_ADDR_RNG] tmem_read_address; // Tag memory read address
159 wire [`LM32_DC_TMEM_ADDR_RNG] tmem_write_address; // Tag memory write address
160 wire [`LM32_DC_DMEM_ADDR_RNG] dmem_read_address; // Data memory read address
161 wire [`LM32_DC_DMEM_ADDR_RNG] dmem_write_address; // Data memory write address
162 wire [`LM32_DC_TAGS_RNG] tmem_write_data; // Tag memory write data
163 reg [`LM32_WORD_RNG] dmem_write_data; // Data memory write data
165 reg [`LM32_DC_STATE_RNG] state; // Current state of FSM
166 wire flushing; // Indicates if cache is currently flushing
167 wire check; // Indicates if cache is currently checking for hits/misses
168 wire refill; // Indicates if cache is currently refilling
170 wire valid_store; // Indicates if there is a valid store instruction
171 reg [associativity-1:0] refill_way_select; // Which way should be refilled
172 reg [`LM32_DC_ADDR_OFFSET_RNG] refill_offset; // Which word in cache line should be refilled
173 wire last_refill; // Indicates when on last cycle of cache refill
174 reg [`LM32_DC_TMEM_ADDR_RNG] flush_set; // Which set is currently being flushed
176 genvar i, j;
178 /////////////////////////////////////////////////////
179 // Functions
180 /////////////////////////////////////////////////////
182 `include "lm32_functions.v"
184 /////////////////////////////////////////////////////
185 // Instantiations
186 /////////////////////////////////////////////////////
188 generate
189 for (i = 0; i < associativity; i = i + 1)
190 begin : memories
191 // Way data
192 if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
193 begin : data_memories
194 lm32_ram
195 #(
196 // ----- Parameters -------
197 .data_width (32),
198 .address_width (`LM32_DC_DMEM_ADDR_WIDTH),
199 `ifdef PLATFORM_LATTICE
200 `ifdef CFG_DCACHE_DAT_USE_DP_TRUE
201 .RAM_IMPLEMENTATION ("EBR"),
202 .RAM_TYPE ("RAM_DP_TRUE")
203 `else
204 `ifdef CFG_DCACHE_DAT_USE_SLICE
205 .RAM_IMPLEMENTATION ("SLICE")
206 `else
207 .RAM_IMPLEMENTATION ("AUTO")
208 `endif
209 `endif
210 `endif
211 ) way_0_data_ram
212 (
213 // ----- Inputs -------
214 .read_clk (clk_i),
215 .write_clk (clk_i),
216 .reset (rst_i),
217 .read_address (dmem_read_address),
218 .enable_read (read_port_enable),
219 .write_address (dmem_write_address),
220 .enable_write (write_port_enable),
221 .write_enable (way_dmem_we[i]),
222 .write_data (dmem_write_data),
223 // ----- Outputs -------
224 .read_data (way_data[i])
225 );
226 end
227 else
228 begin
229 for (j = 0; j < 4; j = j + 1)
230 begin : byte_memories
231 lm32_ram
232 #(
233 // ----- Parameters -------
234 .data_width (8),
235 .address_width (`LM32_DC_DMEM_ADDR_WIDTH),
236 `ifdef CFG_DCACHE_DAT_USE_DP_TRUE
237 .RAM_IMPLEMENTATION ("EBR"),
238 .RAM_TYPE ("RAM_DP_TRUE")
239 `else
240 `ifdef CFG_DCACHE_DAT_USE_SLICE
241 .RAM_IMPLEMENTATION ("SLICE")
242 `else
243 .RAM_IMPLEMENTATION ("AUTO")
244 `endif
245 `endif
246 ) way_0_data_ram
247 (
248 // ----- Inputs -------
249 .read_clk (clk_i),
250 .write_clk (clk_i),
251 .reset (rst_i),
252 .read_address (dmem_read_address),
253 .enable_read (read_port_enable),
254 .write_address (dmem_write_address),
255 .enable_write (write_port_enable),
256 .write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)),
257 .write_data (dmem_write_data[(j+1)*8-1:j*8]),
258 // ----- Outputs -------
259 .read_data (way_data[i][(j+1)*8-1:j*8])
260 );
261 end
262 end
264 // Way tags
265 lm32_ram
266 #(
267 // ----- Parameters -------
268 .data_width (`LM32_DC_TAGS_WIDTH),
269 .address_width (`LM32_DC_TMEM_ADDR_WIDTH),
270 `ifdef CFG_DCACHE_DAT_USE_DP_TRUE
271 .RAM_IMPLEMENTATION ("EBR"),
272 .RAM_TYPE ("RAM_DP_TRUE")
273 `else
274 `ifdef CFG_DCACHE_DAT_USE_SLICE
275 .RAM_IMPLEMENTATION ("SLICE")
276 `else
277 .RAM_IMPLEMENTATION ("AUTO")
278 `endif
279 `endif
280 ) way_0_tag_ram
281 (
282 // ----- Inputs -------
283 .read_clk (clk_i),
284 .write_clk (clk_i),
285 .reset (rst_i),
286 .read_address (tmem_read_address),
287 .enable_read (read_port_enable),
288 .write_address (tmem_write_address),
289 .enable_write (`TRUE),
290 .write_enable (way_tmem_we[i]),
291 .write_data (tmem_write_data),
292 // ----- Outputs -------
293 .read_data ({way_tag[i], way_valid[i]})
294 );
295 end
297 endgenerate
299 /////////////////////////////////////////////////////
300 // Combinational logic
301 /////////////////////////////////////////////////////
303 // Compute which ways in the cache match the address being read
304 generate
305 for (i = 0; i < associativity; i = i + 1)
306 begin : match
307 assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE});
308 end
309 endgenerate
311 // Select data from way that matched the address being read
312 generate
313 if (associativity == 1)
314 begin : data_1
315 assign load_data = way_data[0];
316 end
317 else if (associativity == 2)
318 begin : data_2
319 assign load_data = way_match[0] ? way_data[0] : way_data[1];
320 end
321 endgenerate
323 generate
324 if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
325 begin
326 // Select data to write to data memories
327 always @(*)
328 begin
329 if (refill == `TRUE)
330 dmem_write_data = refill_data;
331 else
332 begin
333 dmem_write_data[`LM32_BYTE_0_RNG] = store_byte_select[0] ? store_data[`LM32_BYTE_0_RNG] : load_data[`LM32_BYTE_0_RNG];
334 dmem_write_data[`LM32_BYTE_1_RNG] = store_byte_select[1] ? store_data[`LM32_BYTE_1_RNG] : load_data[`LM32_BYTE_1_RNG];
335 dmem_write_data[`LM32_BYTE_2_RNG] = store_byte_select[2] ? store_data[`LM32_BYTE_2_RNG] : load_data[`LM32_BYTE_2_RNG];
336 dmem_write_data[`LM32_BYTE_3_RNG] = store_byte_select[3] ? store_data[`LM32_BYTE_3_RNG] : load_data[`LM32_BYTE_3_RNG];
337 end
338 end
339 end
340 else
341 begin
342 // Select data to write to data memories - FIXME: Should use different write ports on dual port RAMs, but they don't work
343 always @(*)
344 begin
345 if (refill == `TRUE)
346 dmem_write_data = refill_data;
347 else
348 dmem_write_data = store_data;
349 end
350 end
351 endgenerate
353 // Compute address to use to index into the data memories
354 generate
355 if (bytes_per_line > 4)
356 assign dmem_write_address = (refill == `TRUE)
357 ? {refill_address[`LM32_DC_ADDR_SET_RNG], refill_offset}
358 : address_m[`LM32_DC_ADDR_IDX_RNG];
359 else
360 assign dmem_write_address = (refill == `TRUE)
361 ? refill_address[`LM32_DC_ADDR_SET_RNG]
362 : address_m[`LM32_DC_ADDR_IDX_RNG];
363 endgenerate
364 assign dmem_read_address = address_x[`LM32_DC_ADDR_IDX_RNG];
365 // Compute address to use to index into the tag memories
366 assign tmem_write_address = (flushing == `TRUE)
367 ? flush_set
368 : refill_address[`LM32_DC_ADDR_SET_RNG];
369 assign tmem_read_address = address_x[`LM32_DC_ADDR_SET_RNG];
371 // Compute signal to indicate when we are on the last refill accesses
372 generate
373 if (bytes_per_line > 4)
374 assign last_refill = refill_offset == {addr_offset_width{1'b1}};
375 else
376 assign last_refill = `TRUE;
377 endgenerate
379 // Compute data and tag memory access enable
380 assign read_port_enable = (stall_x == `FALSE);
381 assign write_port_enable = (refill_ready == `TRUE) || !stall_m;
383 // Determine when we have a valid store
384 assign valid_store = (store_q_m == `TRUE) && (check == `TRUE);
386 // Compute data and tag memory write enables
387 generate
388 if (associativity == 1)
389 begin : we_1
390 assign way_dmem_we[0] = (refill_ready == `TRUE) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
391 assign way_tmem_we[0] = (refill_ready == `TRUE) || (flushing == `TRUE);
392 end
393 else
394 begin : we_2
395 assign way_dmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
396 assign way_dmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || ((valid_store == `TRUE) && (way_match[1] == `TRUE));
397 assign way_tmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || (flushing == `TRUE);
398 assign way_tmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || (flushing == `TRUE);
399 end
400 endgenerate
402 // On the last refill cycle set the valid bit, for all other writes it should be cleared
403 assign tmem_write_data[`LM32_DC_TAGS_VALID_RNG] = ((last_refill == `TRUE) || (valid_store == `TRUE)) && (flushing == `FALSE);
404 assign tmem_write_data[`LM32_DC_TAGS_TAG_RNG] = refill_address[`LM32_DC_ADDR_TAG_RNG];
406 // Signals that indicate which state we are in
407 assign flushing = state[0];
408 assign check = state[1];
409 assign refill = state[2];
411 assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE);
412 assign stall_request = (check == `FALSE);
414 /////////////////////////////////////////////////////
415 // Sequential logic
416 /////////////////////////////////////////////////////
418 // Record way selected for replacement on a cache miss
419 generate
420 if (associativity >= 2)
421 begin : way_select
422 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
423 begin
424 if (rst_i == `TRUE)
425 refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
426 else
427 begin
428 if (refill_request == `TRUE)
429 refill_way_select <= {refill_way_select[0], refill_way_select[1]};
430 end
431 end
432 end
433 endgenerate
435 // Record whether we are currently refilling
436 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
437 begin
438 if (rst_i == `TRUE)
439 refilling <= `FALSE;
440 else
441 refilling <= refill;
442 end
444 // Instruction cache control FSM
445 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
446 begin
447 if (rst_i == `TRUE)
448 begin
449 state <= `LM32_DC_STATE_FLUSH;
450 flush_set <= {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}};
451 refill_request <= `FALSE;
452 refill_address <= {`LM32_WORD_WIDTH{1'bx}};
453 restart_request <= `FALSE;
454 end
455 else
456 begin
457 case (state)
459 // Flush the cache
460 `LM32_DC_STATE_FLUSH:
461 begin
462 if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}})
463 state <= `LM32_DC_STATE_CHECK;
464 flush_set <= flush_set - 1'b1;
465 end
467 // Check for cache misses
468 `LM32_DC_STATE_CHECK:
469 begin
470 if (stall_a == `FALSE)
471 restart_request <= `FALSE;
472 if (miss == `TRUE)
473 begin
474 refill_request <= `TRUE;
475 refill_address <= address_m;
476 state <= `LM32_DC_STATE_REFILL;
477 end
478 else if (dflush == `TRUE)
479 state <= `LM32_DC_STATE_FLUSH;
480 end
482 // Refill a cache line
483 `LM32_DC_STATE_REFILL:
484 begin
485 refill_request <= `FALSE;
486 if (refill_ready == `TRUE)
487 begin
488 if (last_refill == `TRUE)
489 begin
490 restart_request <= `TRUE;
491 state <= `LM32_DC_STATE_CHECK;
492 end
493 end
494 end
496 endcase
497 end
498 end
500 generate
501 if (bytes_per_line > 4)
502 begin
503 // Refill offset
504 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
505 begin
506 if (rst_i == `TRUE)
507 refill_offset <= {addr_offset_width{1'b0}};
508 else
509 begin
510 case (state)
512 // Check for cache misses
513 `LM32_DC_STATE_CHECK:
514 begin
515 if (miss == `TRUE)
516 refill_offset <= {addr_offset_width{1'b0}};
517 end
519 // Refill a cache line
520 `LM32_DC_STATE_REFILL:
521 begin
522 if (refill_ready == `TRUE)
523 refill_offset <= refill_offset + 1'b1;
524 end
526 endcase
527 end
528 end
529 end
530 endgenerate
532 endmodule
534 `endif