Sat, 06 Aug 2011 01:33:43 +0100
Update documents for LM32 V3.8
1 // ==================================================================
2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
3 // ------------------------------------------------------------------
4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
5 // ALL RIGHTS RESERVED
6 // ------------------------------------------------------------------
7 //
8 // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
9 //
10 // Permission:
11 //
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13 // pursuant to the terms of the Lattice Semiconductor Corporation
14 // Open Source License Agreement.
15 //
16 // Disclaimer:
17 //
18 // Lattice Semiconductor provides no warranty regarding the use or
19 // functionality of this code. It is the user's responsibility to
20 // verify the user’s design for consistency and functionality through
21 // the use of formal verification methods.
22 //
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36 // --------------------------------------------------------------------
37 // FILE DETAILS
38 // Project : LatticeMico32
39 // File : lm32_cpu.v
40 // Title : Top-level of CPU.
41 // Dependencies : lm32_include.v
42 //
43 // Version 3.8
44 // 1. Feature: Support for dynamically switching EBA to DEBA via a GPIO.
45 // 2. Bug: EA now reports instruction that caused the data abort, rather than
46 // next instruction.
47 //
48 // Version 3.4
49 // 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were
50 // never serviced.
51 //
52 // Version 3.3
53 // 1. Feature: Support for memory that is tightly coupled to processor core, and
54 // has a single-cycle access latency (same as caches). Instruction port has
55 // access to a dedicated physically-mapped memory. Data port has access to
56 // a dedicated physically-mapped memory. In order to be able to manipulate
57 // values in both these memories via the debugger, these memories also
58 // interface with the data port of LM32.
59 // 2. Feature: Extended Configuration Register
60 // 3. Bug Fix: Removed port names that conflict with keywords reserved in System-
61 // Verilog.
62 //
63 // Version 3.2
64 // 1. Bug Fix: Single-stepping a load/store to invalid address causes debugger to
65 // hang. At the same time CPU fails to register data bus error exception. Bug
66 // is caused because (a) data bus error exception occurs after load/store has
67 // passed X stage and next sequential instruction (e.g., brk) is already in X
68 // stage, and (b) data bus error exception had lower priority than, say, brk
69 // exception.
70 // 2. Bug Fix: If a brk (or scall/eret/bret) sequentially follows a load/store to
71 // invalid location, CPU will fail to register data bus error exception. The
72 // solution is to stall scall/eret/bret/brk instructions in D pipeline stage
73 // until load/store has completed.
74 // 3. Feature: Enable precise identification of load/store that causes seg fault.
75 // 4. SYNC resets used for register file when implemented in EBRs.
76 //
77 // Version 3.1
78 // 1. Feature: LM32 Register File can now be mapped in to on-chip block RAM (EBR)
79 // instead of distributed memory by enabling the option in LM32 GUI.
80 // 2. Feature: LM32 also adds a static branch predictor to improve branch
81 // performance. All immediate-based forward-pointing branches are predicted
82 // not-taken. All immediate-based backward-pointing branches are predicted taken.
83 //
84 // Version 7.0SP2, 3.0
85 // No Change
86 //
87 // Version 6.1.17
88 // Initial Release
89 // =============================================================================
91 `include "lm32_include.v"
93 /////////////////////////////////////////////////////
94 // Module interface
95 /////////////////////////////////////////////////////
97 module lm32_cpu (
98 // ----- Inputs -------
99 clk_i,
100 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
101 clk_n_i,
102 `endif
103 rst_i,
104 `ifdef CFG_DEBUG_ENABLED
105 `ifdef CFG_ALTERNATE_EBA
106 at_debug,
107 `endif
108 `endif
109 // From external devices
110 `ifdef CFG_INTERRUPTS_ENABLED
111 interrupt_n,
112 `endif
113 // From user logic
114 `ifdef CFG_USER_ENABLED
115 user_result,
116 user_complete,
117 `endif
118 `ifdef CFG_JTAG_ENABLED
119 // From JTAG
120 jtag_clk,
121 jtag_update,
122 jtag_reg_q,
123 jtag_reg_addr_q,
124 `endif
125 `ifdef CFG_IWB_ENABLED
126 // Instruction Wishbone master
127 I_DAT_I,
128 I_ACK_I,
129 I_ERR_I,
130 I_RTY_I,
131 `endif
132 // Data Wishbone master
133 D_DAT_I,
134 D_ACK_I,
135 D_ERR_I,
136 D_RTY_I,
137 // ----- Outputs -------
138 `ifdef CFG_TRACE_ENABLED
139 trace_pc,
140 trace_pc_valid,
141 trace_exception,
142 trace_eid,
143 trace_eret,
144 `ifdef CFG_DEBUG_ENABLED
145 trace_bret,
146 `endif
147 `endif
148 `ifdef CFG_JTAG_ENABLED
149 jtag_reg_d,
150 jtag_reg_addr_d,
151 `endif
152 `ifdef CFG_USER_ENABLED
153 user_valid,
154 user_opcode,
155 user_operand_0,
156 user_operand_1,
157 `endif
158 `ifdef CFG_IWB_ENABLED
159 // Instruction Wishbone master
160 I_DAT_O,
161 I_ADR_O,
162 I_CYC_O,
163 I_SEL_O,
164 I_STB_O,
165 I_WE_O,
166 I_CTI_O,
167 I_LOCK_O,
168 I_BTE_O,
169 `endif
170 // Data Wishbone master
171 D_DAT_O,
172 D_ADR_O,
173 D_CYC_O,
174 D_SEL_O,
175 D_STB_O,
176 D_WE_O,
177 D_CTI_O,
178 D_LOCK_O,
179 D_BTE_O
180 );
182 /////////////////////////////////////////////////////
183 // Parameters
184 /////////////////////////////////////////////////////
186 parameter eba_reset = `CFG_EBA_RESET; // Reset value for EBA CSR
187 `ifdef CFG_DEBUG_ENABLED
188 parameter deba_reset = `CFG_DEBA_RESET; // Reset value for DEBA CSR
189 `endif
191 `ifdef CFG_ICACHE_ENABLED
192 parameter icache_associativity = `CFG_ICACHE_ASSOCIATIVITY; // Associativity of the cache (Number of ways)
193 parameter icache_sets = `CFG_ICACHE_SETS; // Number of sets
194 parameter icache_bytes_per_line = `CFG_ICACHE_BYTES_PER_LINE; // Number of bytes per cache line
195 parameter icache_base_address = `CFG_ICACHE_BASE_ADDRESS; // Base address of cachable memory
196 parameter icache_limit = `CFG_ICACHE_LIMIT; // Limit (highest address) of cachable memory
197 `else
198 parameter icache_associativity = 1;
199 parameter icache_sets = 512;
200 parameter icache_bytes_per_line = 16;
201 parameter icache_base_address = 0;
202 parameter icache_limit = 0;
203 `endif
205 `ifdef CFG_DCACHE_ENABLED
206 parameter dcache_associativity = `CFG_DCACHE_ASSOCIATIVITY; // Associativity of the cache (Number of ways)
207 parameter dcache_sets = `CFG_DCACHE_SETS; // Number of sets
208 parameter dcache_bytes_per_line = `CFG_DCACHE_BYTES_PER_LINE; // Number of bytes per cache line
209 parameter dcache_base_address = `CFG_DCACHE_BASE_ADDRESS; // Base address of cachable memory
210 parameter dcache_limit = `CFG_DCACHE_LIMIT; // Limit (highest address) of cachable memory
211 `else
212 parameter dcache_associativity = 1;
213 parameter dcache_sets = 512;
214 parameter dcache_bytes_per_line = 16;
215 parameter dcache_base_address = 0;
216 parameter dcache_limit = 0;
217 `endif
219 `ifdef CFG_DEBUG_ENABLED
220 parameter watchpoints = `CFG_WATCHPOINTS; // Number of h/w watchpoint CSRs
221 `else
222 parameter watchpoints = 0;
223 `endif
224 `ifdef CFG_ROM_DEBUG_ENABLED
225 parameter breakpoints = `CFG_BREAKPOINTS; // Number of h/w breakpoint CSRs
226 `else
227 parameter breakpoints = 0;
228 `endif
230 `ifdef CFG_INTERRUPTS_ENABLED
231 parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts
232 `else
233 parameter interrupts = 0;
234 `endif
236 /////////////////////////////////////////////////////
237 // Inputs
238 /////////////////////////////////////////////////////
240 input clk_i; // Clock
241 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
242 input clk_n_i; // Inverted clock
243 `endif
244 input rst_i; // Reset
246 `ifdef CFG_DEBUG_ENABLED
247 `ifdef CFG_ALTERNATE_EBA
248 input at_debug; // GPIO input that maps EBA to DEBA
249 `endif
250 `endif
252 `ifdef CFG_INTERRUPTS_ENABLED
253 input [`LM32_INTERRUPT_RNG] interrupt_n; // Interrupt pins, active-low
254 `endif
256 `ifdef CFG_USER_ENABLED
257 input [`LM32_WORD_RNG] user_result; // User-defined instruction result
258 input user_complete; // User-defined instruction execution is complete
259 `endif
261 `ifdef CFG_JTAG_ENABLED
262 input jtag_clk; // JTAG clock
263 input jtag_update; // JTAG state machine is in data register update state
264 input [`LM32_BYTE_RNG] jtag_reg_q;
265 input [2:0] jtag_reg_addr_q;
266 `endif
268 `ifdef CFG_IWB_ENABLED
269 input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data
270 input I_ACK_I; // Instruction Wishbone interface acknowledgement
271 input I_ERR_I; // Instruction Wishbone interface error
272 input I_RTY_I; // Instruction Wishbone interface retry
273 `endif
275 input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
276 input D_ACK_I; // Data Wishbone interface acknowledgement
277 input D_ERR_I; // Data Wishbone interface error
278 input D_RTY_I; // Data Wishbone interface retry
280 /////////////////////////////////////////////////////
281 // Outputs
282 /////////////////////////////////////////////////////
284 `ifdef CFG_TRACE_ENABLED
285 output [`LM32_PC_RNG] trace_pc; // PC to trace
286 reg [`LM32_PC_RNG] trace_pc;
287 output trace_pc_valid; // Indicates that a new trace PC is valid
288 reg trace_pc_valid;
289 output trace_exception; // Indicates an exception has occured
290 reg trace_exception;
291 output [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured
292 reg [`LM32_EID_RNG] trace_eid;
293 output trace_eret; // Indicates an eret instruction has been executed
294 reg trace_eret;
295 `ifdef CFG_DEBUG_ENABLED
296 output trace_bret; // Indicates a bret instruction has been executed
297 reg trace_bret;
298 `endif
299 `endif
301 `ifdef CFG_JTAG_ENABLED
302 output [`LM32_BYTE_RNG] jtag_reg_d;
303 wire [`LM32_BYTE_RNG] jtag_reg_d;
304 output [2:0] jtag_reg_addr_d;
305 wire [2:0] jtag_reg_addr_d;
306 `endif
308 `ifdef CFG_USER_ENABLED
309 output user_valid; // Indicates if user_opcode is valid
310 wire user_valid;
311 output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode
312 reg [`LM32_USER_OPCODE_RNG] user_opcode;
313 output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction
314 wire [`LM32_WORD_RNG] user_operand_0;
315 output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction
316 wire [`LM32_WORD_RNG] user_operand_1;
317 `endif
319 `ifdef CFG_IWB_ENABLED
320 output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data
321 wire [`LM32_WORD_RNG] I_DAT_O;
322 output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address
323 wire [`LM32_WORD_RNG] I_ADR_O;
324 output I_CYC_O; // Instruction Wishbone interface cycle
325 wire I_CYC_O;
326 output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select
327 wire [`LM32_BYTE_SELECT_RNG] I_SEL_O;
328 output I_STB_O; // Instruction Wishbone interface strobe
329 wire I_STB_O;
330 output I_WE_O; // Instruction Wishbone interface write enable
331 wire I_WE_O;
332 output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type
333 wire [`LM32_CTYPE_RNG] I_CTI_O;
334 output I_LOCK_O; // Instruction Wishbone interface lock bus
335 wire I_LOCK_O;
336 output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type
337 wire [`LM32_BTYPE_RNG] I_BTE_O;
338 `endif
340 output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
341 wire [`LM32_WORD_RNG] D_DAT_O;
342 output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
343 wire [`LM32_WORD_RNG] D_ADR_O;
344 output D_CYC_O; // Data Wishbone interface cycle
345 wire D_CYC_O;
346 output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select
347 wire [`LM32_BYTE_SELECT_RNG] D_SEL_O;
348 output D_STB_O; // Data Wishbone interface strobe
349 wire D_STB_O;
350 output D_WE_O; // Data Wishbone interface write enable
351 wire D_WE_O;
352 output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type
353 wire [`LM32_CTYPE_RNG] D_CTI_O;
354 output D_LOCK_O; // Date Wishbone interface lock bus
355 wire D_LOCK_O;
356 output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
357 wire [`LM32_BTYPE_RNG] D_BTE_O;
359 /////////////////////////////////////////////////////
360 // Internal nets and registers
361 /////////////////////////////////////////////////////
363 // Pipeline registers
365 `ifdef LM32_CACHE_ENABLED
366 reg valid_a; // Instruction in A stage is valid
367 `endif
368 reg valid_f; // Instruction in F stage is valid
369 reg valid_d; // Instruction in D stage is valid
370 reg valid_x; // Instruction in X stage is valid
371 reg valid_m; // Instruction in M stage is valid
372 reg valid_w; // Instruction in W stage is valid
374 wire q_x;
375 wire [`LM32_WORD_RNG] immediate_d; // Immediate operand
376 wire load_d; // Indicates a load instruction
377 reg load_x;
378 reg load_m;
379 wire load_q_x;
380 wire store_q_x;
381 wire store_d; // Indicates a store instruction
382 reg store_x;
383 reg store_m;
384 wire [`LM32_SIZE_RNG] size_d; // Size of load/store (byte, hword, word)
385 reg [`LM32_SIZE_RNG] size_x;
386 wire branch_d; // Indicates a branch instruction
387 wire branch_predict_d; // Indicates a branch is predicted
388 wire branch_predict_taken_d; // Indicates a branch is predicted taken
389 wire [`LM32_PC_RNG] branch_predict_address_d; // Address to which predicted branch jumps
390 wire [`LM32_PC_RNG] branch_target_d;
391 wire bi_unconditional;
392 wire bi_conditional;
393 reg branch_x;
394 reg branch_predict_x;
395 reg branch_predict_taken_x;
396 reg branch_m;
397 reg branch_predict_m;
398 reg branch_predict_taken_m;
399 wire branch_mispredict_taken_m; // Indicates a branch was mispredicted as taken
400 wire branch_flushX_m; // Indicates that instruction in X stage must be squashed
401 wire branch_reg_d; // Branch to register or immediate
402 wire [`LM32_PC_RNG] branch_offset_d; // Branch offset for immediate branches
403 reg [`LM32_PC_RNG] branch_target_x; // Address to branch to
404 reg [`LM32_PC_RNG] branch_target_m;
405 wire [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0_d; // Which result should be selected in D stage for operand 0
406 wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be selected in D stage for operand 1
408 wire x_result_sel_csr_d; // Select X stage result from CSRs
409 reg x_result_sel_csr_x;
410 `ifdef LM32_MC_ARITHMETIC_ENABLED
411 wire x_result_sel_mc_arith_d; // Select X stage result from multi-cycle arithmetic unit
412 reg x_result_sel_mc_arith_x;
413 `endif
414 `ifdef LM32_NO_BARREL_SHIFT
415 wire x_result_sel_shift_d; // Select X stage result from shifter
416 reg x_result_sel_shift_x;
417 `endif
418 `ifdef CFG_SIGN_EXTEND_ENABLED
419 wire x_result_sel_sext_d; // Select X stage result from sign-extend logic
420 reg x_result_sel_sext_x;
421 `endif
422 wire x_result_sel_logic_d; // Select X stage result from logic op unit
423 reg x_result_sel_logic_x;
424 `ifdef CFG_USER_ENABLED
425 wire x_result_sel_user_d; // Select X stage result from user-defined logic
426 reg x_result_sel_user_x;
427 `endif
428 wire x_result_sel_add_d; // Select X stage result from adder
429 reg x_result_sel_add_x;
430 wire m_result_sel_compare_d; // Select M stage result from comparison logic
431 reg m_result_sel_compare_x;
432 reg m_result_sel_compare_m;
433 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
434 wire m_result_sel_shift_d; // Select M stage result from shifter
435 reg m_result_sel_shift_x;
436 reg m_result_sel_shift_m;
437 `endif
438 wire w_result_sel_load_d; // Select W stage result from load/store unit
439 reg w_result_sel_load_x;
440 reg w_result_sel_load_m;
441 reg w_result_sel_load_w;
442 `ifdef CFG_PL_MULTIPLY_ENABLED
443 wire w_result_sel_mul_d; // Select W stage result from multiplier
444 reg w_result_sel_mul_x;
445 reg w_result_sel_mul_m;
446 reg w_result_sel_mul_w;
447 `endif
448 wire x_bypass_enable_d; // Whether result is bypassable in X stage
449 reg x_bypass_enable_x;
450 wire m_bypass_enable_d; // Whether result is bypassable in M stage
451 reg m_bypass_enable_x;
452 reg m_bypass_enable_m;
453 wire sign_extend_d; // Whether to sign-extend or zero-extend
454 reg sign_extend_x;
455 wire write_enable_d; // Register file write enable
456 reg write_enable_x;
457 wire write_enable_q_x;
458 reg write_enable_m;
459 wire write_enable_q_m;
460 reg write_enable_w;
461 wire write_enable_q_w;
462 wire read_enable_0_d; // Register file read enable 0
463 wire [`LM32_REG_IDX_RNG] read_idx_0_d; // Register file read index 0
464 wire read_enable_1_d; // Register file read enable 1
465 wire [`LM32_REG_IDX_RNG] read_idx_1_d; // Register file read index 1
466 wire [`LM32_REG_IDX_RNG] write_idx_d; // Register file write index
467 reg [`LM32_REG_IDX_RNG] write_idx_x;
468 reg [`LM32_REG_IDX_RNG] write_idx_m;
469 reg [`LM32_REG_IDX_RNG] write_idx_w;
470 wire [`LM32_CSR_RNG] csr_d; // CSR read/write index
471 reg [`LM32_CSR_RNG] csr_x;
472 wire [`LM32_CONDITION_RNG] condition_d; // Branch condition
473 reg [`LM32_CONDITION_RNG] condition_x;
474 `ifdef CFG_DEBUG_ENABLED
475 wire break_d; // Indicates a break instruction
476 reg break_x;
477 `endif
478 wire scall_d; // Indicates a scall instruction
479 reg scall_x;
480 wire eret_d; // Indicates an eret instruction
481 reg eret_x;
482 wire eret_q_x;
483 reg eret_m;
484 `ifdef CFG_TRACE_ENABLED
485 reg eret_w;
486 `endif
487 `ifdef CFG_DEBUG_ENABLED
488 wire bret_d; // Indicates a bret instruction
489 reg bret_x;
490 wire bret_q_x;
491 reg bret_m;
492 `ifdef CFG_TRACE_ENABLED
493 reg bret_w;
494 `endif
495 `endif
496 wire csr_write_enable_d; // CSR write enable
497 reg csr_write_enable_x;
498 wire csr_write_enable_q_x;
499 `ifdef CFG_USER_ENABLED
500 wire [`LM32_USER_OPCODE_RNG] user_opcode_d; // User-defined instruction opcode
501 `endif
503 `ifdef CFG_BUS_ERRORS_ENABLED
504 wire bus_error_d; // Indicates an bus error occured while fetching the instruction in this pipeline stage
505 reg bus_error_x;
506 reg data_bus_error_exception_m;
507 reg [`LM32_PC_RNG] memop_pc_w;
508 `endif
510 reg [`LM32_WORD_RNG] d_result_0; // Result of instruction in D stage (operand 0)
511 reg [`LM32_WORD_RNG] d_result_1; // Result of instruction in D stage (operand 1)
512 reg [`LM32_WORD_RNG] x_result; // Result of instruction in X stage
513 reg [`LM32_WORD_RNG] m_result; // Result of instruction in M stage
514 reg [`LM32_WORD_RNG] w_result; // Result of instruction in W stage
516 reg [`LM32_WORD_RNG] operand_0_x; // Operand 0 for X stage instruction
517 reg [`LM32_WORD_RNG] operand_1_x; // Operand 1 for X stage instruction
518 reg [`LM32_WORD_RNG] store_operand_x; // Data read from register to store
519 reg [`LM32_WORD_RNG] operand_m; // Operand for M stage instruction
520 reg [`LM32_WORD_RNG] operand_w; // Operand for W stage instruction
522 // To/from register file
523 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
524 reg [`LM32_WORD_RNG] reg_data_live_0;
525 reg [`LM32_WORD_RNG] reg_data_live_1;
526 reg use_buf; // Whether to use reg_data_live or reg_data_buf
527 reg [`LM32_WORD_RNG] reg_data_buf_0;
528 reg [`LM32_WORD_RNG] reg_data_buf_1;
529 `endif
530 `ifdef LM32_EBR_REGISTER_FILE
531 `else
532 reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1]; // Register file
533 `endif
534 wire [`LM32_WORD_RNG] reg_data_0; // Register file read port 0 data
535 wire [`LM32_WORD_RNG] reg_data_1; // Register file read port 1 data
536 reg [`LM32_WORD_RNG] bypass_data_0; // Register value 0 after bypassing
537 reg [`LM32_WORD_RNG] bypass_data_1; // Register value 1 after bypassing
538 wire reg_write_enable_q_w;
540 reg interlock; // Indicates pipeline should be stalled because of a read-after-write hazzard
542 wire stall_a; // Stall instruction in A pipeline stage
543 wire stall_f; // Stall instruction in F pipeline stage
544 wire stall_d; // Stall instruction in D pipeline stage
545 wire stall_x; // Stall instruction in X pipeline stage
546 wire stall_m; // Stall instruction in M pipeline stage
548 // To/from adder
549 wire adder_op_d; // Whether to add or subtract
550 reg adder_op_x;
551 reg adder_op_x_n; // Inverted version of adder_op_x
552 wire [`LM32_WORD_RNG] adder_result_x; // Result from adder
553 wire adder_overflow_x; // Whether a signed overflow occured
554 wire adder_carry_n_x; // Whether a carry was generated
556 // To/from logical operations unit
557 wire [`LM32_LOGIC_OP_RNG] logic_op_d; // Which operation to perform
558 reg [`LM32_LOGIC_OP_RNG] logic_op_x;
559 wire [`LM32_WORD_RNG] logic_result_x; // Result of logical operation
561 `ifdef CFG_SIGN_EXTEND_ENABLED
562 // From sign-extension unit
563 wire [`LM32_WORD_RNG] sextb_result_x; // Result of byte sign-extension
564 wire [`LM32_WORD_RNG] sexth_result_x; // Result of half-word sign-extenstion
565 wire [`LM32_WORD_RNG] sext_result_x; // Result of sign-extension specified by instruction
566 `endif
568 // To/from shifter
569 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
570 `ifdef CFG_ROTATE_ENABLED
571 wire rotate_d; // Whether we should rotate or shift
572 reg rotate_x;
573 `endif
574 wire direction_d; // Which direction to shift in
575 reg direction_x;
576 wire [`LM32_WORD_RNG] shifter_result_m; // Result of shifter
577 `endif
578 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
579 wire shift_left_d; // Indicates whether to perform a left shift or not
580 wire shift_left_q_d;
581 wire shift_right_d; // Indicates whether to perform a right shift or not
582 wire shift_right_q_d;
583 `endif
584 `ifdef LM32_NO_BARREL_SHIFT
585 wire [`LM32_WORD_RNG] shifter_result_x; // Result of single-bit right shifter
586 `endif
588 // To/from multiplier
589 `ifdef LM32_MULTIPLY_ENABLED
590 wire [`LM32_WORD_RNG] multiplier_result_w; // Result from multiplier
591 `endif
592 `ifdef CFG_MC_MULTIPLY_ENABLED
593 wire multiply_d; // Indicates whether to perform a multiply or not
594 wire multiply_q_d;
595 `endif
597 // To/from divider
598 `ifdef CFG_MC_DIVIDE_ENABLED
599 wire divide_d; // Indicates whether to perform a divider or not
600 wire divide_q_d;
601 wire modulus_d;
602 wire modulus_q_d;
603 wire divide_by_zero_x; // Indicates an attempt was made to divide by zero
604 `endif
606 // To from multi-cycle arithmetic unit
607 `ifdef LM32_MC_ARITHMETIC_ENABLED
608 wire mc_stall_request_x; // Multi-cycle arithmetic unit stall request
609 wire [`LM32_WORD_RNG] mc_result_x;
610 `endif
612 // From CSRs
613 `ifdef CFG_INTERRUPTS_ENABLED
614 wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs
615 `endif
616 wire [`LM32_WORD_RNG] cfg; // Configuration CSR
617 wire [`LM32_WORD_RNG] cfg2; // Extended Configuration CSR
618 `ifdef CFG_CYCLE_COUNTER_ENABLED
619 reg [`LM32_WORD_RNG] cc; // Cycle counter CSR
620 `endif
621 reg [`LM32_WORD_RNG] csr_read_data_x; // Data read from CSRs
623 // To/from instruction unit
624 wire [`LM32_PC_RNG] pc_f; // PC of instruction in F stage
625 wire [`LM32_PC_RNG] pc_d; // PC of instruction in D stage
626 wire [`LM32_PC_RNG] pc_x; // PC of instruction in X stage
627 wire [`LM32_PC_RNG] pc_m; // PC of instruction in M stage
628 wire [`LM32_PC_RNG] pc_w; // PC of instruction in W stage
629 `ifdef CFG_TRACE_ENABLED
630 reg [`LM32_PC_RNG] pc_c; // PC of last commited instruction
631 `endif
632 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
633 wire [`LM32_INSTRUCTION_RNG] instruction_f; // Instruction in F stage
634 `endif
635 //pragma attribute instruction_d preserve_signal true
636 //pragma attribute instruction_d preserve_driver true
637 wire [`LM32_INSTRUCTION_RNG] instruction_d; // Instruction in D stage
638 `ifdef CFG_ICACHE_ENABLED
639 wire iflush; // Flush instruction cache
640 wire icache_stall_request; // Stall pipeline because instruction cache is busy
641 wire icache_restart_request; // Restart instruction that caused an instruction cache miss
642 wire icache_refill_request; // Request to refill instruction cache
643 wire icache_refilling; // Indicates the instruction cache is being refilled
644 `endif
645 `ifdef CFG_IROM_ENABLED
646 wire [`LM32_WORD_RNG] irom_store_data_m; // Store data to instruction ROM
647 wire [`LM32_WORD_RNG] irom_address_xm; // Address to instruction ROM from load-store unit
648 wire [`LM32_WORD_RNG] irom_data_m; // Load data from instruction ROM
649 wire irom_we_xm; // Indicates data needs to be written to instruction ROM
650 wire irom_stall_request_x; // Indicates D stage needs to be stalled on a store to instruction ROM
651 `endif
653 // To/from load/store unit
654 `ifdef CFG_DCACHE_ENABLED
655 wire dflush_x; // Flush data cache
656 reg dflush_m;
657 wire dcache_stall_request; // Stall pipeline because data cache is busy
658 wire dcache_restart_request; // Restart instruction that caused a data cache miss
659 wire dcache_refill_request; // Request to refill data cache
660 wire dcache_refilling; // Indicates the data cache is being refilled
661 `endif
662 wire [`LM32_WORD_RNG] load_data_w; // Result of a load instruction
663 wire stall_wb_load; // Stall pipeline because of a load via the data Wishbone interface
665 // To/from JTAG interface
666 `ifdef CFG_JTAG_ENABLED
667 `ifdef CFG_JTAG_UART_ENABLED
668 wire [`LM32_WORD_RNG] jtx_csr_read_data; // Read data for JTX CSR
669 wire [`LM32_WORD_RNG] jrx_csr_read_data; // Read data for JRX CSR
670 `endif
671 `ifdef CFG_HW_DEBUG_ENABLED
672 wire jtag_csr_write_enable; // Debugger CSR write enable
673 wire [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR
674 wire [`LM32_CSR_RNG] jtag_csr; // Which CSR to write
675 wire jtag_read_enable;
676 wire [`LM32_BYTE_RNG] jtag_read_data;
677 wire jtag_write_enable;
678 wire [`LM32_BYTE_RNG] jtag_write_data;
679 wire [`LM32_WORD_RNG] jtag_address;
680 wire jtag_access_complete;
681 `endif
682 `ifdef CFG_DEBUG_ENABLED
683 wire jtag_break; // Request from debugger to raise a breakpoint
684 `endif
685 `endif
687 // Hazzard detection
688 wire raw_x_0; // RAW hazzard between instruction in X stage and read port 0
689 wire raw_x_1; // RAW hazzard between instruction in X stage and read port 1
690 wire raw_m_0; // RAW hazzard between instruction in M stage and read port 0
691 wire raw_m_1; // RAW hazzard between instruction in M stage and read port 1
692 wire raw_w_0; // RAW hazzard between instruction in W stage and read port 0
693 wire raw_w_1; // RAW hazzard between instruction in W stage and read port 1
695 // Control flow
696 wire cmp_zero; // Result of comparison is zero
697 wire cmp_negative; // Result of comparison is negative
698 wire cmp_overflow; // Comparison produced an overflow
699 wire cmp_carry_n; // Comparison produced a carry, inverted
700 reg condition_met_x; // Condition of branch instruction is met
701 reg condition_met_m;
702 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
703 wire branch_taken_x; // Branch is taken in X stage
704 `endif
705 wire branch_taken_m; // Branch is taken in M stage
707 wire kill_f; // Kill instruction in F stage
708 wire kill_d; // Kill instruction in D stage
709 wire kill_x; // Kill instruction in X stage
710 wire kill_m; // Kill instruction in M stage
711 wire kill_w; // Kill instruction in W stage
713 reg [`LM32_PC_WIDTH+2-1:8] eba; // Exception Base Address (EBA) CSR
714 `ifdef CFG_DEBUG_ENABLED
715 reg [`LM32_PC_WIDTH+2-1:8] deba; // Debug Exception Base Address (DEBA) CSR
716 `endif
717 reg [`LM32_EID_RNG] eid_x; // Exception ID in X stage
718 `ifdef CFG_TRACE_ENABLED
719 reg [`LM32_EID_RNG] eid_m; // Exception ID in M stage
720 reg [`LM32_EID_RNG] eid_w; // Exception ID in W stage
721 `endif
723 `ifdef CFG_DEBUG_ENABLED
724 `ifdef LM32_SINGLE_STEP_ENABLED
725 wire dc_ss; // Is single-step enabled
726 `endif
727 wire dc_re; // Remap all exceptions
728 wire exception_x; // An exception occured in the X stage
729 reg exception_m; // An instruction that caused an exception is in the M stage
730 wire debug_exception_x; // Indicates if a debug exception has occured
731 reg debug_exception_m;
732 reg debug_exception_w;
733 wire debug_exception_q_w;
734 wire non_debug_exception_x; // Indicates if a non debug exception has occured
735 reg non_debug_exception_m;
736 reg non_debug_exception_w;
737 wire non_debug_exception_q_w;
738 `else
739 wire exception_x; // Indicates if a debug exception has occured
740 reg exception_m;
741 reg exception_w;
742 wire exception_q_w;
743 `endif
745 `ifdef CFG_DEBUG_ENABLED
746 `ifdef CFG_JTAG_ENABLED
747 wire reset_exception; // Indicates if a reset exception has occured
748 `endif
749 `endif
750 `ifdef CFG_INTERRUPTS_ENABLED
751 wire interrupt_exception; // Indicates if an interrupt exception has occured
752 `endif
753 `ifdef CFG_DEBUG_ENABLED
754 wire breakpoint_exception; // Indicates if a breakpoint exception has occured
755 wire watchpoint_exception; // Indicates if a watchpoint exception has occured
756 `endif
757 `ifdef CFG_BUS_ERRORS_ENABLED
758 wire instruction_bus_error_exception; // Indicates if an instruction bus error exception has occured
759 wire data_bus_error_exception; // Indicates if a data bus error exception has occured
760 `endif
761 `ifdef CFG_MC_DIVIDE_ENABLED
762 wire divide_by_zero_exception; // Indicates if a divide by zero exception has occured
763 `endif
764 wire system_call_exception; // Indicates if a system call exception has occured
766 `ifdef CFG_BUS_ERRORS_ENABLED
767 reg data_bus_error_seen; // Indicates if a data bus error was seen
768 `endif
770 /////////////////////////////////////////////////////
771 // Functions
772 /////////////////////////////////////////////////////
774 `include "lm32_functions.v"
776 /////////////////////////////////////////////////////
777 // Instantiations
778 /////////////////////////////////////////////////////
780 // Instruction unit
781 lm32_instruction_unit #(
782 .associativity (icache_associativity),
783 .sets (icache_sets),
784 .bytes_per_line (icache_bytes_per_line),
785 .base_address (icache_base_address),
786 .limit (icache_limit)
787 ) instruction_unit (
788 // ----- Inputs -------
789 .clk_i (clk_i),
790 .rst_i (rst_i),
791 `ifdef CFG_DEBUG_ENABLED
792 `ifdef CFG_ALTERNATE_EBA
793 .at_debug (at_debug),
794 `endif
795 `endif
796 // From pipeline
797 .stall_a (stall_a),
798 .stall_f (stall_f),
799 .stall_d (stall_d),
800 .stall_x (stall_x),
801 .stall_m (stall_m),
802 .valid_f (valid_f),
803 .valid_d (valid_d),
804 .kill_f (kill_f),
805 .branch_predict_taken_d (branch_predict_taken_d),
806 .branch_predict_address_d (branch_predict_address_d),
807 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
808 .branch_taken_x (branch_taken_x),
809 .branch_target_x (branch_target_x),
810 `endif
811 .exception_m (exception_m),
812 .branch_taken_m (branch_taken_m),
813 .branch_mispredict_taken_m (branch_mispredict_taken_m),
814 .branch_target_m (branch_target_m),
815 `ifdef CFG_ICACHE_ENABLED
816 .iflush (iflush),
817 `endif
818 `ifdef CFG_IROM_ENABLED
819 .irom_store_data_m (irom_store_data_m),
820 .irom_address_xm (irom_address_xm),
821 .irom_we_xm (irom_we_xm),
822 `endif
823 `ifdef CFG_DCACHE_ENABLED
824 .dcache_restart_request (dcache_restart_request),
825 .dcache_refill_request (dcache_refill_request),
826 .dcache_refilling (dcache_refilling),
827 `endif
828 `ifdef CFG_IWB_ENABLED
829 // From Wishbone
830 .i_dat_i (I_DAT_I),
831 .i_ack_i (I_ACK_I),
832 .i_err_i (I_ERR_I),
833 `endif
834 `ifdef CFG_HW_DEBUG_ENABLED
835 .jtag_read_enable (jtag_read_enable),
836 .jtag_write_enable (jtag_write_enable),
837 .jtag_write_data (jtag_write_data),
838 .jtag_address (jtag_address),
839 `endif
840 // ----- Outputs -------
841 // To pipeline
842 .pc_f (pc_f),
843 .pc_d (pc_d),
844 .pc_x (pc_x),
845 .pc_m (pc_m),
846 .pc_w (pc_w),
847 `ifdef CFG_ICACHE_ENABLED
848 .icache_stall_request (icache_stall_request),
849 .icache_restart_request (icache_restart_request),
850 .icache_refill_request (icache_refill_request),
851 .icache_refilling (icache_refilling),
852 `endif
853 `ifdef CFG_IROM_ENABLED
854 .irom_data_m (irom_data_m),
855 `endif
856 `ifdef CFG_IWB_ENABLED
857 // To Wishbone
858 .i_dat_o (I_DAT_O),
859 .i_adr_o (I_ADR_O),
860 .i_cyc_o (I_CYC_O),
861 .i_sel_o (I_SEL_O),
862 .i_stb_o (I_STB_O),
863 .i_we_o (I_WE_O),
864 .i_cti_o (I_CTI_O),
865 .i_lock_o (I_LOCK_O),
866 .i_bte_o (I_BTE_O),
867 `endif
868 `ifdef CFG_HW_DEBUG_ENABLED
869 .jtag_read_data (jtag_read_data),
870 .jtag_access_complete (jtag_access_complete),
871 `endif
872 `ifdef CFG_BUS_ERRORS_ENABLED
873 .bus_error_d (bus_error_d),
874 `endif
875 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
876 .instruction_f (instruction_f),
877 `endif
878 .instruction_d (instruction_d)
879 );
881 // Instruction decoder
882 lm32_decoder decoder (
883 // ----- Inputs -------
884 .instruction (instruction_d),
885 // ----- Outputs -------
886 .d_result_sel_0 (d_result_sel_0_d),
887 .d_result_sel_1 (d_result_sel_1_d),
888 .x_result_sel_csr (x_result_sel_csr_d),
889 `ifdef LM32_MC_ARITHMETIC_ENABLED
890 .x_result_sel_mc_arith (x_result_sel_mc_arith_d),
891 `endif
892 `ifdef LM32_NO_BARREL_SHIFT
893 .x_result_sel_shift (x_result_sel_shift_d),
894 `endif
895 `ifdef CFG_SIGN_EXTEND_ENABLED
896 .x_result_sel_sext (x_result_sel_sext_d),
897 `endif
898 .x_result_sel_logic (x_result_sel_logic_d),
899 `ifdef CFG_USER_ENABLED
900 .x_result_sel_user (x_result_sel_user_d),
901 `endif
902 .x_result_sel_add (x_result_sel_add_d),
903 .m_result_sel_compare (m_result_sel_compare_d),
904 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
905 .m_result_sel_shift (m_result_sel_shift_d),
906 `endif
907 .w_result_sel_load (w_result_sel_load_d),
908 `ifdef CFG_PL_MULTIPLY_ENABLED
909 .w_result_sel_mul (w_result_sel_mul_d),
910 `endif
911 .x_bypass_enable (x_bypass_enable_d),
912 .m_bypass_enable (m_bypass_enable_d),
913 .read_enable_0 (read_enable_0_d),
914 .read_idx_0 (read_idx_0_d),
915 .read_enable_1 (read_enable_1_d),
916 .read_idx_1 (read_idx_1_d),
917 .write_enable (write_enable_d),
918 .write_idx (write_idx_d),
919 .immediate (immediate_d),
920 .branch_offset (branch_offset_d),
921 .load (load_d),
922 .store (store_d),
923 .size (size_d),
924 .sign_extend (sign_extend_d),
925 .adder_op (adder_op_d),
926 .logic_op (logic_op_d),
927 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
928 .direction (direction_d),
929 `endif
930 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
931 .shift_left (shift_left_d),
932 .shift_right (shift_right_d),
933 `endif
934 `ifdef CFG_MC_MULTIPLY_ENABLED
935 .multiply (multiply_d),
936 `endif
937 `ifdef CFG_MC_DIVIDE_ENABLED
938 .divide (divide_d),
939 .modulus (modulus_d),
940 `endif
941 .branch (branch_d),
942 .bi_unconditional (bi_unconditional),
943 .bi_conditional (bi_conditional),
944 .branch_reg (branch_reg_d),
945 .condition (condition_d),
946 `ifdef CFG_DEBUG_ENABLED
947 .break_opcode (break_d),
948 `endif
949 .scall (scall_d),
950 .eret (eret_d),
951 `ifdef CFG_DEBUG_ENABLED
952 .bret (bret_d),
953 `endif
954 `ifdef CFG_USER_ENABLED
955 .user_opcode (user_opcode_d),
956 `endif
957 .csr_write_enable (csr_write_enable_d)
958 );
960 // Load/store unit
961 lm32_load_store_unit #(
962 .associativity (dcache_associativity),
963 .sets (dcache_sets),
964 .bytes_per_line (dcache_bytes_per_line),
965 .base_address (dcache_base_address),
966 .limit (dcache_limit)
967 ) load_store_unit (
968 // ----- Inputs -------
969 .clk_i (clk_i),
970 .rst_i (rst_i),
971 // From pipeline
972 .stall_a (stall_a),
973 .stall_x (stall_x),
974 .stall_m (stall_m),
975 .kill_m (kill_m),
976 .exception_m (exception_m),
977 .store_operand_x (store_operand_x),
978 .load_store_address_x (adder_result_x),
979 .load_store_address_m (operand_m),
980 .load_store_address_w (operand_w[1:0]),
981 .load_x (load_x),
982 .store_x (store_x),
983 .load_q_x (load_q_x),
984 .store_q_x (store_q_x),
985 .load_q_m (load_q_m),
986 .store_q_m (store_q_m),
987 .sign_extend_x (sign_extend_x),
988 .size_x (size_x),
989 `ifdef CFG_DCACHE_ENABLED
990 .dflush (dflush_m),
991 `endif
992 `ifdef CFG_IROM_ENABLED
993 .irom_data_m (irom_data_m),
994 `endif
995 // From Wishbone
996 .d_dat_i (D_DAT_I),
997 .d_ack_i (D_ACK_I),
998 .d_err_i (D_ERR_I),
999 .d_rty_i (D_RTY_I),
1000 // ----- Outputs -------
1001 // To pipeline
1002 `ifdef CFG_DCACHE_ENABLED
1003 .dcache_refill_request (dcache_refill_request),
1004 .dcache_restart_request (dcache_restart_request),
1005 .dcache_stall_request (dcache_stall_request),
1006 .dcache_refilling (dcache_refilling),
1007 `endif
1008 `ifdef CFG_IROM_ENABLED
1009 .irom_store_data_m (irom_store_data_m),
1010 .irom_address_xm (irom_address_xm),
1011 .irom_we_xm (irom_we_xm),
1012 .irom_stall_request_x (irom_stall_request_x),
1013 `endif
1014 .load_data_w (load_data_w),
1015 .stall_wb_load (stall_wb_load),
1016 // To Wishbone
1017 .d_dat_o (D_DAT_O),
1018 .d_adr_o (D_ADR_O),
1019 .d_cyc_o (D_CYC_O),
1020 .d_sel_o (D_SEL_O),
1021 .d_stb_o (D_STB_O),
1022 .d_we_o (D_WE_O),
1023 .d_cti_o (D_CTI_O),
1024 .d_lock_o (D_LOCK_O),
1025 .d_bte_o (D_BTE_O)
1026 );
1028 // Adder
1029 lm32_adder adder (
1030 // ----- Inputs -------
1031 .adder_op_x (adder_op_x),
1032 .adder_op_x_n (adder_op_x_n),
1033 .operand_0_x (operand_0_x),
1034 .operand_1_x (operand_1_x),
1035 // ----- Outputs -------
1036 .adder_result_x (adder_result_x),
1037 .adder_carry_n_x (adder_carry_n_x),
1038 .adder_overflow_x (adder_overflow_x)
1039 );
1041 // Logic operations
1042 lm32_logic_op logic_op (
1043 // ----- Inputs -------
1044 .logic_op_x (logic_op_x),
1045 .operand_0_x (operand_0_x),
1047 .operand_1_x (operand_1_x),
1048 // ----- Outputs -------
1049 .logic_result_x (logic_result_x)
1050 );
1052 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
1053 // Pipelined barrel-shifter
1054 lm32_shifter shifter (
1055 // ----- Inputs -------
1056 .clk_i (clk_i),
1057 .rst_i (rst_i),
1058 .stall_x (stall_x),
1059 .direction_x (direction_x),
1060 .sign_extend_x (sign_extend_x),
1061 .operand_0_x (operand_0_x),
1062 .operand_1_x (operand_1_x),
1063 // ----- Outputs -------
1064 .shifter_result_m (shifter_result_m)
1065 );
1066 `endif
1068 `ifdef CFG_PL_MULTIPLY_ENABLED
1069 // Pipeline fixed-point multiplier
1070 lm32_multiplier multiplier (
1071 // ----- Inputs -------
1072 .clk_i (clk_i),
1073 .rst_i (rst_i),
1074 .stall_x (stall_x),
1075 .stall_m (stall_m),
1076 .operand_0 (d_result_0),
1077 .operand_1 (d_result_1),
1078 // ----- Outputs -------
1079 .result (multiplier_result_w)
1080 );
1081 `endif
1083 `ifdef LM32_MC_ARITHMETIC_ENABLED
1084 // Multi-cycle arithmetic
1085 lm32_mc_arithmetic mc_arithmetic (
1086 // ----- Inputs -------
1087 .clk_i (clk_i),
1088 .rst_i (rst_i),
1089 .stall_d (stall_d),
1090 .kill_x (kill_x),
1091 `ifdef CFG_MC_DIVIDE_ENABLED
1092 .divide_d (divide_q_d),
1093 .modulus_d (modulus_q_d),
1094 `endif
1095 `ifdef CFG_MC_MULTIPLY_ENABLED
1096 .multiply_d (multiply_q_d),
1097 `endif
1098 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
1099 .shift_left_d (shift_left_q_d),
1100 .shift_right_d (shift_right_q_d),
1101 .sign_extend_d (sign_extend_d),
1102 `endif
1103 .operand_0_d (d_result_0),
1104 .operand_1_d (d_result_1),
1105 // ----- Outputs -------
1106 .result_x (mc_result_x),
1107 `ifdef CFG_MC_DIVIDE_ENABLED
1108 .divide_by_zero_x (divide_by_zero_x),
1109 `endif
1110 .stall_request_x (mc_stall_request_x)
1111 );
1112 `endif
1114 `ifdef CFG_INTERRUPTS_ENABLED
1115 // Interrupt unit
1116 lm32_interrupt interrupt (
1117 // ----- Inputs -------
1118 .clk_i (clk_i),
1119 .rst_i (rst_i),
1120 // From external devices
1121 .interrupt_n (interrupt_n),
1122 // From pipeline
1123 .stall_x (stall_x),
1124 `ifdef CFG_DEBUG_ENABLED
1125 .non_debug_exception (non_debug_exception_q_w),
1126 .debug_exception (debug_exception_q_w),
1127 `else
1128 .exception (exception_q_w),
1129 `endif
1130 .eret_q_x (eret_q_x),
1131 `ifdef CFG_DEBUG_ENABLED
1132 .bret_q_x (bret_q_x),
1133 `endif
1134 .csr (csr_x),
1135 .csr_write_data (operand_1_x),
1136 .csr_write_enable (csr_write_enable_q_x),
1137 // ----- Outputs -------
1138 .interrupt_exception (interrupt_exception),
1139 // To pipeline
1140 .csr_read_data (interrupt_csr_read_data_x)
1141 );
1142 `endif
1144 `ifdef CFG_JTAG_ENABLED
1145 // JTAG interface
1146 lm32_jtag jtag (
1147 // ----- Inputs -------
1148 .clk_i (clk_i),
1149 .rst_i (rst_i),
1150 // From JTAG
1151 .jtag_clk (jtag_clk),
1152 .jtag_update (jtag_update),
1153 .jtag_reg_q (jtag_reg_q),
1154 .jtag_reg_addr_q (jtag_reg_addr_q),
1155 // From pipeline
1156 `ifdef CFG_JTAG_UART_ENABLED
1157 .csr (csr_x),
1158 .csr_write_data (operand_1_x),
1159 .csr_write_enable (csr_write_enable_q_x),
1160 .stall_x (stall_x),
1161 `endif
1162 `ifdef CFG_HW_DEBUG_ENABLED
1163 .jtag_read_data (jtag_read_data),
1164 .jtag_access_complete (jtag_access_complete),
1165 `endif
1166 `ifdef CFG_DEBUG_ENABLED
1167 .exception_q_w (debug_exception_q_w || non_debug_exception_q_w),
1168 `endif
1169 // ----- Outputs -------
1170 // To pipeline
1171 `ifdef CFG_JTAG_UART_ENABLED
1172 .jtx_csr_read_data (jtx_csr_read_data),
1173 .jrx_csr_read_data (jrx_csr_read_data),
1174 `endif
1175 `ifdef CFG_HW_DEBUG_ENABLED
1176 .jtag_csr_write_enable (jtag_csr_write_enable),
1177 .jtag_csr_write_data (jtag_csr_write_data),
1178 .jtag_csr (jtag_csr),
1179 .jtag_read_enable (jtag_read_enable),
1180 .jtag_write_enable (jtag_write_enable),
1181 .jtag_write_data (jtag_write_data),
1182 .jtag_address (jtag_address),
1183 `endif
1184 `ifdef CFG_DEBUG_ENABLED
1185 .jtag_break (jtag_break),
1186 .jtag_reset (reset_exception),
1187 `endif
1188 // To JTAG
1189 .jtag_reg_d (jtag_reg_d),
1190 .jtag_reg_addr_d (jtag_reg_addr_d)
1191 );
1192 `endif
1194 `ifdef CFG_DEBUG_ENABLED
1195 // Debug unit
1196 lm32_debug #(
1197 .breakpoints (breakpoints),
1198 .watchpoints (watchpoints)
1199 ) hw_debug (
1200 // ----- Inputs -------
1201 .clk_i (clk_i),
1202 .rst_i (rst_i),
1203 .pc_x (pc_x),
1204 .load_x (load_x),
1205 .store_x (store_x),
1206 .load_store_address_x (adder_result_x),
1207 .csr_write_enable_x (csr_write_enable_q_x),
1208 .csr_write_data (operand_1_x),
1209 .csr_x (csr_x),
1210 `ifdef CFG_HW_DEBUG_ENABLED
1211 .jtag_csr_write_enable (jtag_csr_write_enable),
1212 .jtag_csr_write_data (jtag_csr_write_data),
1213 .jtag_csr (jtag_csr),
1214 `endif
1215 `ifdef LM32_SINGLE_STEP_ENABLED
1216 .eret_q_x (eret_q_x),
1217 .bret_q_x (bret_q_x),
1218 .stall_x (stall_x),
1219 .exception_x (exception_x),
1220 .q_x (q_x),
1221 `ifdef CFG_DCACHE_ENABLED
1222 .dcache_refill_request (dcache_refill_request),
1223 `endif
1224 `endif
1225 // ----- Outputs -------
1226 `ifdef LM32_SINGLE_STEP_ENABLED
1227 .dc_ss (dc_ss),
1228 `endif
1229 .dc_re (dc_re),
1230 .bp_match (bp_match),
1231 .wp_match (wp_match)
1232 );
1233 `endif
1235 // Register file
1237 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
1238 /*----------------------------------------------------------------------
1239 Register File is implemented using EBRs. There can be three accesses to
1240 the register file in each cycle: two reads and one write. On-chip block
1241 RAM has two read/write ports. To accomodate three accesses, two on-chip
1242 block RAMs are used (each register file "write" is made to both block
1243 RAMs).
1245 One limitation of the on-chip block RAMs is that one cannot perform a
1246 read and write to same location in a cycle (if this is done, then the
1247 data read out is indeterminate).
1248 ----------------------------------------------------------------------*/
1249 wire [31:0] regfile_data_0, regfile_data_1;
1250 reg [31:0] w_result_d;
1251 reg regfile_raw_0, regfile_raw_0_nxt;
1252 reg regfile_raw_1, regfile_raw_1_nxt;
1254 /*----------------------------------------------------------------------
1255 Check if read and write is being performed to same register in current
1256 cycle? This is done by comparing the read and write IDXs.
1257 ----------------------------------------------------------------------*/
1258 always @(reg_write_enable_q_w or write_idx_w or instruction_f)
1259 begin
1260 if (reg_write_enable_q_w
1261 && (write_idx_w == instruction_f[25:21]))
1262 regfile_raw_0_nxt = 1'b1;
1263 else
1264 regfile_raw_0_nxt = 1'b0;
1266 if (reg_write_enable_q_w
1267 && (write_idx_w == instruction_f[20:16]))
1268 regfile_raw_1_nxt = 1'b1;
1269 else
1270 regfile_raw_1_nxt = 1'b0;
1271 end
1273 /*----------------------------------------------------------------------
1274 Select latched (delayed) write value or data from register file. If
1275 read in previous cycle was performed to register written to in same
1276 cycle, then latched (delayed) write value is selected.
1277 ----------------------------------------------------------------------*/
1278 always @(regfile_raw_0 or w_result_d or regfile_data_0)
1279 if (regfile_raw_0)
1280 reg_data_live_0 = w_result_d;
1281 else
1282 reg_data_live_0 = regfile_data_0;
1284 /*----------------------------------------------------------------------
1285 Select latched (delayed) write value or data from register file. If
1286 read in previous cycle was performed to register written to in same
1287 cycle, then latched (delayed) write value is selected.
1288 ----------------------------------------------------------------------*/
1289 always @(regfile_raw_1 or w_result_d or regfile_data_1)
1290 if (regfile_raw_1)
1291 reg_data_live_1 = w_result_d;
1292 else
1293 reg_data_live_1 = regfile_data_1;
1295 /*----------------------------------------------------------------------
1296 Latch value written to register file
1297 ----------------------------------------------------------------------*/
1298 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
1299 if (rst_i == `TRUE)
1300 begin
1301 regfile_raw_0 <= 1'b0;
1302 regfile_raw_1 <= 1'b0;
1303 w_result_d <= 32'b0;
1304 end
1305 else
1306 begin
1307 regfile_raw_0 <= regfile_raw_0_nxt;
1308 regfile_raw_1 <= regfile_raw_1_nxt;
1309 w_result_d <= w_result;
1310 end
1312 /*----------------------------------------------------------------------
1313 Register file instantiation as Pseudo-Dual Port EBRs.
1314 ----------------------------------------------------------------------*/
1315 pmi_ram_dp
1316 #(
1317 // ----- Parameters -----
1318 .pmi_wr_addr_depth(1<<5),
1319 .pmi_wr_addr_width(5),
1320 .pmi_wr_data_width(32),
1321 .pmi_rd_addr_depth(1<<5),
1322 .pmi_rd_addr_width(5),
1323 .pmi_rd_data_width(32),
1324 .pmi_regmode("noreg"),
1325 .pmi_gsr("enable"),
1326 .pmi_resetmode("sync"),
1327 .pmi_init_file("none"),
1328 .pmi_init_file_format("binary"),
1329 .pmi_family(`LATTICE_FAMILY),
1330 .module_type("pmi_ram_dp")
1331 )
1332 reg_0
1333 (
1334 // ----- Inputs -----
1335 .Data(w_result),
1336 .WrAddress(write_idx_w),
1337 .RdAddress(instruction_f[25:21]),
1338 .WrClock(clk_i),
1339 .RdClock(clk_i),
1340 .WrClockEn(`TRUE),
1341 .RdClockEn(`TRUE),
1342 .WE(reg_write_enable_q_w),
1343 .Reset(rst_i),
1344 // ----- Outputs -----
1345 .Q(regfile_data_0)
1346 );
1348 pmi_ram_dp
1349 #(
1350 // ----- Parameters -----
1351 .pmi_wr_addr_depth(1<<5),
1352 .pmi_wr_addr_width(5),
1353 .pmi_wr_data_width(32),
1354 .pmi_rd_addr_depth(1<<5),
1355 .pmi_rd_addr_width(5),
1356 .pmi_rd_data_width(32),
1357 .pmi_regmode("noreg"),
1358 .pmi_gsr("enable"),
1359 .pmi_resetmode("sync"),
1360 .pmi_init_file("none"),
1361 .pmi_init_file_format("binary"),
1362 .pmi_family(`LATTICE_FAMILY),
1363 .module_type("pmi_ram_dp")
1364 )
1365 reg_1
1366 (
1367 // ----- Inputs -----
1368 .Data(w_result),
1369 .WrAddress(write_idx_w),
1370 .RdAddress(instruction_f[20:16]),
1371 .WrClock(clk_i),
1372 .RdClock(clk_i),
1373 .WrClockEn(`TRUE),
1374 .RdClockEn(`TRUE),
1375 .WE(reg_write_enable_q_w),
1376 .Reset(rst_i),
1377 // ----- Outputs -----
1378 .Q(regfile_data_1)
1379 );
1380 `endif
1382 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
1383 pmi_ram_dp
1384 #(
1385 // ----- Parameters -----
1386 .pmi_wr_addr_depth(1<<5),
1387 .pmi_wr_addr_width(5),
1388 .pmi_wr_data_width(32),
1389 .pmi_rd_addr_depth(1<<5),
1390 .pmi_rd_addr_width(5),
1391 .pmi_rd_data_width(32),
1392 .pmi_regmode("noreg"),
1393 .pmi_gsr("enable"),
1394 .pmi_resetmode("sync"),
1395 .pmi_init_file("none"),
1396 .pmi_init_file_format("binary"),
1397 .pmi_family(`LATTICE_FAMILY),
1398 .module_type("pmi_ram_dp")
1399 )
1400 reg_0
1401 (
1402 // ----- Inputs -----
1403 .Data(w_result),
1404 .WrAddress(write_idx_w),
1405 .RdAddress(read_idx_0_d),
1406 .WrClock(clk_i),
1407 .RdClock(clk_n_i),
1408 .WrClockEn(`TRUE),
1409 .RdClockEn(stall_f == `FALSE),
1410 .WE(reg_write_enable_q_w),
1411 .Reset(rst_i),
1412 // ----- Outputs -----
1413 .Q(reg_data_0)
1414 );
1416 pmi_ram_dp
1417 #(
1418 // ----- Parameters -----
1419 .pmi_wr_addr_depth(1<<5),
1420 .pmi_wr_addr_width(5),
1421 .pmi_wr_data_width(32),
1422 .pmi_rd_addr_depth(1<<5),
1423 .pmi_rd_addr_width(5),
1424 .pmi_rd_data_width(32),
1425 .pmi_regmode("noreg"),
1426 .pmi_gsr("enable"),
1427 .pmi_resetmode("sync"),
1428 .pmi_init_file("none"),
1429 .pmi_init_file_format("binary"),
1430 .pmi_family(`LATTICE_FAMILY),
1431 .module_type("pmi_ram_dp")
1432 )
1433 reg_1
1434 (
1435 // ----- Inputs -----
1436 .Data(w_result),
1437 .WrAddress(write_idx_w),
1438 .RdAddress(read_idx_1_d),
1439 .WrClock(clk_i),
1440 .RdClock(clk_n_i),
1441 .WrClockEn(`TRUE),
1442 .RdClockEn(stall_f == `FALSE),
1443 .WE(reg_write_enable_q_w),
1444 .Reset(rst_i),
1445 // ----- Outputs -----
1446 .Q(reg_data_1)
1447 );
1448 `endif
1451 /////////////////////////////////////////////////////
1452 // Combinational Logic
1453 /////////////////////////////////////////////////////
1455 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
1456 // Select between buffered and live data from register file
1457 assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
1458 assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
1459 `endif
1460 `ifdef LM32_EBR_REGISTER_FILE
1461 `else
1462 // Register file read ports
1463 assign reg_data_0 = registers[read_idx_0_d];
1464 assign reg_data_1 = registers[read_idx_1_d];
1465 `endif
1467 // Detect read-after-write hazzards
1468 assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == `TRUE);
1469 assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == `TRUE);
1470 assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == `TRUE);
1471 assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == `TRUE);
1472 assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == `TRUE);
1473 assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == `TRUE);
1475 // Interlock detection - Raise an interlock for RAW hazzards
1476 always @(*)
1477 begin
1478 if ( ( (x_bypass_enable_x == `FALSE)
1479 && ( ((read_enable_0_d == `TRUE) && (raw_x_0 == `TRUE))
1480 || ((read_enable_1_d == `TRUE) && (raw_x_1 == `TRUE))
1481 )
1482 )
1483 || ( (m_bypass_enable_m == `FALSE)
1484 && ( ((read_enable_0_d == `TRUE) && (raw_m_0 == `TRUE))
1485 || ((read_enable_1_d == `TRUE) && (raw_m_1 == `TRUE))
1486 )
1487 )
1488 )
1489 interlock = `TRUE;
1490 else
1491 interlock = `FALSE;
1492 end
1494 // Bypass for reg port 0
1495 always @(*)
1496 begin
1497 if (raw_x_0 == `TRUE)
1498 bypass_data_0 = x_result;
1499 else if (raw_m_0 == `TRUE)
1500 bypass_data_0 = m_result;
1501 else if (raw_w_0 == `TRUE)
1502 bypass_data_0 = w_result;
1503 else
1504 bypass_data_0 = reg_data_0;
1505 end
1507 // Bypass for reg port 1
1508 always @(*)
1509 begin
1510 if (raw_x_1 == `TRUE)
1511 bypass_data_1 = x_result;
1512 else if (raw_m_1 == `TRUE)
1513 bypass_data_1 = m_result;
1514 else if (raw_w_1 == `TRUE)
1515 bypass_data_1 = w_result;
1516 else
1517 bypass_data_1 = reg_data_1;
1518 end
1520 /*----------------------------------------------------------------------
1521 Branch prediction is performed in D stage of pipeline. Only PC-relative
1522 branches are predicted: forward-pointing conditional branches are not-
1523 taken, while backward-pointing conditional branches are taken.
1524 Unconditional branches are always predicted taken!
1525 ----------------------------------------------------------------------*/
1526 assign branch_predict_d = bi_unconditional | bi_conditional;
1527 assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
1529 // Compute branch target address: Branch PC PLUS Offset
1530 assign branch_target_d = pc_d + branch_offset_d;
1532 // Compute fetch address. Address of instruction sequentially after the
1533 // branch if branch is not taken. Target address of branch is branch is
1534 // taken
1535 assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
1537 // D stage result selection
1538 always @(*)
1539 begin
1540 d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0;
1541 case (d_result_sel_1_d)
1542 `LM32_D_RESULT_SEL_1_ZERO: d_result_1 = {`LM32_WORD_WIDTH{1'b0}};
1543 `LM32_D_RESULT_SEL_1_REG_1: d_result_1 = bypass_data_1;
1544 `LM32_D_RESULT_SEL_1_IMMEDIATE: d_result_1 = immediate_d;
1545 default: d_result_1 = {`LM32_WORD_WIDTH{1'bx}};
1546 endcase
1547 end
1549 `ifdef CFG_USER_ENABLED
1550 // Operands for user-defined instructions
1551 assign user_operand_0 = operand_0_x;
1552 assign user_operand_1 = operand_1_x;
1553 `endif
1555 `ifdef CFG_SIGN_EXTEND_ENABLED
1556 // Sign-extension
1557 assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
1558 assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
1559 assign sext_result_x = size_x == `LM32_SIZE_BYTE ? sextb_result_x : sexth_result_x;
1560 `endif
1562 `ifdef LM32_NO_BARREL_SHIFT
1563 // Only single bit shift operations are supported when barrel-shifter isn't implemented
1564 assign shifter_result_x = {operand_0_x[`LM32_WORD_WIDTH-1] & sign_extend_x, operand_0_x[`LM32_WORD_WIDTH-1:1]};
1565 `endif
1567 // Condition evaluation
1568 assign cmp_zero = operand_0_x == operand_1_x;
1569 assign cmp_negative = adder_result_x[`LM32_WORD_WIDTH-1];
1570 assign cmp_overflow = adder_overflow_x;
1571 assign cmp_carry_n = adder_carry_n_x;
1572 always @(*)
1573 begin
1574 case (condition_x)
1575 `LM32_CONDITION_U1: condition_met_x = `TRUE;
1576 `LM32_CONDITION_U2: condition_met_x = `TRUE;
1577 `LM32_CONDITION_E: condition_met_x = cmp_zero;
1578 `LM32_CONDITION_NE: condition_met_x = !cmp_zero;
1579 `LM32_CONDITION_G: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
1580 `LM32_CONDITION_GU: condition_met_x = cmp_carry_n && !cmp_zero;
1581 `LM32_CONDITION_GE: condition_met_x = cmp_negative == cmp_overflow;
1582 `LM32_CONDITION_GEU: condition_met_x = cmp_carry_n;
1583 default: condition_met_x = 1'bx;
1584 endcase
1585 end
1587 // X stage result selection
1588 always @(*)
1589 begin
1590 x_result = x_result_sel_add_x ? adder_result_x
1591 : x_result_sel_csr_x ? csr_read_data_x
1592 `ifdef CFG_SIGN_EXTEND_ENABLED
1593 : x_result_sel_sext_x ? sext_result_x
1594 `endif
1595 `ifdef CFG_USER_ENABLED
1596 : x_result_sel_user_x ? user_result
1597 `endif
1598 `ifdef LM32_NO_BARREL_SHIFT
1599 : x_result_sel_shift_x ? shifter_result_x
1600 `endif
1601 `ifdef LM32_MC_ARITHMETIC_ENABLED
1602 : x_result_sel_mc_arith_x ? mc_result_x
1603 `endif
1604 : logic_result_x;
1605 end
1607 // M stage result selection
1608 always @(*)
1609 begin
1610 m_result = m_result_sel_compare_m ? {{`LM32_WORD_WIDTH-1{1'b0}}, condition_met_m}
1611 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
1612 : m_result_sel_shift_m ? shifter_result_m
1613 `endif
1614 : operand_m;
1615 end
1617 // W stage result selection
1618 always @(*)
1619 begin
1620 w_result = w_result_sel_load_w ? load_data_w
1621 `ifdef CFG_PL_MULTIPLY_ENABLED
1622 : w_result_sel_mul_w ? multiplier_result_w
1623 `endif
1624 : operand_w;
1625 end
1627 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
1628 // Indicate when a branch should be taken in X stage
1629 assign branch_taken_x = (stall_x == `FALSE)
1630 && ( (branch_x == `TRUE)
1631 && ((condition_x == `LM32_CONDITION_U1) || (condition_x == `LM32_CONDITION_U2))
1632 && (valid_x == `TRUE)
1633 && (branch_predict_x == `FALSE)
1634 );
1635 `endif
1637 // Indicate when a branch should be taken in M stage (exceptions are a type of branch)
1638 assign branch_taken_m = (stall_m == `FALSE)
1639 && ( ( (branch_m == `TRUE)
1640 && (valid_m == `TRUE)
1641 && ( ( (condition_met_m == `TRUE)
1642 && (branch_predict_taken_m == `FALSE)
1643 )
1644 || ( (condition_met_m == `FALSE)
1645 && (branch_predict_m == `TRUE)
1646 && (branch_predict_taken_m == `TRUE)
1647 )
1648 )
1649 )
1650 || (exception_m == `TRUE)
1651 );
1653 // Indicate when a branch in M stage is mispredicted as being taken
1654 assign branch_mispredict_taken_m = (condition_met_m == `FALSE)
1655 && (branch_predict_m == `TRUE)
1656 && (branch_predict_taken_m == `TRUE);
1658 // Indicate when a branch in M stage will cause flush in X stage
1659 assign branch_flushX_m = (stall_m == `FALSE)
1660 && ( ( (branch_m == `TRUE)
1661 && (valid_m == `TRUE)
1662 && ( (condition_met_m == `TRUE)
1663 || ( (condition_met_m == `FALSE)
1664 && (branch_predict_m == `TRUE)
1665 && (branch_predict_taken_m == `TRUE)
1666 )
1667 )
1668 )
1669 || (exception_m == `TRUE)
1670 );
1672 // Generate signal that will kill instructions in each pipeline stage when necessary
1673 assign kill_f = ( (valid_d == `TRUE)
1674 && (branch_predict_taken_d == `TRUE)
1675 )
1676 || (branch_taken_m == `TRUE)
1677 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
1678 || (branch_taken_x == `TRUE)
1679 `endif
1680 `ifdef CFG_ICACHE_ENABLED
1681 || (icache_refill_request == `TRUE)
1682 `endif
1683 `ifdef CFG_DCACHE_ENABLED
1684 || (dcache_refill_request == `TRUE)
1685 `endif
1686 ;
1687 assign kill_d = (branch_taken_m == `TRUE)
1688 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
1689 || (branch_taken_x == `TRUE)
1690 `endif
1691 `ifdef CFG_ICACHE_ENABLED
1692 || (icache_refill_request == `TRUE)
1693 `endif
1694 `ifdef CFG_DCACHE_ENABLED
1695 || (dcache_refill_request == `TRUE)
1696 `endif
1697 ;
1698 assign kill_x = (branch_flushX_m == `TRUE)
1699 `ifdef CFG_DCACHE_ENABLED
1700 || (dcache_refill_request == `TRUE)
1701 `endif
1702 ;
1703 assign kill_m = `FALSE
1704 `ifdef CFG_DCACHE_ENABLED
1705 || (dcache_refill_request == `TRUE)
1706 `endif
1707 ;
1708 assign kill_w = `FALSE
1709 `ifdef CFG_DCACHE_ENABLED
1710 || (dcache_refill_request == `TRUE)
1711 `endif
1712 ;
1714 // Exceptions
1716 `ifdef CFG_DEBUG_ENABLED
1717 assign breakpoint_exception = ( ( (break_x == `TRUE)
1718 || (bp_match == `TRUE)
1719 )
1720 && (valid_x == `TRUE)
1721 )
1722 `ifdef CFG_JTAG_ENABLED
1723 || (jtag_break == `TRUE)
1724 `endif
1725 ;
1726 `endif
1728 `ifdef CFG_DEBUG_ENABLED
1729 assign watchpoint_exception = wp_match == `TRUE;
1730 `endif
1732 `ifdef CFG_BUS_ERRORS_ENABLED
1733 assign instruction_bus_error_exception = ( (bus_error_x == `TRUE)
1734 && (valid_x == `TRUE)
1735 );
1736 assign data_bus_error_exception = data_bus_error_seen == `TRUE;
1737 `endif
1739 `ifdef CFG_MC_DIVIDE_ENABLED
1740 assign divide_by_zero_exception = divide_by_zero_x == `TRUE;
1741 `endif
1743 assign system_call_exception = ( (scall_x == `TRUE)
1744 `ifdef CFG_BUS_ERRORS_ENABLED
1745 && (valid_x == `TRUE)
1746 `endif
1747 );
1749 `ifdef CFG_DEBUG_ENABLED
1750 assign debug_exception_x = (breakpoint_exception == `TRUE)
1751 || (watchpoint_exception == `TRUE)
1752 ;
1754 assign non_debug_exception_x = (system_call_exception == `TRUE)
1755 `ifdef CFG_JTAG_ENABLED
1756 || (reset_exception == `TRUE)
1757 `endif
1758 `ifdef CFG_BUS_ERRORS_ENABLED
1759 || (instruction_bus_error_exception == `TRUE)
1760 || (data_bus_error_exception == `TRUE)
1761 `endif
1762 `ifdef CFG_MC_DIVIDE_ENABLED
1763 || (divide_by_zero_exception == `TRUE)
1764 `endif
1765 `ifdef CFG_INTERRUPTS_ENABLED
1766 || ( (interrupt_exception == `TRUE)
1767 `ifdef LM32_SINGLE_STEP_ENABLED
1768 && (dc_ss == `FALSE)
1769 `endif
1770 `ifdef CFG_BUS_ERRORS_ENABLED
1771 && (store_q_m == `FALSE)
1772 && (D_CYC_O == `FALSE)
1773 `endif
1774 )
1775 `endif
1776 ;
1778 assign exception_x = (debug_exception_x == `TRUE) || (non_debug_exception_x == `TRUE);
1779 `else
1780 assign exception_x = (system_call_exception == `TRUE)
1781 `ifdef CFG_BUS_ERRORS_ENABLED
1782 || (instruction_bus_error_exception == `TRUE)
1783 || (data_bus_error_exception == `TRUE)
1784 `endif
1785 `ifdef CFG_MC_DIVIDE_ENABLED
1786 || (divide_by_zero_exception == `TRUE)
1787 `endif
1788 `ifdef CFG_INTERRUPTS_ENABLED
1789 || ( (interrupt_exception == `TRUE)
1790 `ifdef LM32_SINGLE_STEP_ENABLED
1791 && (dc_ss == `FALSE)
1792 `endif
1793 `ifdef CFG_BUS_ERRORS_ENABLED
1794 && (store_q_m == `FALSE)
1795 && (D_CYC_O == `FALSE)
1796 `endif
1797 )
1798 `endif
1799 ;
1800 `endif
1802 // Exception ID
1803 always @(*)
1804 begin
1805 `ifdef CFG_DEBUG_ENABLED
1806 `ifdef CFG_JTAG_ENABLED
1807 if (reset_exception == `TRUE)
1808 eid_x = `LM32_EID_RESET;
1809 else
1810 `endif
1811 `ifdef CFG_BUS_ERRORS_ENABLED
1812 if (data_bus_error_exception == `TRUE)
1813 eid_x = `LM32_EID_DATA_BUS_ERROR;
1814 else
1815 `endif
1816 if (breakpoint_exception == `TRUE)
1817 eid_x = `LM32_EID_BREAKPOINT;
1818 else
1819 `endif
1820 `ifdef CFG_BUS_ERRORS_ENABLED
1821 if (data_bus_error_exception == `TRUE)
1822 eid_x = `LM32_EID_DATA_BUS_ERROR;
1823 else
1824 if (instruction_bus_error_exception == `TRUE)
1825 eid_x = `LM32_EID_INST_BUS_ERROR;
1826 else
1827 `endif
1828 `ifdef CFG_DEBUG_ENABLED
1829 if (watchpoint_exception == `TRUE)
1830 eid_x = `LM32_EID_WATCHPOINT;
1831 else
1832 `endif
1833 `ifdef CFG_MC_DIVIDE_ENABLED
1834 if (divide_by_zero_exception == `TRUE)
1835 eid_x = `LM32_EID_DIVIDE_BY_ZERO;
1836 else
1837 `endif
1838 `ifdef CFG_INTERRUPTS_ENABLED
1839 if ( (interrupt_exception == `TRUE)
1840 `ifdef LM32_SINGLE_STEP_ENABLED
1841 && (dc_ss == `FALSE)
1842 `endif
1843 )
1844 eid_x = `LM32_EID_INTERRUPT;
1845 else
1846 `endif
1847 eid_x = `LM32_EID_SCALL;
1848 end
1850 // Stall generation
1852 assign stall_a = (stall_f == `TRUE);
1854 assign stall_f = (stall_d == `TRUE);
1856 assign stall_d = (stall_x == `TRUE)
1857 || ( (interlock == `TRUE)
1858 && (kill_d == `FALSE)
1859 )
1860 || ( ( (eret_d == `TRUE)
1861 || (scall_d == `TRUE)
1862 || (bus_error_d == `TRUE)
1863 )
1864 && ( (load_q_x == `TRUE)
1865 || (load_q_m == `TRUE)
1866 || (store_q_x == `TRUE)
1867 || (store_q_m == `TRUE)
1868 || (D_CYC_O == `TRUE)
1869 )
1870 && (kill_d == `FALSE)
1871 )
1872 `ifdef CFG_DEBUG_ENABLED
1873 || ( ( (break_d == `TRUE)
1874 || (bret_d == `TRUE)
1875 )
1876 && ( (load_q_x == `TRUE)
1877 || (store_q_x == `TRUE)
1878 || (load_q_m == `TRUE)
1879 || (store_q_m == `TRUE)
1880 || (D_CYC_O == `TRUE)
1881 )
1882 && (kill_d == `FALSE)
1883 )
1884 `endif
1885 || ( (csr_write_enable_d == `TRUE)
1886 && (load_q_x == `TRUE)
1887 )
1888 ;
1890 assign stall_x = (stall_m == `TRUE)
1891 `ifdef LM32_MC_ARITHMETIC_ENABLED
1892 || ( (mc_stall_request_x == `TRUE)
1893 && (kill_x == `FALSE)
1894 )
1895 `endif
1896 `ifdef CFG_IROM_ENABLED
1897 // Stall load/store instruction in D stage if there is an ongoing store
1898 // operation to instruction ROM in M stage
1899 || ( (irom_stall_request_x == `TRUE)
1900 && ( (load_d == `TRUE)
1901 || (store_d == `TRUE)
1902 )
1903 )
1904 `endif
1905 ;
1907 assign stall_m = (stall_wb_load == `TRUE)
1908 `ifdef CFG_SIZE_OVER_SPEED
1909 || (D_CYC_O == `TRUE)
1910 `else
1911 || ( (D_CYC_O == `TRUE)
1912 && ( (store_m == `TRUE)
1913 /*
1914 Bug: Following loop does not allow interrupts to be services since
1915 either D_CYC_O or store_m is always high during entire duration of
1916 loop.
1917 L1: addi r1, r1, 1
1918 sw (r2,0), r1
1919 bi L1
1921 Introduce a single-cycle stall when a wishbone cycle is in progress
1922 and a new store instruction is in Execute stage and a interrupt
1923 exception has occured. This stall will ensure that D_CYC_O and
1924 store_m will both be low for one cycle.
1925 */
1926 || ((store_x == `TRUE) && (interrupt_exception == `TRUE))
1927 || (load_m == `TRUE)
1928 || (load_x == `TRUE)
1929 )
1930 )
1931 `endif
1932 `ifdef CFG_DCACHE_ENABLED
1933 || (dcache_stall_request == `TRUE) // Need to stall in case a taken branch is in M stage and data cache is only being flush, so wont be restarted
1934 `endif
1935 `ifdef CFG_ICACHE_ENABLED
1936 || (icache_stall_request == `TRUE) // Pipeline needs to be stalled otherwise branches may be lost
1937 || ((I_CYC_O == `TRUE) && ((branch_m == `TRUE) || (exception_m == `TRUE)))
1938 `else
1939 `ifdef CFG_IWB_ENABLED
1940 || (I_CYC_O == `TRUE)
1941 `endif
1942 `endif
1943 `ifdef CFG_USER_ENABLED
1944 || ( (user_valid == `TRUE) // Stall whole pipeline, rather than just X stage, where the instruction is, so we don't have to worry about exceptions (maybe)
1945 && (user_complete == `FALSE)
1946 )
1947 `endif
1948 ;
1950 // Qualify state changing control signals
1951 `ifdef LM32_MC_ARITHMETIC_ENABLED
1952 assign q_d = (valid_d == `TRUE) && (kill_d == `FALSE);
1953 `endif
1954 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
1955 assign shift_left_q_d = (shift_left_d == `TRUE) && (q_d == `TRUE);
1956 assign shift_right_q_d = (shift_right_d == `TRUE) && (q_d == `TRUE);
1957 `endif
1958 `ifdef CFG_MC_MULTIPLY_ENABLED
1959 assign multiply_q_d = (multiply_d == `TRUE) && (q_d == `TRUE);
1960 `endif
1961 `ifdef CFG_MC_DIVIDE_ENABLED
1962 assign divide_q_d = (divide_d == `TRUE) && (q_d == `TRUE);
1963 assign modulus_q_d = (modulus_d == `TRUE) && (q_d == `TRUE);
1964 `endif
1965 assign q_x = (valid_x == `TRUE) && (kill_x == `FALSE);
1966 assign csr_write_enable_q_x = (csr_write_enable_x == `TRUE) && (q_x == `TRUE);
1967 assign eret_q_x = (eret_x == `TRUE) && (q_x == `TRUE);
1968 `ifdef CFG_DEBUG_ENABLED
1969 assign bret_q_x = (bret_x == `TRUE) && (q_x == `TRUE);
1970 `endif
1971 assign load_q_x = (load_x == `TRUE)
1972 && (q_x == `TRUE)
1973 `ifdef CFG_DEBUG_ENABLED
1974 && (bp_match == `FALSE)
1975 `endif
1976 ;
1977 assign store_q_x = (store_x == `TRUE)
1978 && (q_x == `TRUE)
1979 `ifdef CFG_DEBUG_ENABLED
1980 && (bp_match == `FALSE)
1981 `endif
1982 ;
1983 `ifdef CFG_USER_ENABLED
1984 assign user_valid = (x_result_sel_user_x == `TRUE) && (q_x == `TRUE);
1985 `endif
1986 assign q_m = (valid_m == `TRUE) && (kill_m == `FALSE) && (exception_m == `FALSE);
1987 assign load_q_m = (load_m == `TRUE) && (q_m == `TRUE);
1988 assign store_q_m = (store_m == `TRUE) && (q_m == `TRUE);
1989 `ifdef CFG_DEBUG_ENABLED
1990 assign debug_exception_q_w = ((debug_exception_w == `TRUE) && (valid_w == `TRUE));
1991 assign non_debug_exception_q_w = ((non_debug_exception_w == `TRUE) && (valid_w == `TRUE));
1992 `else
1993 assign exception_q_w = ((exception_w == `TRUE) && (valid_w == `TRUE));
1994 `endif
1995 // Don't qualify register write enables with kill, as the signal is needed early, and it doesn't matter if the instruction is killed (except for the actual write - but that is handled separately)
1996 assign write_enable_q_x = (write_enable_x == `TRUE) && (valid_x == `TRUE) && (branch_flushX_m == `FALSE);
1997 assign write_enable_q_m = (write_enable_m == `TRUE) && (valid_m == `TRUE);
1998 assign write_enable_q_w = (write_enable_w == `TRUE) && (valid_w == `TRUE);
1999 // The enable that actually does write the registers needs to be qualified with kill
2000 assign reg_write_enable_q_w = (write_enable_w == `TRUE) && (kill_w == `FALSE) && (valid_w == `TRUE);
2002 // Configuration (CFG) CSR
2003 assign cfg = {
2004 `LM32_REVISION,
2005 watchpoints[3:0],
2006 breakpoints[3:0],
2007 interrupts[5:0],
2008 `ifdef CFG_JTAG_UART_ENABLED
2009 `TRUE,
2010 `else
2011 `FALSE,
2012 `endif
2013 `ifdef CFG_ROM_DEBUG_ENABLED
2014 `TRUE,
2015 `else
2016 `FALSE,
2017 `endif
2018 `ifdef CFG_HW_DEBUG_ENABLED
2019 `TRUE,
2020 `else
2021 `FALSE,
2022 `endif
2023 `ifdef CFG_DEBUG_ENABLED
2024 `TRUE,
2025 `else
2026 `FALSE,
2027 `endif
2028 `ifdef CFG_ICACHE_ENABLED
2029 `TRUE,
2030 `else
2031 `FALSE,
2032 `endif
2033 `ifdef CFG_DCACHE_ENABLED
2034 `TRUE,
2035 `else
2036 `FALSE,
2037 `endif
2038 `ifdef CFG_CYCLE_COUNTER_ENABLED
2039 `TRUE,
2040 `else
2041 `FALSE,
2042 `endif
2043 `ifdef CFG_USER_ENABLED
2044 `TRUE,
2045 `else
2046 `FALSE,
2047 `endif
2048 `ifdef CFG_SIGN_EXTEND_ENABLED
2049 `TRUE,
2050 `else
2051 `FALSE,
2052 `endif
2053 `ifdef LM32_BARREL_SHIFT_ENABLED
2054 `TRUE,
2055 `else
2056 `FALSE,
2057 `endif
2058 `ifdef CFG_MC_DIVIDE_ENABLED
2059 `TRUE,
2060 `else
2061 `FALSE,
2062 `endif
2063 `ifdef LM32_MULTIPLY_ENABLED
2064 `TRUE
2065 `else
2066 `FALSE
2067 `endif
2068 };
2070 assign cfg2 = {
2071 30'b0,
2072 `ifdef CFG_IROM_ENABLED
2073 `TRUE,
2074 `else
2075 `FALSE,
2076 `endif
2077 `ifdef CFG_DRAM_ENABLED
2078 `TRUE
2079 `else
2080 `FALSE
2081 `endif
2082 };
2084 // Cache flush
2085 `ifdef CFG_ICACHE_ENABLED
2086 assign iflush = (csr_write_enable_d == `TRUE)
2087 && (csr_d == `LM32_CSR_ICC)
2088 && (stall_d == `FALSE)
2089 && (kill_d == `FALSE)
2090 && (valid_d == `TRUE);
2091 `endif
2092 `ifdef CFG_DCACHE_ENABLED
2093 assign dflush_x = (csr_write_enable_q_x == `TRUE)
2094 && (csr_x == `LM32_CSR_DCC);
2095 `endif
2097 // Extract CSR index
2098 assign csr_d = read_idx_0_d[`LM32_CSR_RNG];
2100 // CSR reads
2101 always @(*)
2102 begin
2103 case (csr_x)
2104 `ifdef CFG_INTERRUPTS_ENABLED
2105 `LM32_CSR_IE,
2106 `LM32_CSR_IM,
2107 `LM32_CSR_IP: csr_read_data_x = interrupt_csr_read_data_x;
2108 `endif
2109 `ifdef CFG_CYCLE_COUNTER_ENABLED
2110 `LM32_CSR_CC: csr_read_data_x = cc;
2111 `endif
2112 `LM32_CSR_CFG: csr_read_data_x = cfg;
2113 `LM32_CSR_EBA: csr_read_data_x = {eba, 8'h00};
2114 `ifdef CFG_DEBUG_ENABLED
2115 `LM32_CSR_DEBA: csr_read_data_x = {deba, 8'h00};
2116 `endif
2117 `ifdef CFG_JTAG_UART_ENABLED
2118 `LM32_CSR_JTX: csr_read_data_x = jtx_csr_read_data;
2119 `LM32_CSR_JRX: csr_read_data_x = jrx_csr_read_data;
2120 `endif
2121 `LM32_CSR_CFG2: csr_read_data_x = cfg2;
2123 default: csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
2124 endcase
2125 end
2127 /////////////////////////////////////////////////////
2128 // Sequential Logic
2129 /////////////////////////////////////////////////////
2131 // Exception Base Address (EBA) CSR
2132 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2133 begin
2134 if (rst_i == `TRUE)
2135 eba <= eba_reset[`LM32_PC_WIDTH+2-1:8];
2136 else
2137 begin
2138 if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE))
2139 eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
2140 `ifdef CFG_HW_DEBUG_ENABLED
2141 if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA))
2142 eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
2143 `endif
2144 end
2145 end
2147 `ifdef CFG_DEBUG_ENABLED
2148 // Debug Exception Base Address (DEBA) CSR
2149 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2150 begin
2151 if (rst_i == `TRUE)
2152 deba <= deba_reset[`LM32_PC_WIDTH+2-1:8];
2153 else
2154 begin
2155 if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE))
2156 deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
2157 `ifdef CFG_HW_DEBUG_ENABLED
2158 if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA))
2159 deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
2160 `endif
2161 end
2162 end
2163 `endif
2165 // Cycle Counter (CC) CSR
2166 `ifdef CFG_CYCLE_COUNTER_ENABLED
2167 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2168 begin
2169 if (rst_i == `TRUE)
2170 cc <= {`LM32_WORD_WIDTH{1'b0}};
2171 else
2172 cc <= cc + 1'b1;
2173 end
2174 `endif
2176 `ifdef CFG_BUS_ERRORS_ENABLED
2177 // Watch for data bus errors
2178 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2179 begin
2180 if (rst_i == `TRUE)
2181 data_bus_error_seen <= `FALSE;
2182 else
2183 begin
2184 // Set flag when bus error is detected
2185 if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE))
2186 data_bus_error_seen <= `TRUE;
2187 // Clear flag when exception is taken
2188 if ((exception_m == `TRUE) && (kill_m == `FALSE))
2189 data_bus_error_seen <= `FALSE;
2190 end
2191 end
2192 `endif
2194 // Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not
2196 `ifdef CFG_ICACHE_ENABLED
2197 `ifdef CFG_DCACHE_ENABLED
2198 always @(*)
2199 begin
2200 if ( (icache_refill_request == `TRUE)
2201 || (dcache_refill_request == `TRUE)
2202 )
2203 valid_a = `FALSE;
2204 else if ( (icache_restart_request == `TRUE)
2205 || (dcache_restart_request == `TRUE)
2206 )
2207 valid_a = `TRUE;
2208 else
2209 valid_a = !icache_refilling && !dcache_refilling;
2210 end
2211 `else
2212 always @(*)
2213 begin
2214 if (icache_refill_request == `TRUE)
2215 valid_a = `FALSE;
2216 else if (icache_restart_request == `TRUE)
2217 valid_a = `TRUE;
2218 else
2219 valid_a = !icache_refilling;
2220 end
2221 `endif
2222 `else
2223 `ifdef CFG_DCACHE_ENABLED
2224 always @(*)
2225 begin
2226 if (dcache_refill_request == `TRUE)
2227 valid_a = `FALSE;
2228 else if (dcache_restart_request == `TRUE)
2229 valid_a = `TRUE;
2230 else
2231 valid_a = !dcache_refilling;
2232 end
2233 `endif
2234 `endif
2236 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2237 begin
2238 if (rst_i == `TRUE)
2239 begin
2240 valid_f <= `FALSE;
2241 valid_d <= `FALSE;
2242 valid_x <= `FALSE;
2243 valid_m <= `FALSE;
2244 valid_w <= `FALSE;
2245 end
2246 else
2247 begin
2248 if ((kill_f == `TRUE) || (stall_a == `FALSE))
2249 `ifdef LM32_CACHE_ENABLED
2250 valid_f <= valid_a;
2251 `else
2252 valid_f <= `TRUE;
2253 `endif
2254 else if (stall_f == `FALSE)
2255 valid_f <= `FALSE;
2257 if (kill_d == `TRUE)
2258 valid_d <= `FALSE;
2259 else if (stall_f == `FALSE)
2260 valid_d <= valid_f & !kill_f;
2261 else if (stall_d == `FALSE)
2262 valid_d <= `FALSE;
2264 if (stall_d == `FALSE)
2265 valid_x <= valid_d & !kill_d;
2266 else if (kill_x == `TRUE)
2267 valid_x <= `FALSE;
2268 else if (stall_x == `FALSE)
2269 valid_x <= `FALSE;
2271 if (kill_m == `TRUE)
2272 valid_m <= `FALSE;
2273 else if (stall_x == `FALSE)
2274 valid_m <= valid_x & !kill_x;
2275 else if (stall_m == `FALSE)
2276 valid_m <= `FALSE;
2278 if (stall_m == `FALSE)
2279 valid_w <= valid_m & !kill_m;
2280 else
2281 valid_w <= `FALSE;
2282 end
2283 end
2285 // Microcode pipeline registers
2286 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2287 begin
2288 if (rst_i == `TRUE)
2289 begin
2290 `ifdef CFG_USER_ENABLED
2291 user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}};
2292 `endif
2293 operand_0_x <= {`LM32_WORD_WIDTH{1'b0}};
2294 operand_1_x <= {`LM32_WORD_WIDTH{1'b0}};
2295 store_operand_x <= {`LM32_WORD_WIDTH{1'b0}};
2296 branch_target_x <= {`LM32_WORD_WIDTH{1'b0}};
2297 x_result_sel_csr_x <= `FALSE;
2298 `ifdef LM32_MC_ARITHMETIC_ENABLED
2299 x_result_sel_mc_arith_x <= `FALSE;
2300 `endif
2301 `ifdef LM32_NO_BARREL_SHIFT
2302 x_result_sel_shift_x <= `FALSE;
2303 `endif
2304 `ifdef CFG_SIGN_EXTEND_ENABLED
2305 x_result_sel_sext_x <= `FALSE;
2306 `endif
2307 x_result_sel_logic_x <= `FALSE;
2308 `ifdef CFG_USER_ENABLED
2309 x_result_sel_user_x <= `FALSE;
2310 `endif
2311 x_result_sel_add_x <= `FALSE;
2312 m_result_sel_compare_x <= `FALSE;
2313 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2314 m_result_sel_shift_x <= `FALSE;
2315 `endif
2316 w_result_sel_load_x <= `FALSE;
2317 `ifdef CFG_PL_MULTIPLY_ENABLED
2318 w_result_sel_mul_x <= `FALSE;
2319 `endif
2320 x_bypass_enable_x <= `FALSE;
2321 m_bypass_enable_x <= `FALSE;
2322 write_enable_x <= `FALSE;
2323 write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}};
2324 csr_x <= {`LM32_CSR_WIDTH{1'b0}};
2325 load_x <= `FALSE;
2326 store_x <= `FALSE;
2327 size_x <= {`LM32_SIZE_WIDTH{1'b0}};
2328 sign_extend_x <= `FALSE;
2329 adder_op_x <= `FALSE;
2330 adder_op_x_n <= `FALSE;
2331 logic_op_x <= 4'h0;
2332 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2333 direction_x <= `FALSE;
2334 `endif
2335 `ifdef CFG_ROTATE_ENABLED
2336 rotate_x <= `FALSE;
2338 `endif
2339 branch_x <= `FALSE;
2340 branch_predict_x <= `FALSE;
2341 branch_predict_taken_x <= `FALSE;
2342 condition_x <= `LM32_CONDITION_U1;
2343 `ifdef CFG_DEBUG_ENABLED
2344 break_x <= `FALSE;
2345 `endif
2346 scall_x <= `FALSE;
2347 eret_x <= `FALSE;
2348 `ifdef CFG_DEBUG_ENABLED
2349 bret_x <= `FALSE;
2350 `endif
2351 `ifdef CFG_BUS_ERRORS_ENABLED
2352 bus_error_x <= `FALSE;
2353 data_bus_error_exception_m <= `FALSE;
2354 `endif
2355 csr_write_enable_x <= `FALSE;
2356 operand_m <= {`LM32_WORD_WIDTH{1'b0}};
2357 branch_target_m <= {`LM32_WORD_WIDTH{1'b0}};
2358 m_result_sel_compare_m <= `FALSE;
2359 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2360 m_result_sel_shift_m <= `FALSE;
2361 `endif
2362 w_result_sel_load_m <= `FALSE;
2363 `ifdef CFG_PL_MULTIPLY_ENABLED
2364 w_result_sel_mul_m <= `FALSE;
2365 `endif
2366 m_bypass_enable_m <= `FALSE;
2367 branch_m <= `FALSE;
2368 branch_predict_m <= `FALSE;
2369 branch_predict_taken_m <= `FALSE;
2370 exception_m <= `FALSE;
2371 load_m <= `FALSE;
2372 store_m <= `FALSE;
2373 write_enable_m <= `FALSE;
2374 write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}};
2375 condition_met_m <= `FALSE;
2376 `ifdef CFG_DCACHE_ENABLED
2377 dflush_m <= `FALSE;
2378 `endif
2379 `ifdef CFG_DEBUG_ENABLED
2380 debug_exception_m <= `FALSE;
2381 non_debug_exception_m <= `FALSE;
2382 `endif
2383 operand_w <= {`LM32_WORD_WIDTH{1'b0}};
2384 w_result_sel_load_w <= `FALSE;
2385 `ifdef CFG_PL_MULTIPLY_ENABLED
2386 w_result_sel_mul_w <= `FALSE;
2387 `endif
2388 write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}};
2389 write_enable_w <= `FALSE;
2390 `ifdef CFG_DEBUG_ENABLED
2391 debug_exception_w <= `FALSE;
2392 non_debug_exception_w <= `FALSE;
2393 `else
2394 exception_w <= `FALSE;
2395 `endif
2396 `ifdef CFG_BUS_ERRORS_ENABLED
2397 memop_pc_w <= {`LM32_PC_WIDTH{1'b0}};
2398 `endif
2399 end
2400 else
2401 begin
2402 // D/X stage registers
2404 if (stall_x == `FALSE)
2405 begin
2406 `ifdef CFG_USER_ENABLED
2407 user_opcode <= user_opcode_d;
2408 `endif
2409 operand_0_x <= d_result_0;
2410 operand_1_x <= d_result_1;
2411 store_operand_x <= bypass_data_1;
2412 branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d;
2413 x_result_sel_csr_x <= x_result_sel_csr_d;
2414 `ifdef LM32_MC_ARITHMETIC_ENABLED
2415 x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
2416 `endif
2417 `ifdef LM32_NO_BARREL_SHIFT
2418 x_result_sel_shift_x <= x_result_sel_shift_d;
2419 `endif
2420 `ifdef CFG_SIGN_EXTEND_ENABLED
2421 x_result_sel_sext_x <= x_result_sel_sext_d;
2422 `endif
2423 x_result_sel_logic_x <= x_result_sel_logic_d;
2424 `ifdef CFG_USER_ENABLED
2425 x_result_sel_user_x <= x_result_sel_user_d;
2426 `endif
2427 x_result_sel_add_x <= x_result_sel_add_d;
2428 m_result_sel_compare_x <= m_result_sel_compare_d;
2429 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2430 m_result_sel_shift_x <= m_result_sel_shift_d;
2431 `endif
2432 w_result_sel_load_x <= w_result_sel_load_d;
2433 `ifdef CFG_PL_MULTIPLY_ENABLED
2434 w_result_sel_mul_x <= w_result_sel_mul_d;
2435 `endif
2436 x_bypass_enable_x <= x_bypass_enable_d;
2437 m_bypass_enable_x <= m_bypass_enable_d;
2438 load_x <= load_d;
2439 store_x <= store_d;
2440 branch_x <= branch_d;
2441 branch_predict_x <= branch_predict_d;
2442 branch_predict_taken_x <= branch_predict_taken_d;
2443 write_idx_x <= write_idx_d;
2444 csr_x <= csr_d;
2445 size_x <= size_d;
2446 sign_extend_x <= sign_extend_d;
2447 adder_op_x <= adder_op_d;
2448 adder_op_x_n <= ~adder_op_d;
2449 logic_op_x <= logic_op_d;
2450 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2451 direction_x <= direction_d;
2452 `endif
2453 `ifdef CFG_ROTATE_ENABLED
2454 rotate_x <= rotate_d;
2455 `endif
2456 condition_x <= condition_d;
2457 csr_write_enable_x <= csr_write_enable_d;
2458 `ifdef CFG_DEBUG_ENABLED
2459 break_x <= break_d;
2460 `endif
2461 scall_x <= scall_d;
2462 `ifdef CFG_BUS_ERRORS_ENABLED
2463 bus_error_x <= bus_error_d;
2464 `endif
2465 eret_x <= eret_d;
2466 `ifdef CFG_DEBUG_ENABLED
2467 bret_x <= bret_d;
2468 `endif
2469 write_enable_x <= write_enable_d;
2470 end
2472 // X/M stage registers
2474 if (stall_m == `FALSE)
2475 begin
2476 operand_m <= x_result;
2477 m_result_sel_compare_m <= m_result_sel_compare_x;
2478 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2479 m_result_sel_shift_m <= m_result_sel_shift_x;
2480 `endif
2481 if (exception_x == `TRUE)
2482 begin
2483 w_result_sel_load_m <= `FALSE;
2484 `ifdef CFG_PL_MULTIPLY_ENABLED
2485 w_result_sel_mul_m <= `FALSE;
2486 `endif
2487 end
2488 else
2489 begin
2490 w_result_sel_load_m <= w_result_sel_load_x;
2491 `ifdef CFG_PL_MULTIPLY_ENABLED
2492 w_result_sel_mul_m <= w_result_sel_mul_x;
2493 `endif
2494 end
2495 m_bypass_enable_m <= m_bypass_enable_x;
2496 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2497 `endif
2498 load_m <= load_x;
2499 store_m <= store_x;
2500 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
2501 branch_m <= branch_x && !branch_taken_x;
2502 `else
2503 branch_m <= branch_x;
2504 branch_predict_m <= branch_predict_x;
2505 branch_predict_taken_m <= branch_predict_taken_x;
2506 `endif
2507 `ifdef CFG_DEBUG_ENABLED
2508 // Data bus errors are generated by the wishbone and are
2509 // made known to the processor only in next cycle (as a
2510 // non-debug exception). A break instruction can be seen
2511 // in same cycle (causing a debug exception). Handle non
2512 // -debug exception first!
2513 if (non_debug_exception_x == `TRUE)
2514 write_idx_m <= `LM32_EA_REG;
2515 else if (debug_exception_x == `TRUE)
2516 write_idx_m <= `LM32_BA_REG;
2517 else
2518 write_idx_m <= write_idx_x;
2519 `else
2520 if (exception_x == `TRUE)
2521 write_idx_m <= `LM32_EA_REG;
2522 else
2523 write_idx_m <= write_idx_x;
2524 `endif
2525 condition_met_m <= condition_met_x;
2526 `ifdef CFG_DEBUG_ENABLED
2527 if (exception_x == `TRUE)
2528 if ((dc_re == `TRUE)
2529 `ifdef CFG_ALTERNATE_EBA
2530 || (at_debug == `TRUE)
2531 `endif
2532 || ((debug_exception_x == `TRUE)
2533 && (non_debug_exception_x == `FALSE)))
2534 branch_target_m <= {deba, eid_x, {3{1'b0}}};
2535 else
2536 branch_target_m <= {eba, eid_x, {3{1'b0}}};
2537 else
2538 branch_target_m <= branch_target_x;
2539 `else
2540 branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
2541 `endif
2542 `ifdef CFG_TRACE_ENABLED
2543 eid_m <= eid_x;
2544 `endif
2545 `ifdef CFG_DCACHE_ENABLED
2546 dflush_m <= dflush_x;
2547 `endif
2548 eret_m <= eret_q_x;
2549 `ifdef CFG_DEBUG_ENABLED
2550 bret_m <= bret_q_x;
2551 `endif
2552 write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x;
2553 `ifdef CFG_DEBUG_ENABLED
2554 debug_exception_m <= debug_exception_x;
2555 non_debug_exception_m <= non_debug_exception_x;
2556 `endif
2557 end
2559 // State changing regs
2560 if (stall_m == `FALSE)
2561 begin
2562 if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
2563 exception_m <= `TRUE;
2564 else
2565 exception_m <= `FALSE;
2566 `ifdef CFG_BUS_ERRORS_ENABLED
2567 data_bus_error_exception_m <= (data_bus_error_exception == `TRUE)
2568 `ifdef CFG_DEBUG_ENABLED
2569 && (reset_exception == `FALSE)
2570 `endif
2571 ;
2572 `endif
2573 end
2575 // M/W stage registers
2576 `ifdef CFG_BUS_ERRORS_ENABLED
2577 operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
2578 `else
2579 operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result;
2580 `endif
2581 w_result_sel_load_w <= w_result_sel_load_m;
2582 `ifdef CFG_PL_MULTIPLY_ENABLED
2583 w_result_sel_mul_w <= w_result_sel_mul_m;
2584 `endif
2585 write_idx_w <= write_idx_m;
2586 `ifdef CFG_TRACE_ENABLED
2587 eid_w <= eid_m;
2588 eret_w <= eret_m;
2589 `ifdef CFG_DEBUG_ENABLED
2590 bret_w <= bret_m;
2591 `endif
2592 `endif
2593 write_enable_w <= write_enable_m;
2594 `ifdef CFG_DEBUG_ENABLED
2595 debug_exception_w <= debug_exception_m;
2596 non_debug_exception_w <= non_debug_exception_m;
2597 `else
2598 exception_w <= exception_m;
2599 `endif
2600 `ifdef CFG_BUS_ERRORS_ENABLED
2601 if ( (stall_m == `FALSE)
2602 && (data_bus_error_exception == `FALSE)
2603 && ( (load_q_m == `TRUE)
2604 || (store_q_m == `TRUE)
2605 )
2606 )
2607 memop_pc_w <= pc_m;
2608 `endif
2609 end
2610 end
2612 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
2613 // Buffer data read from register file, in case a stall occurs, and watch for
2614 // any writes to the modified registers
2615 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2616 begin
2617 if (rst_i == `TRUE)
2618 begin
2619 use_buf <= `FALSE;
2620 reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}};
2621 reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}};
2622 end
2623 else
2624 begin
2625 if (stall_d == `FALSE)
2626 use_buf <= `FALSE;
2627 else if (use_buf == `FALSE)
2628 begin
2629 reg_data_buf_0 <= reg_data_live_0;
2630 reg_data_buf_1 <= reg_data_live_1;
2631 use_buf <= `TRUE;
2632 end
2633 if (reg_write_enable_q_w == `TRUE)
2634 begin
2635 if (write_idx_w == read_idx_0_d)
2636 reg_data_buf_0 <= w_result;
2637 if (write_idx_w == read_idx_1_d)
2638 reg_data_buf_1 <= w_result;
2639 end
2640 end
2641 end
2642 `endif
2644 `ifdef LM32_EBR_REGISTER_FILE
2645 `else
2646 // Register file write port
2647 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2648 begin
2649 if (rst_i == `TRUE) begin
2650 registers[0] <= {`LM32_WORD_WIDTH{1'b0}};
2651 registers[1] <= {`LM32_WORD_WIDTH{1'b0}};
2652 registers[2] <= {`LM32_WORD_WIDTH{1'b0}};
2653 registers[3] <= {`LM32_WORD_WIDTH{1'b0}};
2654 registers[4] <= {`LM32_WORD_WIDTH{1'b0}};
2655 registers[5] <= {`LM32_WORD_WIDTH{1'b0}};
2656 registers[6] <= {`LM32_WORD_WIDTH{1'b0}};
2657 registers[7] <= {`LM32_WORD_WIDTH{1'b0}};
2658 registers[8] <= {`LM32_WORD_WIDTH{1'b0}};
2659 registers[9] <= {`LM32_WORD_WIDTH{1'b0}};
2660 registers[10] <= {`LM32_WORD_WIDTH{1'b0}};
2661 registers[11] <= {`LM32_WORD_WIDTH{1'b0}};
2662 registers[12] <= {`LM32_WORD_WIDTH{1'b0}};
2663 registers[13] <= {`LM32_WORD_WIDTH{1'b0}};
2664 registers[14] <= {`LM32_WORD_WIDTH{1'b0}};
2665 registers[15] <= {`LM32_WORD_WIDTH{1'b0}};
2666 registers[16] <= {`LM32_WORD_WIDTH{1'b0}};
2667 registers[17] <= {`LM32_WORD_WIDTH{1'b0}};
2668 registers[18] <= {`LM32_WORD_WIDTH{1'b0}};
2669 registers[19] <= {`LM32_WORD_WIDTH{1'b0}};
2670 registers[20] <= {`LM32_WORD_WIDTH{1'b0}};
2671 registers[21] <= {`LM32_WORD_WIDTH{1'b0}};
2672 registers[22] <= {`LM32_WORD_WIDTH{1'b0}};
2673 registers[23] <= {`LM32_WORD_WIDTH{1'b0}};
2674 registers[24] <= {`LM32_WORD_WIDTH{1'b0}};
2675 registers[25] <= {`LM32_WORD_WIDTH{1'b0}};
2676 registers[26] <= {`LM32_WORD_WIDTH{1'b0}};
2677 registers[27] <= {`LM32_WORD_WIDTH{1'b0}};
2678 registers[28] <= {`LM32_WORD_WIDTH{1'b0}};
2679 registers[29] <= {`LM32_WORD_WIDTH{1'b0}};
2680 registers[30] <= {`LM32_WORD_WIDTH{1'b0}};
2681 registers[31] <= {`LM32_WORD_WIDTH{1'b0}};
2682 end
2683 else begin
2684 if (reg_write_enable_q_w == `TRUE)
2685 registers[write_idx_w] <= w_result;
2686 end
2687 end
2688 `endif
2690 `ifdef CFG_TRACE_ENABLED
2691 // PC tracing logic
2692 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2693 begin
2694 if (rst_i == `TRUE)
2695 begin
2696 trace_pc_valid <= `FALSE;
2697 trace_pc <= {`LM32_PC_WIDTH{1'b0}};
2698 trace_exception <= `FALSE;
2699 trace_eid <= `LM32_EID_RESET;
2700 trace_eret <= `FALSE;
2701 `ifdef CFG_DEBUG_ENABLED
2702 trace_bret <= `FALSE;
2703 `endif
2704 pc_c <= `CFG_EBA_RESET/4;
2705 end
2706 else
2707 begin
2708 trace_pc_valid <= `FALSE;
2709 // Has an exception occured
2710 `ifdef CFG_DEBUG_ENABLED
2711 if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE))
2712 `else
2713 if (exception_q_w == `TRUE)
2714 `endif
2715 begin
2716 trace_exception <= `TRUE;
2717 trace_pc_valid <= `TRUE;
2718 trace_pc <= pc_w;
2719 trace_eid <= eid_w;
2720 end
2721 else
2722 trace_exception <= `FALSE;
2724 if ((valid_w == `TRUE) && (!kill_w))
2725 begin
2726 // An instruction is commiting. Determine if it is non-sequential
2727 if (pc_c + 1'b1 != pc_w)
2728 begin
2729 // Non-sequential instruction
2730 trace_pc_valid <= `TRUE;
2731 trace_pc <= pc_w;
2732 end
2733 // Record PC so we can determine if next instruction is sequential or not
2734 pc_c <= pc_w;
2735 // Indicate if it was an eret/bret instruction
2736 trace_eret <= eret_w;
2737 `ifdef CFG_DEBUG_ENABLED
2738 trace_bret <= bret_w;
2739 `endif
2740 end
2741 else
2742 begin
2743 trace_eret <= `FALSE;
2744 `ifdef CFG_DEBUG_ENABLED
2745 trace_bret <= `FALSE;
2746 `endif
2747 end
2748 end
2749 end
2750 `endif
2752 /////////////////////////////////////////////////////
2753 // Behavioural Logic
2754 /////////////////////////////////////////////////////
2756 // synthesis translate_off
2758 // Reset register 0. Only needed for simulation.
2759 initial
2760 begin
2761 `ifdef LM32_EBR_REGISTER_FILE
2762 reg_0.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
2763 reg_1.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
2764 `else
2765 registers[0] = {`LM32_WORD_WIDTH{1'b0}};
2766 `endif
2767 end
2769 // synthesis translate_on
2771 endmodule