Sat, 06 Aug 2011 01:33:43 +0100
Update documents for LM32 V3.8
1 // ==================================================================
2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
3 // ------------------------------------------------------------------
4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
5 // ALL RIGHTS RESERVED
6 // ------------------------------------------------------------------
7 //
8 // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
9 //
10 // Permission:
11 //
12 // Lattice Semiconductor grants permission to use this code
13 // pursuant to the terms of the Lattice Semiconductor Corporation
14 // Open Source License Agreement.
15 //
16 // Disclaimer:
17 //
18 // Lattice Semiconductor provides no warranty regarding the use or
19 // functionality of this code. It is the user's responsibility to
20 // verify the user’s design for consistency and functionality through
21 // the use of formal verification methods.
22 //
23 // --------------------------------------------------------------------
24 //
25 // Lattice Semiconductor Corporation
26 // 5555 NE Moore Court
27 // Hillsboro, OR 97214
28 // U.S.A
29 //
30 // TEL: 1-800-Lattice (USA and Canada)
31 // 503-286-8001 (other locations)
32 //
33 // web: http://www.latticesemi.com/
34 // email: techsupport@latticesemi.com
35 //
36 // --------------------------------------------------------------------
37 // FILE DETAILS
38 // Project : LatticeMico32
39 // File : lm32_dcache.v
40 // Title : Data cache
41 // Dependencies : lm32_include.v
42 // Version : 6.1.17
43 // : Initial Release
44 // Version : 7.0SP2, 3.0
45 // : No Change
46 // Version : 3.1
47 // : Support for user-selected resource usage when implementing
48 // : cache memory. Additional parameters must be defined when
49 // : invoking lm32_ram.v
50 // =============================================================================
52 `include "lm32_include.v"
54 `ifdef CFG_DCACHE_ENABLED
56 `define LM32_DC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb
57 `define LM32_DC_ADDR_SET_RNG addr_set_msb:addr_set_lsb
58 `define LM32_DC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb
59 `define LM32_DC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb
61 `define LM32_DC_TMEM_ADDR_WIDTH addr_set_width
62 `define LM32_DC_TMEM_ADDR_RNG (`LM32_DC_TMEM_ADDR_WIDTH-1):0
63 `define LM32_DC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width)
64 `define LM32_DC_DMEM_ADDR_RNG (`LM32_DC_DMEM_ADDR_WIDTH-1):0
66 `define LM32_DC_TAGS_WIDTH (addr_tag_width+1)
67 `define LM32_DC_TAGS_RNG (`LM32_DC_TAGS_WIDTH-1):0
68 `define LM32_DC_TAGS_TAG_RNG (`LM32_DC_TAGS_WIDTH-1):1
69 `define LM32_DC_TAGS_VALID_RNG 0
71 `define LM32_DC_STATE_RNG 2:0
72 `define LM32_DC_STATE_FLUSH 3'b001
73 `define LM32_DC_STATE_CHECK 3'b010
74 `define LM32_DC_STATE_REFILL 3'b100
76 /////////////////////////////////////////////////////
77 // Module interface
78 /////////////////////////////////////////////////////
80 module lm32_dcache (
81 // ----- Inputs -----
82 clk_i,
83 rst_i,
84 stall_a,
85 stall_x,
86 stall_m,
87 address_x,
88 address_m,
89 load_q_m,
90 store_q_m,
91 store_data,
92 store_byte_select,
93 refill_ready,
94 refill_data,
95 dflush,
96 // ----- Outputs -----
97 stall_request,
98 restart_request,
99 refill_request,
100 refill_address,
101 refilling,
102 load_data
103 );
105 /////////////////////////////////////////////////////
106 // Parameters
107 /////////////////////////////////////////////////////
109 parameter associativity = 1; // Associativity of the cache (Number of ways)
110 parameter sets = 512; // Number of sets
111 parameter bytes_per_line = 16; // Number of bytes per cache line
112 parameter base_address = 0; // Base address of cachable memory
113 parameter limit = 0; // Limit (highest address) of cachable memory
115 localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
116 localparam addr_set_width = clogb2(sets)-1;
117 localparam addr_offset_lsb = 2;
118 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
119 localparam addr_set_lsb = (addr_offset_msb+1);
120 localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
121 localparam addr_tag_lsb = (addr_set_msb+1);
122 localparam addr_tag_msb = clogb2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS)-1;
123 localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
125 /////////////////////////////////////////////////////
126 // Inputs
127 /////////////////////////////////////////////////////
129 input clk_i; // Clock
130 input rst_i; // Reset
132 input stall_a; // Stall A stage
133 input stall_x; // Stall X stage
134 input stall_m; // Stall M stage
136 input [`LM32_WORD_RNG] address_x; // X stage load/store address
137 input [`LM32_WORD_RNG] address_m; // M stage load/store address
138 input load_q_m; // Load instruction in M stage
139 input store_q_m; // Store instruction in M stage
140 input [`LM32_WORD_RNG] store_data; // Data to store
141 input [`LM32_BYTE_SELECT_RNG] store_byte_select; // Which bytes in store data should be modified
143 input refill_ready; // Indicates next word of refill data is ready
144 input [`LM32_WORD_RNG] refill_data; // Refill data
146 input dflush; // Indicates cache should be flushed
148 /////////////////////////////////////////////////////
149 // Outputs
150 /////////////////////////////////////////////////////
152 output stall_request; // Request pipeline be stalled because cache is busy
153 wire stall_request;
154 output restart_request; // Request to restart instruction that caused the cache miss
155 reg restart_request;
156 output refill_request; // Request a refill
157 reg refill_request;
158 output [`LM32_WORD_RNG] refill_address; // Address to refill from
159 reg [`LM32_WORD_RNG] refill_address;
160 output refilling; // Indicates if the cache is currently refilling
161 reg refilling;
162 output [`LM32_WORD_RNG] load_data; // Data read from cache
163 wire [`LM32_WORD_RNG] load_data;
165 /////////////////////////////////////////////////////
166 // Internal nets and registers
167 /////////////////////////////////////////////////////
169 wire read_port_enable; // Cache memory read port clock enable
170 wire write_port_enable; // Cache memory write port clock enable
171 wire [0:associativity-1] way_tmem_we; // Tag memory write enable
172 wire [0:associativity-1] way_dmem_we; // Data memory write enable
173 wire [`LM32_WORD_RNG] way_data[0:associativity-1]; // Data read from data memory
174 wire [`LM32_DC_TAGS_TAG_RNG] way_tag[0:associativity-1];// Tag read from tag memory
175 wire [0:associativity-1] way_valid; // Indicates which ways are valid
176 wire [0:associativity-1] way_match; // Indicates which ways matched
177 wire miss; // Indicates no ways matched
179 wire [`LM32_DC_TMEM_ADDR_RNG] tmem_read_address; // Tag memory read address
180 wire [`LM32_DC_TMEM_ADDR_RNG] tmem_write_address; // Tag memory write address
181 wire [`LM32_DC_DMEM_ADDR_RNG] dmem_read_address; // Data memory read address
182 wire [`LM32_DC_DMEM_ADDR_RNG] dmem_write_address; // Data memory write address
183 wire [`LM32_DC_TAGS_RNG] tmem_write_data; // Tag memory write data
184 reg [`LM32_WORD_RNG] dmem_write_data; // Data memory write data
186 reg [`LM32_DC_STATE_RNG] state; // Current state of FSM
187 wire flushing; // Indicates if cache is currently flushing
188 wire check; // Indicates if cache is currently checking for hits/misses
189 wire refill; // Indicates if cache is currently refilling
191 wire valid_store; // Indicates if there is a valid store instruction
192 reg [associativity-1:0] refill_way_select; // Which way should be refilled
193 reg [`LM32_DC_ADDR_OFFSET_RNG] refill_offset; // Which word in cache line should be refilled
194 wire last_refill; // Indicates when on last cycle of cache refill
195 reg [`LM32_DC_TMEM_ADDR_RNG] flush_set; // Which set is currently being flushed
197 genvar i, j;
199 /////////////////////////////////////////////////////
200 // Functions
201 /////////////////////////////////////////////////////
203 `include "lm32_functions.v"
205 /////////////////////////////////////////////////////
206 // Instantiations
207 /////////////////////////////////////////////////////
209 generate
210 for (i = 0; i < associativity; i = i + 1)
211 begin : memories
212 // Way data
213 if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
214 begin : data_memories
215 lm32_ram
216 #(
217 // ----- Parameters -------
218 .data_width (32),
219 .address_width (`LM32_DC_DMEM_ADDR_WIDTH),
220 `ifdef CFG_DCACHE_DAT_USE_DP_TRUE
221 .RAM_IMPLEMENTATION ("EBR"),
222 .RAM_TYPE ("RAM_DP_TRUE")
223 `else
224 `ifdef CFG_DCACHE_DAT_USE_SLICE
225 .RAM_IMPLEMENTATION ("SLICE")
226 `else
227 .RAM_IMPLEMENTATION ("AUTO")
228 `endif
229 `endif
230 ) way_0_data_ram
231 (
232 // ----- Inputs -------
233 .read_clk (clk_i),
234 .write_clk (clk_i),
235 .reset (rst_i),
236 .read_address (dmem_read_address),
237 .enable_read (read_port_enable),
238 .write_address (dmem_write_address),
239 .enable_write (write_port_enable),
240 .write_enable (way_dmem_we[i]),
241 .write_data (dmem_write_data),
242 // ----- Outputs -------
243 .read_data (way_data[i])
244 );
245 end
246 else
247 begin
248 for (j = 0; j < 4; j = j + 1)
249 begin : byte_memories
250 lm32_ram
251 #(
252 // ----- Parameters -------
253 .data_width (8),
254 .address_width (`LM32_DC_DMEM_ADDR_WIDTH),
255 `ifdef CFG_DCACHE_DAT_USE_DP_TRUE
256 .RAM_IMPLEMENTATION ("EBR"),
257 .RAM_TYPE ("RAM_DP_TRUE")
258 `else
259 `ifdef CFG_DCACHE_DAT_USE_SLICE
260 .RAM_IMPLEMENTATION ("SLICE")
261 `else
262 .RAM_IMPLEMENTATION ("AUTO")
263 `endif
264 `endif
265 ) way_0_data_ram
266 (
267 // ----- Inputs -------
268 .read_clk (clk_i),
269 .write_clk (clk_i),
270 .reset (rst_i),
271 .read_address (dmem_read_address),
272 .enable_read (read_port_enable),
273 .write_address (dmem_write_address),
274 .enable_write (write_port_enable),
275 .write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)),
276 .write_data (dmem_write_data[(j+1)*8-1:j*8]),
277 // ----- Outputs -------
278 .read_data (way_data[i][(j+1)*8-1:j*8])
279 );
280 end
281 end
283 // Way tags
284 lm32_ram
285 #(
286 // ----- Parameters -------
287 .data_width (`LM32_DC_TAGS_WIDTH),
288 .address_width (`LM32_DC_TMEM_ADDR_WIDTH),
289 `ifdef CFG_DCACHE_DAT_USE_DP_TRUE
290 .RAM_IMPLEMENTATION ("EBR"),
291 .RAM_TYPE ("RAM_DP_TRUE")
292 `else
293 `ifdef CFG_DCACHE_DAT_USE_SLICE
294 .RAM_IMPLEMENTATION ("SLICE")
295 `else
296 .RAM_IMPLEMENTATION ("AUTO")
297 `endif
298 `endif
299 ) way_0_tag_ram
300 (
301 // ----- Inputs -------
302 .read_clk (clk_i),
303 .write_clk (clk_i),
304 .reset (rst_i),
305 .read_address (tmem_read_address),
306 .enable_read (read_port_enable),
307 .write_address (tmem_write_address),
308 .enable_write (`TRUE),
309 .write_enable (way_tmem_we[i]),
310 .write_data (tmem_write_data),
311 // ----- Outputs -------
312 .read_data ({way_tag[i], way_valid[i]})
313 );
314 end
316 endgenerate
318 /////////////////////////////////////////////////////
319 // Combinational logic
320 /////////////////////////////////////////////////////
322 // Compute which ways in the cache match the address being read
323 generate
324 for (i = 0; i < associativity; i = i + 1)
325 begin : match
326 assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE});
327 end
328 endgenerate
330 // Select data from way that matched the address being read
331 generate
332 if (associativity == 1)
333 begin : data_1
334 assign load_data = way_data[0];
335 end
336 else if (associativity == 2)
337 begin : data_2
338 assign load_data = way_match[0] ? way_data[0] : way_data[1];
339 end
340 endgenerate
342 generate
343 if (`LM32_DC_DMEM_ADDR_WIDTH < 11)
344 begin
345 // Select data to write to data memories
346 always @(*)
347 begin
348 if (refill == `TRUE)
349 dmem_write_data = refill_data;
350 else
351 begin
352 dmem_write_data[`LM32_BYTE_0_RNG] = store_byte_select[0] ? store_data[`LM32_BYTE_0_RNG] : load_data[`LM32_BYTE_0_RNG];
353 dmem_write_data[`LM32_BYTE_1_RNG] = store_byte_select[1] ? store_data[`LM32_BYTE_1_RNG] : load_data[`LM32_BYTE_1_RNG];
354 dmem_write_data[`LM32_BYTE_2_RNG] = store_byte_select[2] ? store_data[`LM32_BYTE_2_RNG] : load_data[`LM32_BYTE_2_RNG];
355 dmem_write_data[`LM32_BYTE_3_RNG] = store_byte_select[3] ? store_data[`LM32_BYTE_3_RNG] : load_data[`LM32_BYTE_3_RNG];
356 end
357 end
358 end
359 else
360 begin
361 // Select data to write to data memories - FIXME: Should use different write ports on dual port RAMs, but they don't work
362 always @(*)
363 begin
364 if (refill == `TRUE)
365 dmem_write_data = refill_data;
366 else
367 dmem_write_data = store_data;
368 end
369 end
370 endgenerate
372 // Compute address to use to index into the data memories
373 generate
374 if (bytes_per_line > 4)
375 assign dmem_write_address = (refill == `TRUE)
376 ? {refill_address[`LM32_DC_ADDR_SET_RNG], refill_offset}
377 : address_m[`LM32_DC_ADDR_IDX_RNG];
378 else
379 assign dmem_write_address = (refill == `TRUE)
380 ? refill_address[`LM32_DC_ADDR_SET_RNG]
381 : address_m[`LM32_DC_ADDR_IDX_RNG];
382 endgenerate
383 assign dmem_read_address = address_x[`LM32_DC_ADDR_IDX_RNG];
384 // Compute address to use to index into the tag memories
385 assign tmem_write_address = (flushing == `TRUE)
386 ? flush_set
387 : refill_address[`LM32_DC_ADDR_SET_RNG];
388 assign tmem_read_address = address_x[`LM32_DC_ADDR_SET_RNG];
390 // Compute signal to indicate when we are on the last refill accesses
391 generate
392 if (bytes_per_line > 4)
393 assign last_refill = refill_offset == {addr_offset_width{1'b1}};
394 else
395 assign last_refill = `TRUE;
396 endgenerate
398 // Compute data and tag memory access enable
399 assign read_port_enable = (stall_x == `FALSE);
400 assign write_port_enable = (refill_ready == `TRUE) || !stall_m;
402 // Determine when we have a valid store
403 assign valid_store = (store_q_m == `TRUE) && (check == `TRUE);
405 // Compute data and tag memory write enables
406 generate
407 if (associativity == 1)
408 begin : we_1
409 assign way_dmem_we[0] = (refill_ready == `TRUE) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
410 assign way_tmem_we[0] = (refill_ready == `TRUE) || (flushing == `TRUE);
411 end
412 else
413 begin : we_2
414 assign way_dmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || ((valid_store == `TRUE) && (way_match[0] == `TRUE));
415 assign way_dmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || ((valid_store == `TRUE) && (way_match[1] == `TRUE));
416 assign way_tmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || (flushing == `TRUE);
417 assign way_tmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || (flushing == `TRUE);
418 end
419 endgenerate
421 // On the last refill cycle set the valid bit, for all other writes it should be cleared
422 assign tmem_write_data[`LM32_DC_TAGS_VALID_RNG] = ((last_refill == `TRUE) || (valid_store == `TRUE)) && (flushing == `FALSE);
423 assign tmem_write_data[`LM32_DC_TAGS_TAG_RNG] = refill_address[`LM32_DC_ADDR_TAG_RNG];
425 // Signals that indicate which state we are in
426 assign flushing = state[0];
427 assign check = state[1];
428 assign refill = state[2];
430 assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE);
431 assign stall_request = (check == `FALSE);
433 /////////////////////////////////////////////////////
434 // Sequential logic
435 /////////////////////////////////////////////////////
437 // Record way selected for replacement on a cache miss
438 generate
439 if (associativity >= 2)
440 begin : way_select
441 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
442 begin
443 if (rst_i == `TRUE)
444 refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
445 else
446 begin
447 if (refill_request == `TRUE)
448 refill_way_select <= {refill_way_select[0], refill_way_select[1]};
449 end
450 end
451 end
452 endgenerate
454 // Record whether we are currently refilling
455 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
456 begin
457 if (rst_i == `TRUE)
458 refilling <= `FALSE;
459 else
460 refilling <= refill;
461 end
463 // Instruction cache control FSM
464 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
465 begin
466 if (rst_i == `TRUE)
467 begin
468 state <= `LM32_DC_STATE_FLUSH;
469 flush_set <= {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}};
470 refill_request <= `FALSE;
471 refill_address <= {`LM32_WORD_WIDTH{1'bx}};
472 restart_request <= `FALSE;
473 end
474 else
475 begin
476 case (state)
478 // Flush the cache
479 `LM32_DC_STATE_FLUSH:
480 begin
481 if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}})
482 state <= `LM32_DC_STATE_CHECK;
483 flush_set <= flush_set - 1'b1;
484 end
486 // Check for cache misses
487 `LM32_DC_STATE_CHECK:
488 begin
489 if (stall_a == `FALSE)
490 restart_request <= `FALSE;
491 if (miss == `TRUE)
492 begin
493 refill_request <= `TRUE;
494 refill_address <= address_m;
495 state <= `LM32_DC_STATE_REFILL;
496 end
497 else if (dflush == `TRUE)
498 state <= `LM32_DC_STATE_FLUSH;
499 end
501 // Refill a cache line
502 `LM32_DC_STATE_REFILL:
503 begin
504 refill_request <= `FALSE;
505 if (refill_ready == `TRUE)
506 begin
507 if (last_refill == `TRUE)
508 begin
509 restart_request <= `TRUE;
510 state <= `LM32_DC_STATE_CHECK;
511 end
512 end
513 end
515 endcase
516 end
517 end
519 generate
520 if (bytes_per_line > 4)
521 begin
522 // Refill offset
523 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
524 begin
525 if (rst_i == `TRUE)
526 refill_offset <= {addr_offset_width{1'b0}};
527 else
528 begin
529 case (state)
531 // Check for cache misses
532 `LM32_DC_STATE_CHECK:
533 begin
534 if (miss == `TRUE)
535 refill_offset <= {addr_offset_width{1'b0}};
536 end
538 // Refill a cache line
539 `LM32_DC_STATE_REFILL:
540 begin
541 if (refill_ready == `TRUE)
542 refill_offset <= refill_offset + 1'b1;
543 end
545 endcase
546 end
547 end
548 end
549 endgenerate
551 endmodule
553 `endif