Sat, 06 Aug 2011 01:33:43 +0100
Update documents for LM32 V3.8
1 // ==================================================================
2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
3 // ------------------------------------------------------------------
4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
5 // ALL RIGHTS RESERVED
6 // ------------------------------------------------------------------
7 //
8 // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
9 //
10 // Permission:
11 //
12 // Lattice Semiconductor grants permission to use this code
13 // pursuant to the terms of the Lattice Semiconductor Corporation
14 // Open Source License Agreement.
15 //
16 // Disclaimer:
17 //
18 // Lattice Semiconductor provides no warranty regarding the use or
19 // functionality of this code. It is the user's responsibility to
20 // verify the user’s design for consistency and functionality through
21 // the use of formal verification methods.
22 //
23 // --------------------------------------------------------------------
24 //
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36 // --------------------------------------------------------------------
37 // FILE DETAILS
38 // Project : LatticeMico32
39 // File : lm32_instruction_unit.v
40 // Title : Instruction unit
41 // Dependencies : lm32_include.v
42 // Version : 6.1.17
43 // : Initial Release
44 // Version : 7.0SP2, 3.0
45 // : No Change
46 // Version : 3.1
47 // : Support for static branch prediction is added. Fetching of
48 // : instructions can also be altered by branches predicted in D
49 // : stage of pipeline, and mispredicted branches in the X and M
50 // : stages of the pipeline.
51 // Version : 3.2
52 // : EBRs use SYNC resets instead of ASYNC resets.
53 // Version : 3.3
54 // : Support for a non-cacheable Instruction Memory that has a
55 // : single-cycle access latency. This memory can be accessed by
56 // : data port of LM32 (so that debugger has access to it).
57 // Version : 3.4
58 // : No change
59 // Version : 3.5
60 // : Bug fix: Inline memory is correctly generated if it is not a
61 // : power-of-two.
62 // : Bug fix: Fixed a bug that caused LM32 (configured without
63 // : instruction cache) to lock up in to an infinite loop due to a
64 // : instruction bus error when EBA was set to instruction inline
65 // : memory.
66 // Version : 3.8
67 // : Feature: Support for dynamically switching EBA to DEBA via a
68 // : GPIO.
69 // =============================================================================
71 `include "lm32_include.v"
73 /////////////////////////////////////////////////////
74 // Module interface
75 /////////////////////////////////////////////////////
77 module lm32_instruction_unit (
78 // ----- Inputs -------
79 clk_i,
80 rst_i,
81 `ifdef CFG_DEBUG_ENABLED
82 `ifdef CFG_ALTERNATE_EBA
83 at_debug,
84 `endif
85 `endif
86 // From pipeline
87 stall_a,
88 stall_f,
89 stall_d,
90 stall_x,
91 stall_m,
92 valid_f,
93 valid_d,
94 kill_f,
95 branch_predict_taken_d,
96 branch_predict_address_d,
97 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
98 branch_taken_x,
99 branch_target_x,
100 `endif
101 exception_m,
102 branch_taken_m,
103 branch_mispredict_taken_m,
104 branch_target_m,
105 `ifdef CFG_ICACHE_ENABLED
106 iflush,
107 `endif
108 `ifdef CFG_DCACHE_ENABLED
109 dcache_restart_request,
110 dcache_refill_request,
111 dcache_refilling,
112 `endif
113 `ifdef CFG_IROM_ENABLED
114 irom_store_data_m,
115 irom_address_xm,
116 irom_we_xm,
117 `endif
118 `ifdef CFG_IWB_ENABLED
119 // From Wishbone
120 i_dat_i,
121 i_ack_i,
122 i_err_i,
123 `endif
124 `ifdef CFG_HW_DEBUG_ENABLED
125 jtag_read_enable,
126 jtag_write_enable,
127 jtag_write_data,
128 jtag_address,
129 `endif
130 // ----- Outputs -------
131 // To pipeline
132 pc_f,
133 pc_d,
134 pc_x,
135 pc_m,
136 pc_w,
137 `ifdef CFG_ICACHE_ENABLED
138 icache_stall_request,
139 icache_restart_request,
140 icache_refill_request,
141 icache_refilling,
142 `endif
143 `ifdef CFG_IROM_ENABLED
144 irom_data_m,
145 `endif
146 `ifdef CFG_IWB_ENABLED
147 // To Wishbone
148 i_dat_o,
149 i_adr_o,
150 i_cyc_o,
151 i_sel_o,
152 i_stb_o,
153 i_we_o,
154 i_cti_o,
155 i_lock_o,
156 i_bte_o,
157 `endif
158 `ifdef CFG_HW_DEBUG_ENABLED
159 jtag_read_data,
160 jtag_access_complete,
161 `endif
162 `ifdef CFG_BUS_ERRORS_ENABLED
163 bus_error_d,
164 `endif
165 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
166 instruction_f,
167 `endif
168 instruction_d
169 );
171 /////////////////////////////////////////////////////
172 // Parameters
173 /////////////////////////////////////////////////////
175 parameter associativity = 1; // Associativity of the cache (Number of ways)
176 parameter sets = 512; // Number of sets
177 parameter bytes_per_line = 16; // Number of bytes per cache line
178 parameter base_address = 0; // Base address of cachable memory
179 parameter limit = 0; // Limit (highest address) of cachable memory
181 // For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used
182 localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
183 localparam addr_offset_lsb = 2;
184 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
186 /////////////////////////////////////////////////////
187 // Inputs
188 /////////////////////////////////////////////////////
190 input clk_i; // Clock
191 input rst_i; // Reset
193 `ifdef CFG_DEBUG_ENABLED
194 `ifdef CFG_ALTERNATE_EBA
195 input at_debug; // GPIO input that maps EBA to DEBA
196 `endif
197 `endif
199 input stall_a; // Stall A stage instruction
200 input stall_f; // Stall F stage instruction
201 input stall_d; // Stall D stage instruction
202 input stall_x; // Stall X stage instruction
203 input stall_m; // Stall M stage instruction
204 input valid_f; // Instruction in F stage is valid
205 input valid_d; // Instruction in D stage is valid
206 input kill_f; // Kill instruction in F stage
208 input branch_predict_taken_d; // Branch is predicted taken in D stage
209 input [`LM32_PC_RNG] branch_predict_address_d; // Branch target address
211 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
212 input branch_taken_x; // Branch instruction in X stage is taken
213 input [`LM32_PC_RNG] branch_target_x; // Target PC of X stage branch instruction
214 `endif
215 input exception_m;
216 input branch_taken_m; // Branch instruction in M stage is taken
217 input branch_mispredict_taken_m; // Branch instruction in M stage is mispredicted as taken
218 input [`LM32_PC_RNG] branch_target_m; // Target PC of M stage branch instruction
220 `ifdef CFG_ICACHE_ENABLED
221 input iflush; // Flush instruction cache
222 `endif
223 `ifdef CFG_DCACHE_ENABLED
224 input dcache_restart_request; // Restart instruction that caused a data cache miss
225 input dcache_refill_request; // Request to refill data cache
226 input dcache_refilling;
227 `endif
229 `ifdef CFG_IROM_ENABLED
230 input [`LM32_WORD_RNG] irom_store_data_m; // Data from load-store unit
231 input [`LM32_WORD_RNG] irom_address_xm; // Address from load-store unit
232 input irom_we_xm; // Indicates if memory operation is load or store
233 `endif
235 `ifdef CFG_IWB_ENABLED
236 input [`LM32_WORD_RNG] i_dat_i; // Instruction Wishbone interface read data
237 input i_ack_i; // Instruction Wishbone interface acknowledgement
238 input i_err_i; // Instruction Wishbone interface error
239 `endif
241 `ifdef CFG_HW_DEBUG_ENABLED
242 input jtag_read_enable; // JTAG read memory request
243 input jtag_write_enable; // JTAG write memory request
244 input [`LM32_BYTE_RNG] jtag_write_data; // JTAG wrirte data
245 input [`LM32_WORD_RNG] jtag_address; // JTAG read/write address
246 `endif
248 /////////////////////////////////////////////////////
249 // Outputs
250 /////////////////////////////////////////////////////
252 output [`LM32_PC_RNG] pc_f; // F stage PC
253 reg [`LM32_PC_RNG] pc_f;
254 output [`LM32_PC_RNG] pc_d; // D stage PC
255 reg [`LM32_PC_RNG] pc_d;
256 output [`LM32_PC_RNG] pc_x; // X stage PC
257 reg [`LM32_PC_RNG] pc_x;
258 output [`LM32_PC_RNG] pc_m; // M stage PC
259 reg [`LM32_PC_RNG] pc_m;
260 output [`LM32_PC_RNG] pc_w; // W stage PC
261 reg [`LM32_PC_RNG] pc_w;
263 `ifdef CFG_ICACHE_ENABLED
264 output icache_stall_request; // Instruction cache stall request
265 wire icache_stall_request;
266 output icache_restart_request; // Request to restart instruction that cached instruction cache miss
267 wire icache_restart_request;
268 output icache_refill_request; // Instruction cache refill request
269 wire icache_refill_request;
270 output icache_refilling; // Indicates the icache is refilling
271 wire icache_refilling;
272 `endif
274 `ifdef CFG_IROM_ENABLED
275 output [`LM32_WORD_RNG] irom_data_m; // Data to load-store unit on load
276 wire [`LM32_WORD_RNG] irom_data_m;
277 `endif
279 `ifdef CFG_IWB_ENABLED
280 output [`LM32_WORD_RNG] i_dat_o; // Instruction Wishbone interface write data
281 `ifdef CFG_HW_DEBUG_ENABLED
282 reg [`LM32_WORD_RNG] i_dat_o;
283 `else
284 wire [`LM32_WORD_RNG] i_dat_o;
285 `endif
286 output [`LM32_WORD_RNG] i_adr_o; // Instruction Wishbone interface address
287 reg [`LM32_WORD_RNG] i_adr_o;
288 output i_cyc_o; // Instruction Wishbone interface cycle
289 reg i_cyc_o;
290 output [`LM32_BYTE_SELECT_RNG] i_sel_o; // Instruction Wishbone interface byte select
291 `ifdef CFG_HW_DEBUG_ENABLED
292 reg [`LM32_BYTE_SELECT_RNG] i_sel_o;
293 `else
294 wire [`LM32_BYTE_SELECT_RNG] i_sel_o;
295 `endif
296 output i_stb_o; // Instruction Wishbone interface strobe
297 reg i_stb_o;
298 output i_we_o; // Instruction Wishbone interface write enable
299 `ifdef CFG_HW_DEBUG_ENABLED
300 reg i_we_o;
301 `else
302 wire i_we_o;
303 `endif
304 output [`LM32_CTYPE_RNG] i_cti_o; // Instruction Wishbone interface cycle type
305 reg [`LM32_CTYPE_RNG] i_cti_o;
306 output i_lock_o; // Instruction Wishbone interface lock bus
307 reg i_lock_o;
308 output [`LM32_BTYPE_RNG] i_bte_o; // Instruction Wishbone interface burst type
309 wire [`LM32_BTYPE_RNG] i_bte_o;
310 `endif
312 `ifdef CFG_HW_DEBUG_ENABLED
313 output [`LM32_BYTE_RNG] jtag_read_data; // Data read for JTAG interface
314 reg [`LM32_BYTE_RNG] jtag_read_data;
315 output jtag_access_complete; // Requested memory access by JTAG interface is complete
316 wire jtag_access_complete;
317 `endif
319 `ifdef CFG_BUS_ERRORS_ENABLED
320 output bus_error_d; // Indicates a bus error occured while fetching the instruction
321 reg bus_error_d;
322 `endif
323 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
324 output [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction (only to have register indices extracted from)
325 wire [`LM32_INSTRUCTION_RNG] instruction_f;
326 `endif
327 output [`LM32_INSTRUCTION_RNG] instruction_d; // D stage instruction to be decoded
328 reg [`LM32_INSTRUCTION_RNG] instruction_d;
330 /////////////////////////////////////////////////////
331 // Internal nets and registers
332 /////////////////////////////////////////////////////
334 reg [`LM32_PC_RNG] pc_a; // A stage PC
336 `ifdef LM32_CACHE_ENABLED
337 reg [`LM32_PC_RNG] restart_address; // Address to restart from after a cache miss
338 `endif
340 `ifdef CFG_ICACHE_ENABLED
341 wire icache_read_enable_f; // Indicates if instruction cache miss is valid
342 wire [`LM32_PC_RNG] icache_refill_address; // Address that caused cache miss
343 reg icache_refill_ready; // Indicates when next word of refill data is ready to be written to cache
344 reg [`LM32_INSTRUCTION_RNG] icache_refill_data; // Next word of refill data, fetched from Wishbone
345 wire [`LM32_INSTRUCTION_RNG] icache_data_f; // Instruction fetched from instruction cache
346 wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type
347 wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type
348 wire last_word; // Indicates if this is the last word in the cache line
349 wire [`LM32_PC_RNG] first_address; // First cache refill address
350 `else
351 `ifdef CFG_IWB_ENABLED
352 reg [`LM32_INSTRUCTION_RNG] wb_data_f; // Instruction fetched from Wishbone
353 `endif
354 `endif
355 `ifdef CFG_IROM_ENABLED
356 wire irom_select_a; // Indicates if A stage PC maps to a ROM address
357 reg irom_select_f; // Indicates if F stage PC maps to a ROM address
358 wire [`LM32_INSTRUCTION_RNG] irom_data_f; // Instruction fetched from ROM
359 `endif
360 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
361 `else
362 wire [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction
363 `endif
364 `ifdef CFG_BUS_ERRORS_ENABLED
365 reg bus_error_f; // Indicates if a bus error occured while fetching the instruction in the F stage
366 `endif
368 `ifdef CFG_HW_DEBUG_ENABLED
369 reg jtag_access; // Indicates if a JTAG WB access is in progress
370 `endif
372 `ifdef CFG_ALTERNATE_EBA
373 reg alternate_eba_taken;
374 `endif
376 /////////////////////////////////////////////////////
377 // Functions
378 /////////////////////////////////////////////////////
380 `include "lm32_functions.v"
382 /////////////////////////////////////////////////////
383 // Instantiations
384 /////////////////////////////////////////////////////
386 // Instruction ROM
387 `ifdef CFG_IROM_ENABLED
388 pmi_ram_dp_true
389 #(
390 // ----- Parameters -------
391 .pmi_family (`LATTICE_FAMILY),
393 //.pmi_addr_depth_a (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
394 //.pmi_addr_width_a ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
395 //.pmi_data_width_a (`LM32_WORD_WIDTH),
396 //.pmi_addr_depth_b (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
397 //.pmi_addr_width_b ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
398 //.pmi_data_width_b (`LM32_WORD_WIDTH),
400 .pmi_addr_depth_a (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
401 .pmi_addr_width_a (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
402 .pmi_data_width_a (`LM32_WORD_WIDTH),
403 .pmi_addr_depth_b (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
404 .pmi_addr_width_b (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
405 .pmi_data_width_b (`LM32_WORD_WIDTH),
407 .pmi_regmode_a ("noreg"),
408 .pmi_regmode_b ("noreg"),
409 .pmi_gsr ("enable"),
410 .pmi_resetmode ("sync"),
411 .pmi_init_file (`CFG_IROM_INIT_FILE),
412 .pmi_init_file_format (`CFG_IROM_INIT_FILE_FORMAT),
413 .module_type ("pmi_ram_dp_true")
414 )
415 ram (
416 // ----- Inputs -------
417 .ClockA (clk_i),
418 .ClockB (clk_i),
419 .ResetA (rst_i),
420 .ResetB (rst_i),
421 .DataInA ({32{1'b0}}),
422 .DataInB (irom_store_data_m),
423 .AddressA (pc_a[clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]),
424 .AddressB (irom_address_xm[clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]),
425 .ClockEnA (!stall_a),
426 .ClockEnB (!stall_x || !stall_m),
427 .WrA (`FALSE),
428 .WrB (irom_we_xm),
429 // ----- Outputs -------
430 .QA (irom_data_f),
431 .QB (irom_data_m)
432 );
433 `endif
435 `ifdef CFG_ICACHE_ENABLED
436 // Instruction cache
437 lm32_icache #(
438 .associativity (associativity),
439 .sets (sets),
440 .bytes_per_line (bytes_per_line),
441 .base_address (base_address),
442 .limit (limit)
443 ) icache (
444 // ----- Inputs -----
445 .clk_i (clk_i),
446 .rst_i (rst_i),
447 .stall_a (stall_a),
448 .stall_f (stall_f),
449 .branch_predict_taken_d (branch_predict_taken_d),
450 .valid_d (valid_d),
451 .address_a (pc_a),
452 .address_f (pc_f),
453 .read_enable_f (icache_read_enable_f),
454 .refill_ready (icache_refill_ready),
455 .refill_data (icache_refill_data),
456 .iflush (iflush),
457 // ----- Outputs -----
458 .stall_request (icache_stall_request),
459 .restart_request (icache_restart_request),
460 .refill_request (icache_refill_request),
461 .refill_address (icache_refill_address),
462 .refilling (icache_refilling),
463 .inst (icache_data_f)
464 );
465 `endif
467 /////////////////////////////////////////////////////
468 // Combinational Logic
469 /////////////////////////////////////////////////////
471 `ifdef CFG_ICACHE_ENABLED
472 // Generate signal that indicates when instruction cache misses are valid
473 assign icache_read_enable_f = (valid_f == `TRUE)
474 && (kill_f == `FALSE)
475 `ifdef CFG_DCACHE_ENABLED
476 && (dcache_restart_request == `FALSE)
477 `endif
478 `ifdef CFG_IROM_ENABLED
479 && (irom_select_f == `FALSE)
480 `endif
481 ;
482 `endif
484 // Compute address of next instruction to fetch
485 always @(*)
486 begin
487 // The request from the latest pipeline stage must take priority
488 `ifdef CFG_DCACHE_ENABLED
489 if (dcache_restart_request == `TRUE)
490 pc_a = restart_address;
491 else
492 `endif
493 if (branch_taken_m == `TRUE)
494 if ((branch_mispredict_taken_m == `TRUE) && (exception_m == `FALSE))
495 pc_a = pc_x;
496 else
497 pc_a = branch_target_m;
498 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
499 else if (branch_taken_x == `TRUE)
500 pc_a = branch_target_x;
501 `endif
502 else
503 if ( (valid_d == `TRUE) && (branch_predict_taken_d == `TRUE) )
504 pc_a = branch_predict_address_d;
505 else
506 `ifdef CFG_ICACHE_ENABLED
507 if (icache_restart_request == `TRUE)
508 pc_a = restart_address;
509 else
510 `endif
511 pc_a = pc_f + 1'b1;
512 end
514 // Select where instruction should be fetched from
515 `ifdef CFG_IROM_ENABLED
516 assign irom_select_a = ({pc_a, 2'b00} >= `CFG_IROM_BASE_ADDRESS) && ({pc_a, 2'b00} <= `CFG_IROM_LIMIT);
517 `endif
519 // Select instruction from selected source
520 `ifdef CFG_ICACHE_ENABLED
521 `ifdef CFG_IROM_ENABLED
522 assign instruction_f = irom_select_f == `TRUE ? irom_data_f : icache_data_f;
523 `else
524 assign instruction_f = icache_data_f;
525 `endif
526 `else
527 `ifdef CFG_IROM_ENABLED
528 `ifdef CFG_IWB_ENABLED
529 assign instruction_f = irom_select_f == `TRUE ? irom_data_f : wb_data_f;
530 `else
531 assign instruction_f = irom_data_f;
532 `endif
533 `else
534 assign instruction_f = wb_data_f;
535 `endif
536 `endif
538 // Unused/constant Wishbone signals
539 `ifdef CFG_IWB_ENABLED
540 `ifdef CFG_HW_DEBUG_ENABLED
541 `else
542 assign i_dat_o = 32'd0;
543 assign i_we_o = `FALSE;
544 assign i_sel_o = 4'b1111;
545 `endif
546 assign i_bte_o = `LM32_BTYPE_LINEAR;
547 `endif
549 `ifdef CFG_ICACHE_ENABLED
550 // Determine parameters for next cache refill Wishbone access
551 generate
552 case (bytes_per_line)
553 4:
554 begin
555 assign first_cycle_type = `LM32_CTYPE_END;
556 assign next_cycle_type = `LM32_CTYPE_END;
557 assign last_word = `TRUE;
558 assign first_address = icache_refill_address;
559 end
560 8:
561 begin
562 assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
563 assign next_cycle_type = `LM32_CTYPE_END;
564 assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
565 assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
566 end
567 16:
568 begin
569 assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
570 assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
571 assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
572 assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
573 end
574 endcase
575 endgenerate
576 `endif
578 /////////////////////////////////////////////////////
579 // Sequential Logic
580 /////////////////////////////////////////////////////
582 // PC
583 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
584 begin
585 if (rst_i == `TRUE)
586 begin
587 `ifdef CFG_DEBUG_ENABLED
588 `ifdef CFG_ALTERNATE_EBA
589 if (at_debug == `TRUE)
590 pc_f <= (`CFG_DEBA_RESET-4)/4;
591 else
592 pc_f <= (`CFG_EBA_RESET-4)/4;
593 `else
594 pc_f <= (`CFG_EBA_RESET-4)/4;
595 `endif
596 `else
597 pc_f <= (`CFG_EBA_RESET-4)/4;
598 `endif
599 pc_d <= {`LM32_PC_WIDTH{1'b0}};
600 pc_x <= {`LM32_PC_WIDTH{1'b0}};
601 pc_m <= {`LM32_PC_WIDTH{1'b0}};
602 pc_w <= {`LM32_PC_WIDTH{1'b0}};
603 end
604 else
605 begin
606 if (stall_f == `FALSE)
607 pc_f <= pc_a;
608 if (stall_d == `FALSE)
609 pc_d <= pc_f;
610 if (stall_x == `FALSE)
611 pc_x <= pc_d;
612 if (stall_m == `FALSE)
613 pc_m <= pc_x;
614 pc_w <= pc_m;
615 end
616 end
618 `ifdef LM32_CACHE_ENABLED
619 // Address to restart from after a cache miss has been handled
620 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
621 begin
622 if (rst_i == `TRUE)
623 restart_address <= {`LM32_PC_WIDTH{1'b0}};
624 else
625 begin
626 `ifdef CFG_DCACHE_ENABLED
627 `ifdef CFG_ICACHE_ENABLED
628 // D-cache restart address must take priority, otherwise instructions will be lost
629 if (dcache_refill_request == `TRUE)
630 restart_address <= pc_w;
631 else if ((icache_refill_request == `TRUE) && (!dcache_refilling) && (!dcache_restart_request))
632 restart_address <= icache_refill_address;
633 `else
634 if (dcache_refill_request == `TRUE)
635 restart_address <= pc_w;
636 `endif
637 `else
638 `ifdef CFG_ICACHE_ENABLED
639 if (icache_refill_request == `TRUE)
640 restart_address <= icache_refill_address;
641 `endif
642 `endif
643 end
644 end
645 `endif
647 // Record where instruction was fetched from
648 `ifdef CFG_IROM_ENABLED
649 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
650 begin
651 if (rst_i == `TRUE)
652 irom_select_f <= `FALSE;
653 else
654 begin
655 if (stall_f == `FALSE)
656 irom_select_f <= irom_select_a;
657 end
658 end
659 `endif
661 `ifdef CFG_HW_DEBUG_ENABLED
662 assign jtag_access_complete = (i_cyc_o == `TRUE) && ((i_ack_i == `TRUE) || (i_err_i == `TRUE)) && (jtag_access == `TRUE);
663 always @(*)
664 begin
665 case (jtag_address[1:0])
666 2'b00: jtag_read_data = i_dat_i[`LM32_BYTE_3_RNG];
667 2'b01: jtag_read_data = i_dat_i[`LM32_BYTE_2_RNG];
668 2'b10: jtag_read_data = i_dat_i[`LM32_BYTE_1_RNG];
669 2'b11: jtag_read_data = i_dat_i[`LM32_BYTE_0_RNG];
670 endcase
671 end
672 `endif
674 `ifdef CFG_IWB_ENABLED
675 // Instruction Wishbone interface
676 `ifdef CFG_ICACHE_ENABLED
677 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
678 begin
679 if (rst_i == `TRUE)
680 begin
681 i_cyc_o <= `FALSE;
682 i_stb_o <= `FALSE;
683 i_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
684 i_cti_o <= `LM32_CTYPE_END;
685 i_lock_o <= `FALSE;
686 icache_refill_data <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
687 icache_refill_ready <= `FALSE;
688 `ifdef CFG_BUS_ERRORS_ENABLED
689 bus_error_f <= `FALSE;
690 `endif
691 `ifdef CFG_HW_DEBUG_ENABLED
692 i_we_o <= `FALSE;
693 i_sel_o <= 4'b1111;
694 jtag_access <= `FALSE;
695 `endif
696 end
697 else
698 begin
699 icache_refill_ready <= `FALSE;
700 // Is a cycle in progress?
701 if (i_cyc_o == `TRUE)
702 begin
703 // Has cycle completed?
704 if ((i_ack_i == `TRUE) || (i_err_i == `TRUE))
705 begin
706 `ifdef CFG_HW_DEBUG_ENABLED
707 if (jtag_access == `TRUE)
708 begin
709 i_cyc_o <= `FALSE;
710 i_stb_o <= `FALSE;
711 i_we_o <= `FALSE;
712 jtag_access <= `FALSE;
713 end
714 else
715 `endif
716 begin
717 if (last_word == `TRUE)
718 begin
719 // Cache line fill complete
720 i_cyc_o <= `FALSE;
721 i_stb_o <= `FALSE;
722 i_lock_o <= `FALSE;
723 end
724 // Fetch next word in cache line
725 i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
726 i_cti_o <= next_cycle_type;
727 // Write fetched data into instruction cache
728 icache_refill_ready <= `TRUE;
729 icache_refill_data <= i_dat_i;
730 end
731 end
732 `ifdef CFG_BUS_ERRORS_ENABLED
733 if (i_err_i == `TRUE)
734 begin
735 bus_error_f <= `TRUE;
736 $display ("Instruction bus error. Address: %x", i_adr_o);
737 end
738 `endif
739 end
740 else
741 begin
742 if ((icache_refill_request == `TRUE) && (icache_refill_ready == `FALSE))
743 begin
744 // Read first word of cache line
745 `ifdef CFG_HW_DEBUG_ENABLED
746 i_sel_o <= 4'b1111;
747 `endif
748 i_adr_o <= {first_address, 2'b00};
749 i_cyc_o <= `TRUE;
750 i_stb_o <= `TRUE;
751 i_cti_o <= first_cycle_type;
752 //i_lock_o <= `TRUE;
753 `ifdef CFG_BUS_ERRORS_ENABLED
754 bus_error_f <= `FALSE;
755 `endif
756 end
757 `ifdef CFG_HW_DEBUG_ENABLED
758 else
759 begin
760 if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE))
761 begin
762 case (jtag_address[1:0])
763 2'b00: i_sel_o <= 4'b1000;
764 2'b01: i_sel_o <= 4'b0100;
765 2'b10: i_sel_o <= 4'b0010;
766 2'b11: i_sel_o <= 4'b0001;
767 endcase
768 i_adr_o <= jtag_address;
769 i_dat_o <= {4{jtag_write_data}};
770 i_cyc_o <= `TRUE;
771 i_stb_o <= `TRUE;
772 i_we_o <= jtag_write_enable;
773 i_cti_o <= `LM32_CTYPE_END;
774 jtag_access <= `TRUE;
775 end
776 end
777 `endif
778 `ifdef CFG_BUS_ERRORS_ENABLED
779 // Clear bus error when exception taken, otherwise they would be
780 // continually generated if exception handler is cached
781 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
782 if (branch_taken_x == `TRUE)
783 bus_error_f <= `FALSE;
784 `endif
785 if (branch_taken_m == `TRUE)
786 bus_error_f <= `FALSE;
787 `endif
788 end
789 end
790 end
791 `else
792 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
793 begin
794 if (rst_i == `TRUE)
795 begin
796 i_cyc_o <= `FALSE;
797 i_stb_o <= `FALSE;
798 i_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
799 i_cti_o <= `LM32_CTYPE_END;
800 i_lock_o <= `FALSE;
801 wb_data_f <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
802 `ifdef CFG_BUS_ERRORS_ENABLED
803 bus_error_f <= `FALSE;
804 `endif
805 end
806 else
807 begin
808 // Is a cycle in progress?
809 if (i_cyc_o == `TRUE)
810 begin
811 // Has cycle completed?
812 if((i_ack_i == `TRUE) || (i_err_i == `TRUE))
813 begin
814 // Cycle complete
815 i_cyc_o <= `FALSE;
816 i_stb_o <= `FALSE;
817 // Register fetched instruction
818 wb_data_f <= i_dat_i;
819 end
820 `ifdef CFG_BUS_ERRORS_ENABLED
821 if (i_err_i == `TRUE)
822 begin
823 bus_error_f <= `TRUE;
824 $display ("Instruction bus error. Address: %x", i_adr_o);
825 end
826 `endif
827 end
828 else
829 begin
830 // Wait for an instruction fetch from an external address
831 if ( (stall_a == `FALSE)
832 `ifdef CFG_IROM_ENABLED
833 && (irom_select_a == `FALSE)
834 `endif
835 )
836 begin
837 // Fetch instruction
838 `ifdef CFG_HW_DEBUG_ENABLED
839 i_sel_o <= 4'b1111;
840 `endif
841 i_adr_o <= {pc_a, 2'b00};
842 i_cyc_o <= `TRUE;
843 i_stb_o <= `TRUE;
844 `ifdef CFG_BUS_ERRORS_ENABLED
845 bus_error_f <= `FALSE;
846 `endif
847 end
848 else
849 begin
850 if ( (stall_a == `FALSE)
851 `ifdef CFG_IROM_ENABLED
852 && (irom_select_a == `TRUE)
853 `endif
854 )
855 begin
856 `ifdef CFG_BUS_ERRORS_ENABLED
857 bus_error_f <= `FALSE;
858 `endif
859 end
860 end
861 end
862 end
863 end
864 `endif
865 `endif
867 // Instruction register
868 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
869 begin
870 if (rst_i == `TRUE)
871 begin
872 instruction_d <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
873 `ifdef CFG_BUS_ERRORS_ENABLED
874 bus_error_d <= `FALSE;
875 `endif
876 end
877 else
878 begin
879 if (stall_d == `FALSE)
880 begin
881 instruction_d <= instruction_f;
882 `ifdef CFG_BUS_ERRORS_ENABLED
883 bus_error_d <= bus_error_f;
884 `endif
885 end
886 end
887 end
889 endmodule