Sat, 06 Aug 2011 01:33:43 +0100
Update documents for LM32 V3.8
1 // ==================================================================
2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
3 // ------------------------------------------------------------------
4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
5 // ALL RIGHTS RESERVED
6 // ------------------------------------------------------------------
7 //
8 // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
9 //
10 // Permission:
11 //
12 // Lattice Semiconductor grants permission to use this code
13 // pursuant to the terms of the Lattice Semiconductor Corporation
14 // Open Source License Agreement.
15 //
16 // Disclaimer:
17 //
18 // Lattice Semiconductor provides no warranty regarding the use or
19 // functionality of this code. It is the user's responsibility to
20 // verify the user’s design for consistency and functionality through
21 // the use of formal verification methods.
22 //
23 // --------------------------------------------------------------------
24 //
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36 // --------------------------------------------------------------------
37 // FILE DETAILS
38 // Project : LatticeMico32
39 // File : lm32_top.v
40 // Title : Top-level of CPU.
41 // Dependencies : lm32_include.v
42 // Version : 6.1.17
43 // : removed SPI - 04/12/07
44 // Version : 7.0SP2, 3.0
45 // : No Change
46 // Version : 3.1
47 // : No Change
48 // =============================================================================
50 `include "lm32_include.v"
52 /////////////////////////////////////////////////////
53 // Module interface
54 /////////////////////////////////////////////////////
56 module lm32_top (
57 // ----- Inputs -------
58 clk_i,
59 rst_i,
60 `ifdef CFG_DEBUG_ENABLED
61 `ifdef CFG_ALTERNATE_EBA
62 at_debug,
63 `endif
64 `endif
65 // From external devices
66 `ifdef CFG_INTERRUPTS_ENABLED
67 interrupt_n,
68 `endif
69 // From user logic
70 `ifdef CFG_USER_ENABLED
71 user_result,
72 user_complete,
73 `endif
74 `ifdef CFG_IWB_ENABLED
75 // Instruction Wishbone master
76 I_DAT_I,
77 I_ACK_I,
78 I_ERR_I,
79 I_RTY_I,
80 `endif
81 // Data Wishbone master
82 D_DAT_I,
83 D_ACK_I,
84 D_ERR_I,
85 D_RTY_I,
86 // Debug Slave port WishboneInterface
87 DEBUG_ADR_I,
88 DEBUG_DAT_I,
89 DEBUG_SEL_I,
90 DEBUG_WE_I,
91 DEBUG_CTI_I,
92 DEBUG_BTE_I,
93 DEBUG_LOCK_I,
94 DEBUG_CYC_I,
95 DEBUG_STB_I,
96 // ----- Outputs -------
97 `ifdef CFG_USER_ENABLED
98 user_valid,
99 user_opcode,
100 user_operand_0,
101 user_operand_1,
102 `endif
103 `ifdef CFG_IWB_ENABLED
104 // Instruction Wishbone master
105 I_DAT_O,
106 I_ADR_O,
107 I_CYC_O,
108 I_SEL_O,
109 I_STB_O,
110 I_WE_O,
111 I_CTI_O,
112 I_LOCK_O,
113 I_BTE_O,
114 `endif
115 // Data Wishbone master
116 D_DAT_O,
117 D_ADR_O,
118 D_CYC_O,
119 D_SEL_O,
120 D_STB_O,
121 D_WE_O,
122 D_CTI_O,
123 D_LOCK_O,
124 D_BTE_O,
125 // Debug Slave port WishboneInterface
126 DEBUG_ACK_O,
127 DEBUG_ERR_O,
128 DEBUG_RTY_O,
129 DEBUG_DAT_O
130 );
132 /////////////////////////////////////////////////////
133 // Inputs
134 /////////////////////////////////////////////////////
136 input clk_i; // Clock
137 input rst_i; // Reset
139 `ifdef CFG_DEBUG_ENABLED
140 `ifdef CFG_ALTERNATE_EBA
141 input at_debug; // GPIO input that maps EBA to DEBA
142 `endif
143 `endif
145 `ifdef CFG_INTERRUPTS_ENABLED
146 input [`LM32_INTERRUPT_RNG] interrupt_n; // Interrupt pins, active-low
147 `endif
149 `ifdef CFG_USER_ENABLED
150 input [`LM32_WORD_RNG] user_result; // User-defined instruction result
151 input user_complete; // Indicates the user-defined instruction result is valid
152 `endif
154 `ifdef CFG_IWB_ENABLED
155 input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data
156 input I_ACK_I; // Instruction Wishbone interface acknowledgement
157 input I_ERR_I; // Instruction Wishbone interface error
158 input I_RTY_I; // Instruction Wishbone interface retry
159 `endif
161 input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
162 input D_ACK_I; // Data Wishbone interface acknowledgement
163 input D_ERR_I; // Data Wishbone interface error
164 input D_RTY_I; // Data Wishbone interface retry
166 input [`LM32_WORD_RNG] DEBUG_ADR_I; // Debug monitor Wishbone interface address
167 input [`LM32_WORD_RNG] DEBUG_DAT_I; // Debug monitor Wishbone interface write data
168 input [`LM32_BYTE_SELECT_RNG] DEBUG_SEL_I; // Debug monitor Wishbone interface byte select
169 input DEBUG_WE_I; // Debug monitor Wishbone interface write enable
170 input [`LM32_CTYPE_RNG] DEBUG_CTI_I; // Debug monitor Wishbone interface cycle type
171 input [`LM32_BTYPE_RNG] DEBUG_BTE_I; // Debug monitor Wishbone interface burst type
172 input DEBUG_LOCK_I; // Debug monitor Wishbone interface locked transfer
173 input DEBUG_CYC_I; // Debug monitor Wishbone interface cycle
174 input DEBUG_STB_I; // Debug monitor Wishbone interface strobe
176 /////////////////////////////////////////////////////
177 // Outputs
178 /////////////////////////////////////////////////////
180 `ifdef CFG_USER_ENABLED
181 output user_valid; // Indicates that user_opcode and user_operand_* are valid
182 wire user_valid;
183 output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode
184 reg [`LM32_USER_OPCODE_RNG] user_opcode;
185 output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction
186 wire [`LM32_WORD_RNG] user_operand_0;
187 output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction
188 wire [`LM32_WORD_RNG] user_operand_1;
189 `endif
191 `ifdef CFG_IWB_ENABLED
192 output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data
193 wire [`LM32_WORD_RNG] I_DAT_O;
194 output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address
195 wire [`LM32_WORD_RNG] I_ADR_O;
196 output I_CYC_O; // Instruction Wishbone interface cycle
197 wire I_CYC_O;
198 output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select
199 wire [`LM32_BYTE_SELECT_RNG] I_SEL_O;
200 output I_STB_O; // Instruction Wishbone interface strobe
201 wire I_STB_O;
202 output I_WE_O; // Instruction Wishbone interface write enable
203 wire I_WE_O;
204 output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type
205 wire [`LM32_CTYPE_RNG] I_CTI_O;
206 output I_LOCK_O; // Instruction Wishbone interface lock bus
207 wire I_LOCK_O;
208 output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type
209 wire [`LM32_BTYPE_RNG] I_BTE_O;
210 `endif
212 output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
213 wire [`LM32_WORD_RNG] D_DAT_O;
214 output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
215 wire [`LM32_WORD_RNG] D_ADR_O;
216 output D_CYC_O; // Data Wishbone interface cycle
217 wire D_CYC_O;
218 output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select
219 wire [`LM32_BYTE_SELECT_RNG] D_SEL_O;
220 output D_STB_O; // Data Wishbone interface strobe
221 wire D_STB_O;
222 output D_WE_O; // Data Wishbone interface write enable
223 wire D_WE_O;
224 output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type
225 wire [`LM32_CTYPE_RNG] D_CTI_O;
226 output D_LOCK_O; // Date Wishbone interface lock bus
227 wire D_LOCK_O;
228 output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
229 wire [`LM32_BTYPE_RNG] D_BTE_O;
231 output DEBUG_ACK_O; // Debug monitor Wishbone ack
232 wire DEBUG_ACK_O;
233 output DEBUG_ERR_O; // Debug monitor Wishbone error
234 wire DEBUG_ERR_O;
235 output DEBUG_RTY_O; // Debug monitor Wishbone retry
236 wire DEBUG_RTY_O;
237 output [`LM32_WORD_RNG] DEBUG_DAT_O; // Debug monitor Wishbone read data
238 wire [`LM32_WORD_RNG] DEBUG_DAT_O;
240 /////////////////////////////////////////////////////
241 // Internal nets and registers
242 /////////////////////////////////////////////////////
244 `ifdef CFG_JTAG_ENABLED
245 // Signals between JTAG interface and CPU
246 wire [`LM32_BYTE_RNG] jtag_reg_d;
247 wire [`LM32_BYTE_RNG] jtag_reg_q;
248 wire jtag_update;
249 wire [2:0] jtag_reg_addr_d;
250 wire [2:0] jtag_reg_addr_q;
251 wire jtck;
252 wire jrstn;
253 `endif
255 `ifdef CFG_TRACE_ENABLED
256 // PC trace signals
257 wire [`LM32_PC_RNG] trace_pc; // PC to trace (address of next non-sequential instruction)
258 wire trace_pc_valid; // Indicates that a new trace PC is valid
259 wire trace_exception; // Indicates an exception has occured
260 wire [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured
261 wire trace_eret; // Indicates an eret instruction has been executed
262 `ifdef CFG_DEBUG_ENABLED
263 wire trace_bret; // Indicates a bret instruction has been executed
264 `endif
265 `endif
267 /////////////////////////////////////////////////////
268 // Functions
269 /////////////////////////////////////////////////////
271 `include "lm32_functions.v"
272 /////////////////////////////////////////////////////
273 // Instantiations
274 /////////////////////////////////////////////////////
276 // LM32 CPU
277 lm32_cpu cpu (
278 // ----- Inputs -------
279 .clk_i (clk_i),
280 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
281 .clk_n_i (clk_n),
282 `endif
283 .rst_i (rst_i),
284 `ifdef CFG_DEBUG_ENABLED
285 `ifdef CFG_ALTERNATE_EBA
286 .at_debug (at_debug),
287 `endif
288 `endif
289 // From external devices
290 `ifdef CFG_INTERRUPTS_ENABLED
291 .interrupt_n (interrupt_n),
292 `endif
293 // From user logic
294 `ifdef CFG_USER_ENABLED
295 .user_result (user_result),
296 .user_complete (user_complete),
297 `endif
298 `ifdef CFG_JTAG_ENABLED
299 // From JTAG
300 .jtag_clk (jtck),
301 .jtag_update (jtag_update),
302 .jtag_reg_q (jtag_reg_q),
303 .jtag_reg_addr_q (jtag_reg_addr_q),
304 `endif
305 `ifdef CFG_IWB_ENABLED
306 // Instruction Wishbone master
307 .I_DAT_I (I_DAT_I),
308 .I_ACK_I (I_ACK_I),
309 .I_ERR_I (I_ERR_I),
310 .I_RTY_I (I_RTY_I),
311 `endif
312 // Data Wishbone master
313 .D_DAT_I (D_DAT_I),
314 .D_ACK_I (D_ACK_I),
315 .D_ERR_I (D_ERR_I),
316 .D_RTY_I (D_RTY_I),
317 // ----- Outputs -------
318 `ifdef CFG_TRACE_ENABLED
319 .trace_pc (trace_pc),
320 .trace_pc_valid (trace_pc_valid),
321 .trace_exception (trace_exception),
322 .trace_eid (trace_eid),
323 .trace_eret (trace_eret),
324 `ifdef CFG_DEBUG_ENABLED
325 .trace_bret (trace_bret),
326 `endif
327 `endif
328 `ifdef CFG_JTAG_ENABLED
329 .jtag_reg_d (jtag_reg_d),
330 .jtag_reg_addr_d (jtag_reg_addr_d),
331 `endif
332 `ifdef CFG_USER_ENABLED
333 .user_valid (user_valid),
334 .user_opcode (user_opcode),
335 .user_operand_0 (user_operand_0),
336 .user_operand_1 (user_operand_1),
337 `endif
338 `ifdef CFG_IWB_ENABLED
339 // Instruction Wishbone master
340 .I_DAT_O (I_DAT_O),
341 .I_ADR_O (I_ADR_O),
342 .I_CYC_O (I_CYC_O),
343 .I_SEL_O (I_SEL_O),
344 .I_STB_O (I_STB_O),
345 .I_WE_O (I_WE_O),
346 .I_CTI_O (I_CTI_O),
347 .I_LOCK_O (I_LOCK_O),
348 .I_BTE_O (I_BTE_O),
349 `endif
350 // Data Wishbone master
351 .D_DAT_O (D_DAT_O),
352 .D_ADR_O (D_ADR_O),
353 .D_CYC_O (D_CYC_O),
354 .D_SEL_O (D_SEL_O),
355 .D_STB_O (D_STB_O),
356 .D_WE_O (D_WE_O),
357 .D_CTI_O (D_CTI_O),
358 .D_LOCK_O (D_LOCK_O),
359 .D_BTE_O (D_BTE_O)
360 );
362 wire TRACE_ACK_O;
363 wire [`LM32_WORD_RNG] TRACE_DAT_O;
364 `ifdef CFG_TRACE_ENABLED
365 lm32_trace trace_module (.clk_i (clk_i),
366 .rst_i (rst_i),
367 .stb_i (DEBUG_STB_I & DEBUG_ADR_I[13]),
368 .we_i (DEBUG_WE_I),
369 .sel_i (DEBUG_SEL_I),
370 .dat_i (DEBUG_DAT_I),
371 .adr_i (DEBUG_ADR_I),
372 .trace_pc (trace_pc),
373 .trace_eid (trace_eid),
374 .trace_eret (trace_eret),
375 .trace_bret (trace_bret),
376 .trace_pc_valid (trace_pc_valid),
377 .trace_exception (trace_exception),
378 .ack_o (TRACE_ACK_O),
379 .dat_o (TRACE_DAT_O));
380 `else
381 assign TRACE_ACK_O = 0;
382 assign TRACE_DAT_O = 0;
383 `endif
384 `ifdef DEBUG_ROM
385 wire ROM_ACK_O;
386 wire [`LM32_WORD_RNG] ROM_DAT_O;
388 assign DEBUG_ACK_O = DEBUG_ADR_I[13] ? TRACE_ACK_O : ROM_ACK_O;
389 assign DEBUG_DAT_O = DEBUG_ADR_I[13] ? TRACE_DAT_O : ROM_DAT_O;
391 // ROM monitor
392 lm32_monitor debug_rom (
393 // ----- Inputs -------
394 .clk_i (clk_i),
395 .rst_i (rst_i),
396 .MON_ADR_I (DEBUG_ADR_I[10:2]),
397 .MON_STB_I (DEBUG_STB_I & ~DEBUG_ADR_I[13]),
398 .MON_CYC_I (DEBUG_CYC_I & ~DEBUG_ADR_I[13]),
399 .MON_WE_I (DEBUG_WE_I),
400 .MON_SEL_I (DEBUG_SEL_I),
401 .MON_DAT_I (DEBUG_DAT_I),
402 // ----- Outputs ------
403 .MON_RTY_O (DEBUG_RTY_O),
404 .MON_ERR_O (DEBUG_ERR_O),
405 .MON_ACK_O (ROM_ACK_O),
406 .MON_DAT_O (ROM_DAT_O)
407 );
408 `endif
410 `ifdef CFG_JTAG_ENABLED
411 // JTAG cores
412 jtag_cores jtag_cores (
413 // ----- Inputs -----
414 `ifdef INCLUDE_LM32
415 .reg_d (jtag_reg_d),
416 .reg_addr_d (jtag_reg_addr_d),
417 `endif
418 // ----- Outputs -----
419 `ifdef INCLUDE_LM32
420 .reg_update (jtag_update),
421 .reg_q (jtag_reg_q),
422 .reg_addr_q (jtag_reg_addr_q),
423 `endif
424 .jtck (jtck),
425 .jrstn (jrstn)
426 );
427 `endif
429 endmodule