Mon, 05 Apr 2010 21:00:31 +0100
reduce size of caches to fit in DE1 FPGA
The default cache size makes the Icache and Dcache "just a bit" too big to
fit in the EP2C20 FPGA on the DE1 board. This commit reduces the Icache and
Dcache sizes to the defaults shown in the LatticeMico32 Processor Reference
Manual (pages 36 and 37).
1 // =============================================================================
2 // COPYRIGHT NOTICE
3 // Copyright 2006 (c) Lattice Semiconductor Corporation
4 // ALL RIGHTS RESERVED
5 // This confidential and proprietary software may be used only as authorised by
6 // a licensing agreement from Lattice Semiconductor Corporation.
7 // The entire notice above must be reproduced on all authorized copies and
8 // copies may only be made to the extent permitted by a licensing agreement from
9 // Lattice Semiconductor Corporation.
10 //
11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12 // 5555 NE Moore Court 408-826-6000 (other locations)
13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
14 // U.S.A email: techsupport@latticesemi.com
15 // =============================================================================/
16 // FILE DETAILS
17 // Project : LatticeMico32
18 // File : lm32_instruction_unit.v
19 // Title : Instruction unit
20 // Dependencies : lm32_include.v
21 // Version : 6.1.17
22 // : Initial Release
23 // Version : 7.0SP2, 3.0
24 // : No Change
25 // Version : 3.1
26 // : Support for static branch prediction is added. Fetching of
27 // : instructions can also be altered by branches predicted in D
28 // : stage of pipeline, and mispredicted branches in the X and M
29 // : stages of the pipeline.
30 // Version : 3.2
31 // : EBRs use SYNC resets instead of ASYNC resets.
32 // Version : 3.3
33 // : Support for a non-cacheable Instruction Memory that has a
34 // : single-cycle access latency. This memory can be accessed by
35 // : data port of LM32 (so that debugger has access to it).
36 // Version : 3.4
37 // : No change
38 // Version : 3.5
39 // : Bug fix: Inline memory is correctly generated if it is not a
40 // : power-of-two.
41 // : Bug fix: Fixed a bug that caused LM32 (configured without
42 // : instruction cache) to lock up in to an infinite loop due to a
43 // : instruction bus error when EBA was set to instruction inline
44 // : memory.
45 // =============================================================================
47 `include "lm32_include.v"
49 /////////////////////////////////////////////////////
50 // Module interface
51 /////////////////////////////////////////////////////
53 module lm32_instruction_unit (
54 // ----- Inputs -------
55 clk_i,
56 rst_i,
57 // From pipeline
58 stall_a,
59 stall_f,
60 stall_d,
61 stall_x,
62 stall_m,
63 valid_f,
64 valid_d,
65 kill_f,
66 branch_predict_taken_d,
67 branch_predict_address_d,
68 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
69 branch_taken_x,
70 branch_target_x,
71 `endif
72 exception_m,
73 branch_taken_m,
74 branch_mispredict_taken_m,
75 branch_target_m,
76 `ifdef CFG_ICACHE_ENABLED
77 iflush,
78 `endif
79 `ifdef CFG_DCACHE_ENABLED
80 dcache_restart_request,
81 dcache_refill_request,
82 dcache_refilling,
83 `endif
84 `ifdef CFG_IROM_ENABLED
85 irom_store_data_m,
86 irom_address_xm,
87 irom_we_xm,
88 `endif
89 `ifdef CFG_IWB_ENABLED
90 // From Wishbone
91 i_dat_i,
92 i_ack_i,
93 i_err_i,
94 i_rty_i,
95 `endif
96 `ifdef CFG_HW_DEBUG_ENABLED
97 jtag_read_enable,
98 jtag_write_enable,
99 jtag_write_data,
100 jtag_address,
101 `endif
102 // ----- Outputs -------
103 // To pipeline
104 pc_f,
105 pc_d,
106 pc_x,
107 pc_m,
108 pc_w,
109 `ifdef CFG_ICACHE_ENABLED
110 icache_stall_request,
111 icache_restart_request,
112 icache_refill_request,
113 icache_refilling,
114 `endif
115 `ifdef CFG_IROM_ENABLED
116 irom_data_m,
117 `endif
118 `ifdef CFG_IWB_ENABLED
119 // To Wishbone
120 i_dat_o,
121 i_adr_o,
122 i_cyc_o,
123 i_sel_o,
124 i_stb_o,
125 i_we_o,
126 i_cti_o,
127 i_lock_o,
128 i_bte_o,
129 `endif
130 `ifdef CFG_HW_DEBUG_ENABLED
131 jtag_read_data,
132 jtag_access_complete,
133 `endif
134 `ifdef CFG_BUS_ERRORS_ENABLED
135 bus_error_d,
136 `endif
137 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
138 instruction_f,
139 `endif
140 instruction_d
141 );
143 /////////////////////////////////////////////////////
144 // Parameters
145 /////////////////////////////////////////////////////
147 parameter associativity = 1; // Associativity of the cache (Number of ways)
148 parameter sets = 512; // Number of sets
149 parameter bytes_per_line = 16; // Number of bytes per cache line
150 parameter base_address = 0; // Base address of cachable memory
151 parameter limit = 0; // Limit (highest address) of cachable memory
153 // For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used
154 localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
155 localparam addr_offset_lsb = 2;
156 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
158 /////////////////////////////////////////////////////
159 // Inputs
160 /////////////////////////////////////////////////////
162 input clk_i; // Clock
163 input rst_i; // Reset
165 input stall_a; // Stall A stage instruction
166 input stall_f; // Stall F stage instruction
167 input stall_d; // Stall D stage instruction
168 input stall_x; // Stall X stage instruction
169 input stall_m; // Stall M stage instruction
170 input valid_f; // Instruction in F stage is valid
171 input valid_d; // Instruction in D stage is valid
172 input kill_f; // Kill instruction in F stage
174 input branch_predict_taken_d; // Branch is predicted taken in D stage
175 input [`LM32_PC_RNG] branch_predict_address_d; // Branch target address
177 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
178 input branch_taken_x; // Branch instruction in X stage is taken
179 input [`LM32_PC_RNG] branch_target_x; // Target PC of X stage branch instruction
180 `endif
181 input exception_m;
182 input branch_taken_m; // Branch instruction in M stage is taken
183 input branch_mispredict_taken_m; // Branch instruction in M stage is mispredicted as taken
184 input [`LM32_PC_RNG] branch_target_m; // Target PC of M stage branch instruction
186 `ifdef CFG_ICACHE_ENABLED
187 input iflush; // Flush instruction cache
188 `endif
189 `ifdef CFG_DCACHE_ENABLED
190 input dcache_restart_request; // Restart instruction that caused a data cache miss
191 input dcache_refill_request; // Request to refill data cache
192 input dcache_refilling;
193 `endif
195 `ifdef CFG_IROM_ENABLED
196 input [`LM32_WORD_RNG] irom_store_data_m; // Data from load-store unit
197 input [`LM32_WORD_RNG] irom_address_xm; // Address from load-store unit
198 input irom_we_xm; // Indicates if memory operation is load or store
199 `endif
201 `ifdef CFG_IWB_ENABLED
202 input [`LM32_WORD_RNG] i_dat_i; // Instruction Wishbone interface read data
203 input i_ack_i; // Instruction Wishbone interface acknowledgement
204 input i_err_i; // Instruction Wishbone interface error
205 input i_rty_i; // Instruction Wishbone interface retry
206 `endif
208 `ifdef CFG_HW_DEBUG_ENABLED
209 input jtag_read_enable; // JTAG read memory request
210 input jtag_write_enable; // JTAG write memory request
211 input [`LM32_BYTE_RNG] jtag_write_data; // JTAG wrirte data
212 input [`LM32_WORD_RNG] jtag_address; // JTAG read/write address
213 `endif
215 /////////////////////////////////////////////////////
216 // Outputs
217 /////////////////////////////////////////////////////
219 output [`LM32_PC_RNG] pc_f; // F stage PC
220 reg [`LM32_PC_RNG] pc_f;
221 output [`LM32_PC_RNG] pc_d; // D stage PC
222 reg [`LM32_PC_RNG] pc_d;
223 output [`LM32_PC_RNG] pc_x; // X stage PC
224 reg [`LM32_PC_RNG] pc_x;
225 output [`LM32_PC_RNG] pc_m; // M stage PC
226 reg [`LM32_PC_RNG] pc_m;
227 output [`LM32_PC_RNG] pc_w; // W stage PC
228 reg [`LM32_PC_RNG] pc_w;
230 `ifdef CFG_ICACHE_ENABLED
231 output icache_stall_request; // Instruction cache stall request
232 wire icache_stall_request;
233 output icache_restart_request; // Request to restart instruction that cached instruction cache miss
234 wire icache_restart_request;
235 output icache_refill_request; // Instruction cache refill request
236 wire icache_refill_request;
237 output icache_refilling; // Indicates the icache is refilling
238 wire icache_refilling;
239 `endif
241 `ifdef CFG_IROM_ENABLED
242 output [`LM32_WORD_RNG] irom_data_m; // Data to load-store unit on load
243 wire [`LM32_WORD_RNG] irom_data_m;
244 `endif
246 `ifdef CFG_IWB_ENABLED
247 output [`LM32_WORD_RNG] i_dat_o; // Instruction Wishbone interface write data
248 `ifdef CFG_HW_DEBUG_ENABLED
249 reg [`LM32_WORD_RNG] i_dat_o;
250 `else
251 wire [`LM32_WORD_RNG] i_dat_o;
252 `endif
253 output [`LM32_WORD_RNG] i_adr_o; // Instruction Wishbone interface address
254 reg [`LM32_WORD_RNG] i_adr_o;
255 output i_cyc_o; // Instruction Wishbone interface cycle
256 reg i_cyc_o;
257 output [`LM32_BYTE_SELECT_RNG] i_sel_o; // Instruction Wishbone interface byte select
258 `ifdef CFG_HW_DEBUG_ENABLED
259 reg [`LM32_BYTE_SELECT_RNG] i_sel_o;
260 `else
261 wire [`LM32_BYTE_SELECT_RNG] i_sel_o;
262 `endif
263 output i_stb_o; // Instruction Wishbone interface strobe
264 reg i_stb_o;
265 output i_we_o; // Instruction Wishbone interface write enable
266 `ifdef CFG_HW_DEBUG_ENABLED
267 reg i_we_o;
268 `else
269 wire i_we_o;
270 `endif
271 output [`LM32_CTYPE_RNG] i_cti_o; // Instruction Wishbone interface cycle type
272 reg [`LM32_CTYPE_RNG] i_cti_o;
273 output i_lock_o; // Instruction Wishbone interface lock bus
274 reg i_lock_o;
275 output [`LM32_BTYPE_RNG] i_bte_o; // Instruction Wishbone interface burst type
276 wire [`LM32_BTYPE_RNG] i_bte_o;
277 `endif
279 `ifdef CFG_HW_DEBUG_ENABLED
280 output [`LM32_BYTE_RNG] jtag_read_data; // Data read for JTAG interface
281 reg [`LM32_BYTE_RNG] jtag_read_data;
282 output jtag_access_complete; // Requested memory access by JTAG interface is complete
283 wire jtag_access_complete;
284 `endif
286 `ifdef CFG_BUS_ERRORS_ENABLED
287 output bus_error_d; // Indicates a bus error occured while fetching the instruction
288 reg bus_error_d;
289 `endif
290 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
291 output [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction (only to have register indices extracted from)
292 wire [`LM32_INSTRUCTION_RNG] instruction_f;
293 `endif
294 output [`LM32_INSTRUCTION_RNG] instruction_d; // D stage instruction to be decoded
295 reg [`LM32_INSTRUCTION_RNG] instruction_d;
297 /////////////////////////////////////////////////////
298 // Internal nets and registers
299 /////////////////////////////////////////////////////
301 reg [`LM32_PC_RNG] pc_a; // A stage PC
303 `ifdef LM32_CACHE_ENABLED
304 reg [`LM32_PC_RNG] restart_address; // Address to restart from after a cache miss
305 `endif
307 `ifdef CFG_ICACHE_ENABLED
308 wire icache_read_enable_f; // Indicates if instruction cache miss is valid
309 wire [`LM32_PC_RNG] icache_refill_address; // Address that caused cache miss
310 reg icache_refill_ready; // Indicates when next word of refill data is ready to be written to cache
311 reg [`LM32_INSTRUCTION_RNG] icache_refill_data; // Next word of refill data, fetched from Wishbone
312 wire [`LM32_INSTRUCTION_RNG] icache_data_f; // Instruction fetched from instruction cache
313 wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type
314 wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type
315 wire last_word; // Indicates if this is the last word in the cache line
316 wire [`LM32_PC_RNG] first_address; // First cache refill address
317 `else
318 `ifdef CFG_IWB_ENABLED
319 reg [`LM32_INSTRUCTION_RNG] wb_data_f; // Instruction fetched from Wishbone
320 `endif
321 `endif
322 `ifdef CFG_IROM_ENABLED
323 wire irom_select_a; // Indicates if A stage PC maps to a ROM address
324 reg irom_select_f; // Indicates if F stage PC maps to a ROM address
325 wire [`LM32_INSTRUCTION_RNG] irom_data_f; // Instruction fetched from ROM
326 `endif
327 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
328 `else
329 wire [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction
330 `endif
331 `ifdef CFG_BUS_ERRORS_ENABLED
332 reg bus_error_f; // Indicates if a bus error occured while fetching the instruction in the F stage
333 `endif
335 `ifdef CFG_HW_DEBUG_ENABLED
336 reg jtag_access; // Indicates if a JTAG WB access is in progress
337 `endif
339 /////////////////////////////////////////////////////
340 // Functions
341 /////////////////////////////////////////////////////
343 `include "lm32_functions.v"
345 /////////////////////////////////////////////////////
346 // Instantiations
347 /////////////////////////////////////////////////////
349 // Instruction ROM
350 `ifdef CFG_IROM_ENABLED
351 pmi_ram_dp_true
352 #(
353 // ----- Parameters -------
354 .pmi_family (`LATTICE_FAMILY),
356 //.pmi_addr_depth_a (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
357 //.pmi_addr_width_a ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
358 //.pmi_data_width_a (`LM32_WORD_WIDTH),
359 //.pmi_addr_depth_b (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
360 //.pmi_addr_width_b ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
361 //.pmi_data_width_b (`LM32_WORD_WIDTH),
363 .pmi_addr_depth_a (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
364 .pmi_addr_width_a (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
365 .pmi_data_width_a (`LM32_WORD_WIDTH),
366 .pmi_addr_depth_b (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
367 .pmi_addr_width_b (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
368 .pmi_data_width_b (`LM32_WORD_WIDTH),
370 .pmi_regmode_a ("noreg"),
371 .pmi_regmode_b ("noreg"),
372 .pmi_gsr ("enable"),
373 .pmi_resetmode ("sync"),
374 .pmi_init_file (`CFG_IROM_INIT_FILE),
375 .pmi_init_file_format (`CFG_IROM_INIT_FILE_FORMAT),
376 .module_type ("pmi_ram_dp_true")
377 )
378 ram (
379 // ----- Inputs -------
380 .ClockA (clk_i),
381 .ClockB (clk_i),
382 .ResetA (rst_i),
383 .ResetB (rst_i),
384 .DataInA ({32{1'b0}}),
385 .DataInB (irom_store_data_m),
386 .AddressA (pc_a[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]),
387 .AddressB (irom_address_xm[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]),
388 .ClockEnA (!stall_a),
389 .ClockEnB (!stall_x || !stall_m),
390 .WrA (`FALSE),
391 .WrB (irom_we_xm),
392 // ----- Outputs -------
393 .QA (irom_data_f),
394 .QB (irom_data_m)
395 );
396 `endif
398 `ifdef CFG_ICACHE_ENABLED
399 // Instruction cache
400 lm32_icache #(
401 .associativity (associativity),
402 .sets (sets),
403 .bytes_per_line (bytes_per_line),
404 .base_address (base_address),
405 .limit (limit)
406 ) icache (
407 // ----- Inputs -----
408 .clk_i (clk_i),
409 .rst_i (rst_i),
410 .stall_a (stall_a),
411 .stall_f (stall_f),
412 .branch_predict_taken_d (branch_predict_taken_d),
413 .valid_d (valid_d),
414 .address_a (pc_a),
415 .address_f (pc_f),
416 .read_enable_f (icache_read_enable_f),
417 .refill_ready (icache_refill_ready),
418 .refill_data (icache_refill_data),
419 .iflush (iflush),
420 // ----- Outputs -----
421 .stall_request (icache_stall_request),
422 .restart_request (icache_restart_request),
423 .refill_request (icache_refill_request),
424 .refill_address (icache_refill_address),
425 .refilling (icache_refilling),
426 .inst (icache_data_f)
427 );
428 `endif
430 /////////////////////////////////////////////////////
431 // Combinational Logic
432 /////////////////////////////////////////////////////
434 `ifdef CFG_ICACHE_ENABLED
435 // Generate signal that indicates when instruction cache misses are valid
436 assign icache_read_enable_f = (valid_f == `TRUE)
437 && (kill_f == `FALSE)
438 `ifdef CFG_DCACHE_ENABLED
439 && (dcache_restart_request == `FALSE)
440 `endif
441 `ifdef CFG_IROM_ENABLED
442 && (irom_select_f == `FALSE)
443 `endif
444 ;
445 `endif
447 // Compute address of next instruction to fetch
448 always @(*)
449 begin
450 // The request from the latest pipeline stage must take priority
451 `ifdef CFG_DCACHE_ENABLED
452 if (dcache_restart_request == `TRUE)
453 pc_a = restart_address;
454 else
455 `endif
456 if (branch_taken_m == `TRUE)
457 if ((branch_mispredict_taken_m == `TRUE) && (exception_m == `FALSE))
458 pc_a = pc_x;
459 else
460 pc_a = branch_target_m;
461 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
462 else if (branch_taken_x == `TRUE)
463 pc_a = branch_target_x;
464 `endif
465 else
466 if ( (valid_d == `TRUE) && (branch_predict_taken_d == `TRUE) )
467 pc_a = branch_predict_address_d;
468 else
469 `ifdef CFG_ICACHE_ENABLED
470 if (icache_restart_request == `TRUE)
471 pc_a = restart_address;
472 else
473 `endif
474 pc_a = pc_f + 1'b1;
475 end
477 // Select where instruction should be fetched from
478 `ifdef CFG_IROM_ENABLED
479 assign irom_select_a = ({pc_a, 2'b00} >= `CFG_IROM_BASE_ADDRESS) && ({pc_a, 2'b00} <= `CFG_IROM_LIMIT);
480 `endif
482 // Select instruction from selected source
483 `ifdef CFG_ICACHE_ENABLED
484 `ifdef CFG_IROM_ENABLED
485 assign instruction_f = irom_select_f == `TRUE ? irom_data_f : icache_data_f;
486 `else
487 assign instruction_f = icache_data_f;
488 `endif
489 `else
490 `ifdef CFG_IROM_ENABLED
491 `ifdef CFG_IWB_ENABLED
492 assign instruction_f = irom_select_f == `TRUE ? irom_data_f : wb_data_f;
493 `else
494 assign instruction_f = irom_data_f;
495 `endif
496 `else
497 assign instruction_f = wb_data_f;
498 `endif
499 `endif
501 // Unused/constant Wishbone signals
502 `ifdef CFG_IWB_ENABLED
503 `ifdef CFG_HW_DEBUG_ENABLED
504 `else
505 assign i_dat_o = 32'd0;
506 assign i_we_o = `FALSE;
507 assign i_sel_o = 4'b1111;
508 `endif
509 assign i_bte_o = `LM32_BTYPE_LINEAR;
510 `endif
512 `ifdef CFG_ICACHE_ENABLED
513 // Determine parameters for next cache refill Wishbone access
514 generate
515 case (bytes_per_line)
516 4:
517 begin
518 assign first_cycle_type = `LM32_CTYPE_END;
519 assign next_cycle_type = `LM32_CTYPE_END;
520 assign last_word = `TRUE;
521 assign first_address = icache_refill_address;
522 end
523 8:
524 begin
525 assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
526 assign next_cycle_type = `LM32_CTYPE_END;
527 assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
528 assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
529 end
530 16:
531 begin
532 assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
533 assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
534 assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
535 assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
536 end
537 endcase
538 endgenerate
539 `endif
541 /////////////////////////////////////////////////////
542 // Sequential Logic
543 /////////////////////////////////////////////////////
545 // PC
546 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
547 begin
548 if (rst_i == `TRUE)
549 begin
550 pc_f <= (`CFG_EBA_RESET-4)/4;
551 pc_d <= {`LM32_PC_WIDTH{1'b0}};
552 pc_x <= {`LM32_PC_WIDTH{1'b0}};
553 pc_m <= {`LM32_PC_WIDTH{1'b0}};
554 pc_w <= {`LM32_PC_WIDTH{1'b0}};
555 end
556 else
557 begin
558 if (stall_f == `FALSE)
559 pc_f <= pc_a;
560 if (stall_d == `FALSE)
561 pc_d <= pc_f;
562 if (stall_x == `FALSE)
563 pc_x <= pc_d;
564 if (stall_m == `FALSE)
565 pc_m <= pc_x;
566 pc_w <= pc_m;
567 end
568 end
570 `ifdef LM32_CACHE_ENABLED
571 // Address to restart from after a cache miss has been handled
572 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
573 begin
574 if (rst_i == `TRUE)
575 restart_address <= {`LM32_PC_WIDTH{1'b0}};
576 else
577 begin
578 `ifdef CFG_DCACHE_ENABLED
579 `ifdef CFG_ICACHE_ENABLED
580 // D-cache restart address must take priority, otherwise instructions will be lost
581 if (dcache_refill_request == `TRUE)
582 restart_address <= pc_w;
583 else if ((icache_refill_request == `TRUE) && (!dcache_refilling) && (!dcache_restart_request))
584 restart_address <= icache_refill_address;
585 `else
586 if (dcache_refill_request == `TRUE)
587 restart_address <= pc_w;
588 `endif
589 `else
590 `ifdef CFG_ICACHE_ENABLED
591 if (icache_refill_request == `TRUE)
592 restart_address <= icache_refill_address;
593 `endif
594 `endif
595 end
596 end
597 `endif
599 // Record where instruction was fetched from
600 `ifdef CFG_IROM_ENABLED
601 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
602 begin
603 if (rst_i == `TRUE)
604 irom_select_f <= `FALSE;
605 else
606 begin
607 if (stall_f == `FALSE)
608 irom_select_f <= irom_select_a;
609 end
610 end
611 `endif
613 `ifdef CFG_HW_DEBUG_ENABLED
614 assign jtag_access_complete = (i_cyc_o == `TRUE) && ((i_ack_i == `TRUE) || (i_err_i == `TRUE)) && (jtag_access == `TRUE);
615 always @(*)
616 begin
617 case (jtag_address[1:0])
618 2'b00: jtag_read_data = i_dat_i[`LM32_BYTE_3_RNG];
619 2'b01: jtag_read_data = i_dat_i[`LM32_BYTE_2_RNG];
620 2'b10: jtag_read_data = i_dat_i[`LM32_BYTE_1_RNG];
621 2'b11: jtag_read_data = i_dat_i[`LM32_BYTE_0_RNG];
622 endcase
623 end
624 `endif
626 `ifdef CFG_IWB_ENABLED
627 // Instruction Wishbone interface
628 `ifdef CFG_ICACHE_ENABLED
629 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
630 begin
631 if (rst_i == `TRUE)
632 begin
633 i_cyc_o <= `FALSE;
634 i_stb_o <= `FALSE;
635 i_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
636 i_cti_o <= `LM32_CTYPE_END;
637 i_lock_o <= `FALSE;
638 icache_refill_data <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
639 icache_refill_ready <= `FALSE;
640 `ifdef CFG_BUS_ERRORS_ENABLED
641 bus_error_f <= `FALSE;
642 `endif
643 `ifdef CFG_HW_DEBUG_ENABLED
644 i_we_o <= `FALSE;
645 i_sel_o <= 4'b1111;
646 jtag_access <= `FALSE;
647 `endif
648 end
649 else
650 begin
651 icache_refill_ready <= `FALSE;
652 // Is a cycle in progress?
653 if (i_cyc_o == `TRUE)
654 begin
655 // Has cycle completed?
656 if ((i_ack_i == `TRUE) || (i_err_i == `TRUE))
657 begin
658 `ifdef CFG_HW_DEBUG_ENABLED
659 if (jtag_access == `TRUE)
660 begin
661 i_cyc_o <= `FALSE;
662 i_stb_o <= `FALSE;
663 i_we_o <= `FALSE;
664 jtag_access <= `FALSE;
665 end
666 else
667 `endif
668 begin
669 if (last_word == `TRUE)
670 begin
671 // Cache line fill complete
672 i_cyc_o <= `FALSE;
673 i_stb_o <= `FALSE;
674 i_lock_o <= `FALSE;
675 end
676 // Fetch next word in cache line
677 i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
678 i_cti_o <= next_cycle_type;
679 // Write fetched data into instruction cache
680 icache_refill_ready <= `TRUE;
681 icache_refill_data <= i_dat_i;
682 end
683 end
684 `ifdef CFG_BUS_ERRORS_ENABLED
685 if (i_err_i == `TRUE)
686 begin
687 bus_error_f <= `TRUE;
688 $display ("Instruction bus error. Address: %x", i_adr_o);
689 end
690 `endif
691 end
692 else
693 begin
694 if ((icache_refill_request == `TRUE) && (icache_refill_ready == `FALSE))
695 begin
696 // Read first word of cache line
697 `ifdef CFG_HW_DEBUG_ENABLED
698 i_sel_o <= 4'b1111;
699 `endif
700 i_adr_o <= {first_address, 2'b00};
701 i_cyc_o <= `TRUE;
702 i_stb_o <= `TRUE;
703 i_cti_o <= first_cycle_type;
704 //i_lock_o <= `TRUE;
705 `ifdef CFG_BUS_ERRORS_ENABLED
706 bus_error_f <= `FALSE;
707 `endif
708 end
709 `ifdef CFG_HW_DEBUG_ENABLED
710 else
711 begin
712 if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE))
713 begin
714 case (jtag_address[1:0])
715 2'b00: i_sel_o <= 4'b1000;
716 2'b01: i_sel_o <= 4'b0100;
717 2'b10: i_sel_o <= 4'b0010;
718 2'b11: i_sel_o <= 4'b0001;
719 endcase
720 i_adr_o <= jtag_address;
721 i_dat_o <= {4{jtag_write_data}};
722 i_cyc_o <= `TRUE;
723 i_stb_o <= `TRUE;
724 i_we_o <= jtag_write_enable;
725 i_cti_o <= `LM32_CTYPE_END;
726 jtag_access <= `TRUE;
727 end
728 end
729 `endif
730 `ifdef CFG_BUS_ERRORS_ENABLED
731 // Clear bus error when exception taken, otherwise they would be
732 // continually generated if exception handler is cached
733 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
734 if (branch_taken_x == `TRUE)
735 bus_error_f <= `FALSE;
736 `endif
737 if (branch_taken_m == `TRUE)
738 bus_error_f <= `FALSE;
739 `endif
740 end
741 end
742 end
743 `else
744 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
745 begin
746 if (rst_i == `TRUE)
747 begin
748 i_cyc_o <= `FALSE;
749 i_stb_o <= `FALSE;
750 i_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
751 i_cti_o <= `LM32_CTYPE_END;
752 i_lock_o <= `FALSE;
753 wb_data_f <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
754 `ifdef CFG_BUS_ERRORS_ENABLED
755 bus_error_f <= `FALSE;
756 `endif
757 end
758 else
759 begin
760 // Is a cycle in progress?
761 if (i_cyc_o == `TRUE)
762 begin
763 // Has cycle completed?
764 if((i_ack_i == `TRUE) || (i_err_i == `TRUE))
765 begin
766 // Cycle complete
767 i_cyc_o <= `FALSE;
768 i_stb_o <= `FALSE;
769 // Register fetched instruction
770 wb_data_f <= i_dat_i;
771 end
772 `ifdef CFG_BUS_ERRORS_ENABLED
773 if (i_err_i == `TRUE)
774 begin
775 bus_error_f <= `TRUE;
776 $display ("Instruction bus error. Address: %x", i_adr_o);
777 end
778 `endif
779 end
780 else
781 begin
782 // Wait for an instruction fetch from an external address
783 if ( (stall_a == `FALSE)
784 `ifdef CFG_IROM_ENABLED
785 && (irom_select_a == `FALSE)
786 `endif
787 )
788 begin
789 // Fetch instruction
790 `ifdef CFG_HW_DEBUG_ENABLED
791 i_sel_o <= 4'b1111;
792 `endif
793 i_adr_o <= {pc_a, 2'b00};
794 i_cyc_o <= `TRUE;
795 i_stb_o <= `TRUE;
796 `ifdef CFG_BUS_ERRORS_ENABLED
797 bus_error_f <= `FALSE;
798 `endif
799 end
800 else
801 begin
802 if ( (stall_a == `FALSE)
803 `ifdef CFG_IROM_ENABLED
804 && (irom_select_a == `TRUE)
805 `endif
806 )
807 begin
808 `ifdef CFG_BUS_ERRORS_ENABLED
809 bus_error_f <= `FALSE;
810 `endif
811 end
812 end
813 end
814 end
815 end
816 `endif
817 `endif
819 // Instruction register
820 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
821 begin
822 if (rst_i == `TRUE)
823 begin
824 instruction_d <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
825 `ifdef CFG_BUS_ERRORS_ENABLED
826 bus_error_d <= `FALSE;
827 `endif
828 end
829 else
830 begin
831 if (stall_d == `FALSE)
832 begin
833 instruction_d <= instruction_f;
834 `ifdef CFG_BUS_ERRORS_ENABLED
835 bus_error_d <= bus_error_f;
836 `endif
837 end
838 end
839 end
841 endmodule