Mon, 05 Apr 2010 21:00:31 +0100
reduce size of caches to fit in DE1 FPGA
The default cache size makes the Icache and Dcache "just a bit" too big to
fit in the EP2C20 FPGA on the DE1 board. This commit reduces the Icache and
Dcache sizes to the defaults shown in the LatticeMico32 Processor Reference
Manual (pages 36 and 37).
1 // =============================================================================
2 // COPYRIGHT NOTICE
3 // Copyright 2006 (c) Lattice Semiconductor Corporation
4 // ALL RIGHTS RESERVED
5 // This confidential and proprietary software may be used only as authorised by
6 // a licensing agreement from Lattice Semiconductor Corporation.
7 // The entire notice above must be reproduced on all authorized copies and
8 // copies may only be made to the extent permitted by a licensing agreement from
9 // Lattice Semiconductor Corporation.
10 //
11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12 // 5555 NE Moore Court 408-826-6000 (other locations)
13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
14 // U.S.A email: techsupport@latticesemi.com
15 // =============================================================================/
16 // FILE DETAILS
17 // Project : LatticeMico32
18 // File : lm32_logic_op.v
19 // Title : Logic operations (and / or / not etc)
20 // Dependencies : lm32_include.v
21 // Version : 6.1.17
22 // : Initial Release
23 // Version : 7.0SP2, 3.0
24 // : No Change
25 // Version : 3.1
26 // : No Change
27 // =============================================================================
29 `include "lm32_include.v"
31 /////////////////////////////////////////////////////
32 // Module interface
33 /////////////////////////////////////////////////////
35 module lm32_logic_op (
36 // ----- Inputs -------
37 logic_op_x,
38 operand_0_x,
39 operand_1_x,
40 // ----- Outputs -------
41 logic_result_x
42 );
44 /////////////////////////////////////////////////////
45 // Inputs
46 /////////////////////////////////////////////////////
48 input [`LM32_LOGIC_OP_RNG] logic_op_x;
49 input [`LM32_WORD_RNG] operand_0_x;
50 input [`LM32_WORD_RNG] operand_1_x;
52 /////////////////////////////////////////////////////
53 // Outputs
54 /////////////////////////////////////////////////////
56 output [`LM32_WORD_RNG] logic_result_x;
57 reg [`LM32_WORD_RNG] logic_result_x;
59 /////////////////////////////////////////////////////
60 // Internal nets and registers
61 /////////////////////////////////////////////////////
63 integer logic_idx;
65 /////////////////////////////////////////////////////
66 // Combinational Logic
67 /////////////////////////////////////////////////////
69 always @(*)
70 begin
71 for(logic_idx = 0; logic_idx < `LM32_WORD_WIDTH; logic_idx = logic_idx + 1)
72 logic_result_x[logic_idx] = logic_op_x[{operand_1_x[logic_idx], operand_0_x[logic_idx]}];
73 end
75 endmodule