Mon, 05 Apr 2010 21:00:31 +0100
reduce size of caches to fit in DE1 FPGA
The default cache size makes the Icache and Dcache "just a bit" too big to
fit in the EP2C20 FPGA on the DE1 board. This commit reduces the Icache and
Dcache sizes to the defaults shown in the LatticeMico32 Processor Reference
Manual (pages 36 and 37).
1 // =============================================================================
2 // COPYRIGHT NOTICE
3 // Copyright 2006 (c) Lattice Semiconductor Corporation
4 // ALL RIGHTS RESERVED
5 // This confidential and proprietary software may be used only as authorised by
6 // a licensing agreement from Lattice Semiconductor Corporation.
7 // The entire notice above must be reproduced on all authorized copies and
8 // copies may only be made to the extent permitted by a licensing agreement from
9 // Lattice Semiconductor Corporation.
10 //
11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12 // 5555 NE Moore Court 408-826-6000 (other locations)
13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
14 // U.S.A email: techsupport@latticesemi.com
15 // =============================================================================/
16 // FILE DETAILS
17 // Project : LatticeMico32
18 // File : lm32_multiplier.v
19 // Title : Pipelined multiplier.
20 // Dependencies : lm32_include.v
21 // Version : 6.1.17
22 // : Initial Release
23 // Version : 7.0SP2, 3.0
24 // : No Change
25 // Version : 3.1
26 // : No Change
27 // =============================================================================
29 `include "lm32_include.v"
31 /////////////////////////////////////////////////////
32 // Module interface
33 /////////////////////////////////////////////////////
35 module lm32_multiplier (
36 // ----- Inputs -----
37 clk_i,
38 rst_i,
39 stall_x,
40 stall_m,
41 operand_0,
42 operand_1,
43 // ----- Ouputs -----
44 result
45 );
47 /////////////////////////////////////////////////////
48 // Inputs
49 /////////////////////////////////////////////////////
51 input clk_i; // Clock
52 input rst_i; // Reset
53 input stall_x; // Stall instruction in X stage
54 input stall_m; // Stall instruction in M stage
55 input [`LM32_WORD_RNG] operand_0; // Muliplicand
56 input [`LM32_WORD_RNG] operand_1; // Multiplier
58 /////////////////////////////////////////////////////
59 // Outputs
60 /////////////////////////////////////////////////////
62 output [`LM32_WORD_RNG] result; // Product of multiplication
63 reg [`LM32_WORD_RNG] result;
65 /////////////////////////////////////////////////////
66 // Internal nets and registers
67 /////////////////////////////////////////////////////
69 reg [`LM32_WORD_RNG] muliplicand;
70 reg [`LM32_WORD_RNG] multiplier;
71 reg [`LM32_WORD_RNG] product;
73 /////////////////////////////////////////////////////
74 // Sequential logic
75 /////////////////////////////////////////////////////
77 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
78 begin
79 if (rst_i == `TRUE)
80 begin
81 muliplicand <= {`LM32_WORD_WIDTH{1'b0}};
82 multiplier <= {`LM32_WORD_WIDTH{1'b0}};
83 product <= {`LM32_WORD_WIDTH{1'b0}};
84 result <= {`LM32_WORD_WIDTH{1'b0}};
85 end
86 else
87 begin
88 if (stall_x == `FALSE)
89 begin
90 muliplicand <= operand_0;
91 multiplier <= operand_1;
92 end
93 if (stall_m == `FALSE)
94 product <= muliplicand * multiplier;
95 result <= product;
96 end
97 end
99 endmodule