Mon, 05 Apr 2010 21:00:31 +0100
reduce size of caches to fit in DE1 FPGA
The default cache size makes the Icache and Dcache "just a bit" too big to
fit in the EP2C20 FPGA on the DE1 board. This commit reduces the Icache and
Dcache sizes to the defaults shown in the LatticeMico32 Processor Reference
Manual (pages 36 and 37).
1 // =============================================================================
2 // COPYRIGHT NOTICE
3 // Copyright 2006 (c) Lattice Semiconductor Corporation
4 // ALL RIGHTS RESERVED
5 // This confidential and proprietary software may be used only as authorised by
6 // a licensing agreement from Lattice Semiconductor Corporation.
7 // The entire notice above must be reproduced on all authorized copies and
8 // copies may only be made to the extent permitted by a licensing agreement from
9 // Lattice Semiconductor Corporation.
10 //
11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12 // 5555 NE Moore Court 408-826-6000 (other locations)
13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
14 // U.S.A email: techsupport@latticesemi.com
15 // =============================================================================/
16 // FILE DETAILS
17 // Project : LatticeMico32
18 // File : lm32_top.v
19 // Title : Top-level of CPU.
20 // Dependencies : lm32_include.v
21 // Version : 6.1.17
22 // : removed SPI - 04/12/07
23 // Version : 7.0SP2, 3.0
24 // : No Change
25 // Version : 3.1
26 // : No Change
27 // =============================================================================
29 `include "lm32_include.v"
31 /////////////////////////////////////////////////////
32 // Module interface
33 /////////////////////////////////////////////////////
35 module lm32_top (
36 // ----- Inputs -------
37 clk_i,
38 rst_i,
39 // From external devices
40 `ifdef CFG_INTERRUPTS_ENABLED
41 interrupt_n,
42 `endif
43 // From user logic
44 `ifdef CFG_USER_ENABLED
45 user_result,
46 user_complete,
47 `endif
48 `ifdef CFG_IWB_ENABLED
49 // Instruction Wishbone master
50 I_DAT_I,
51 I_ACK_I,
52 I_ERR_I,
53 I_RTY_I,
54 `endif
55 // Data Wishbone master
56 D_DAT_I,
57 D_ACK_I,
58 D_ERR_I,
59 D_RTY_I,
60 // Debug Slave port WishboneInterface
61 DEBUG_ADR_I,
62 DEBUG_DAT_I,
63 DEBUG_SEL_I,
64 DEBUG_WE_I,
65 DEBUG_CTI_I,
66 DEBUG_BTE_I,
67 DEBUG_LOCK_I,
68 DEBUG_CYC_I,
69 DEBUG_STB_I,
70 // ----- Outputs -------
71 `ifdef CFG_USER_ENABLED
72 user_valid,
73 user_opcode,
74 user_operand_0,
75 user_operand_1,
76 `endif
77 `ifdef CFG_IWB_ENABLED
78 // Instruction Wishbone master
79 I_DAT_O,
80 I_ADR_O,
81 I_CYC_O,
82 I_SEL_O,
83 I_STB_O,
84 I_WE_O,
85 I_CTI_O,
86 I_LOCK_O,
87 I_BTE_O,
88 `endif
89 // Data Wishbone master
90 D_DAT_O,
91 D_ADR_O,
92 D_CYC_O,
93 D_SEL_O,
94 D_STB_O,
95 D_WE_O,
96 D_CTI_O,
97 D_LOCK_O,
98 D_BTE_O,
99 // Debug Slave port WishboneInterface
100 DEBUG_ACK_O,
101 DEBUG_ERR_O,
102 DEBUG_RTY_O,
103 DEBUG_DAT_O
104 );
106 /////////////////////////////////////////////////////
107 // Inputs
108 /////////////////////////////////////////////////////
110 input clk_i; // Clock
111 input rst_i; // Reset
113 `ifdef CFG_INTERRUPTS_ENABLED
114 input [`LM32_INTERRUPT_RNG] interrupt_n; // Interrupt pins, active-low
115 `endif
117 `ifdef CFG_USER_ENABLED
118 input [`LM32_WORD_RNG] user_result; // User-defined instruction result
119 input user_complete; // Indicates the user-defined instruction result is valid
120 `endif
122 `ifdef CFG_IWB_ENABLED
123 input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data
124 input I_ACK_I; // Instruction Wishbone interface acknowledgement
125 input I_ERR_I; // Instruction Wishbone interface error
126 input I_RTY_I; // Instruction Wishbone interface retry
127 `endif
129 input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
130 input D_ACK_I; // Data Wishbone interface acknowledgement
131 input D_ERR_I; // Data Wishbone interface error
132 input D_RTY_I; // Data Wishbone interface retry
134 input [`LM32_WORD_RNG] DEBUG_ADR_I; // Debug monitor Wishbone interface address
135 input [`LM32_WORD_RNG] DEBUG_DAT_I; // Debug monitor Wishbone interface write data
136 input [`LM32_BYTE_SELECT_RNG] DEBUG_SEL_I; // Debug monitor Wishbone interface byte select
137 input DEBUG_WE_I; // Debug monitor Wishbone interface write enable
138 input [`LM32_CTYPE_RNG] DEBUG_CTI_I; // Debug monitor Wishbone interface cycle type
139 input [`LM32_BTYPE_RNG] DEBUG_BTE_I; // Debug monitor Wishbone interface burst type
140 input DEBUG_LOCK_I; // Debug monitor Wishbone interface locked transfer
141 input DEBUG_CYC_I; // Debug monitor Wishbone interface cycle
142 input DEBUG_STB_I; // Debug monitor Wishbone interface strobe
144 /////////////////////////////////////////////////////
145 // Outputs
146 /////////////////////////////////////////////////////
148 `ifdef CFG_USER_ENABLED
149 output user_valid; // Indicates that user_opcode and user_operand_* are valid
150 wire user_valid;
151 output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode
152 reg [`LM32_USER_OPCODE_RNG] user_opcode;
153 output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction
154 wire [`LM32_WORD_RNG] user_operand_0;
155 output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction
156 wire [`LM32_WORD_RNG] user_operand_1;
157 `endif
159 `ifdef CFG_IWB_ENABLED
160 output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data
161 wire [`LM32_WORD_RNG] I_DAT_O;
162 output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address
163 wire [`LM32_WORD_RNG] I_ADR_O;
164 output I_CYC_O; // Instruction Wishbone interface cycle
165 wire I_CYC_O;
166 output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select
167 wire [`LM32_BYTE_SELECT_RNG] I_SEL_O;
168 output I_STB_O; // Instruction Wishbone interface strobe
169 wire I_STB_O;
170 output I_WE_O; // Instruction Wishbone interface write enable
171 wire I_WE_O;
172 output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type
173 wire [`LM32_CTYPE_RNG] I_CTI_O;
174 output I_LOCK_O; // Instruction Wishbone interface lock bus
175 wire I_LOCK_O;
176 output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type
177 wire [`LM32_BTYPE_RNG] I_BTE_O;
178 `endif
180 output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
181 wire [`LM32_WORD_RNG] D_DAT_O;
182 output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
183 wire [`LM32_WORD_RNG] D_ADR_O;
184 output D_CYC_O; // Data Wishbone interface cycle
185 wire D_CYC_O;
186 output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select
187 wire [`LM32_BYTE_SELECT_RNG] D_SEL_O;
188 output D_STB_O; // Data Wishbone interface strobe
189 wire D_STB_O;
190 output D_WE_O; // Data Wishbone interface write enable
191 wire D_WE_O;
192 output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type
193 wire [`LM32_CTYPE_RNG] D_CTI_O;
194 output D_LOCK_O; // Date Wishbone interface lock bus
195 wire D_LOCK_O;
196 output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
197 wire [`LM32_BTYPE_RNG] D_BTE_O;
199 output DEBUG_ACK_O; // Debug monitor Wishbone ack
200 wire DEBUG_ACK_O;
201 output DEBUG_ERR_O; // Debug monitor Wishbone error
202 wire DEBUG_ERR_O;
203 output DEBUG_RTY_O; // Debug monitor Wishbone retry
204 wire DEBUG_RTY_O;
205 output [`LM32_WORD_RNG] DEBUG_DAT_O; // Debug monitor Wishbone read data
206 wire [`LM32_WORD_RNG] DEBUG_DAT_O;
208 /////////////////////////////////////////////////////
209 // Internal nets and registers
210 /////////////////////////////////////////////////////
212 `ifdef CFG_JTAG_ENABLED
213 // Signals between JTAG interface and CPU
214 wire [`LM32_BYTE_RNG] jtag_reg_d;
215 wire [`LM32_BYTE_RNG] jtag_reg_q;
216 wire jtag_update;
217 wire [2:0] jtag_reg_addr_d;
218 wire [2:0] jtag_reg_addr_q;
219 wire jtck;
220 wire jrstn;
221 `endif
223 `ifdef CFG_TRACE_ENABLED
224 // PC trace signals
225 wire [`LM32_PC_RNG] trace_pc; // PC to trace (address of next non-sequential instruction)
226 wire trace_pc_valid; // Indicates that a new trace PC is valid
227 wire trace_exception; // Indicates an exception has occured
228 wire [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured
229 wire trace_eret; // Indicates an eret instruction has been executed
230 `ifdef CFG_DEBUG_ENABLED
231 wire trace_bret; // Indicates a bret instruction has been executed
232 `endif
233 `endif
235 /////////////////////////////////////////////////////
236 // Functions
237 /////////////////////////////////////////////////////
239 `include "lm32_functions.v"
240 /////////////////////////////////////////////////////
241 // Instantiations
242 /////////////////////////////////////////////////////
244 // LM32 CPU
245 lm32_cpu cpu (
246 // ----- Inputs -------
247 .clk_i (clk_i),
248 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
249 .clk_n_i (clk_n),
250 `endif
251 .rst_i (rst_i),
252 // From external devices
253 `ifdef CFG_INTERRUPTS_ENABLED
254 .interrupt_n (interrupt_n),
255 `endif
256 // From user logic
257 `ifdef CFG_USER_ENABLED
258 .user_result (user_result),
259 .user_complete (user_complete),
260 `endif
261 `ifdef CFG_JTAG_ENABLED
262 // From JTAG
263 .jtag_clk (jtck),
264 .jtag_update (jtag_update),
265 .jtag_reg_q (jtag_reg_q),
266 .jtag_reg_addr_q (jtag_reg_addr_q),
267 `endif
268 `ifdef CFG_IWB_ENABLED
269 // Instruction Wishbone master
270 .I_DAT_I (I_DAT_I),
271 .I_ACK_I (I_ACK_I),
272 .I_ERR_I (I_ERR_I),
273 .I_RTY_I (I_RTY_I),
274 `endif
275 // Data Wishbone master
276 .D_DAT_I (D_DAT_I),
277 .D_ACK_I (D_ACK_I),
278 .D_ERR_I (D_ERR_I),
279 .D_RTY_I (D_RTY_I),
280 // ----- Outputs -------
281 `ifdef CFG_TRACE_ENABLED
282 .trace_pc (trace_pc),
283 .trace_pc_valid (trace_pc_valid),
284 .trace_exception (trace_exception),
285 .trace_eid (trace_eid),
286 .trace_eret (trace_eret),
287 `ifdef CFG_DEBUG_ENABLED
288 .trace_bret (trace_bret),
289 `endif
290 `endif
291 `ifdef CFG_JTAG_ENABLED
292 .jtag_reg_d (jtag_reg_d),
293 .jtag_reg_addr_d (jtag_reg_addr_d),
294 `endif
295 `ifdef CFG_USER_ENABLED
296 .user_valid (user_valid),
297 .user_opcode (user_opcode),
298 .user_operand_0 (user_operand_0),
299 .user_operand_1 (user_operand_1),
300 `endif
301 `ifdef CFG_IWB_ENABLED
302 // Instruction Wishbone master
303 .I_DAT_O (I_DAT_O),
304 .I_ADR_O (I_ADR_O),
305 .I_CYC_O (I_CYC_O),
306 .I_SEL_O (I_SEL_O),
307 .I_STB_O (I_STB_O),
308 .I_WE_O (I_WE_O),
309 .I_CTI_O (I_CTI_O),
310 .I_LOCK_O (I_LOCK_O),
311 .I_BTE_O (I_BTE_O),
312 `endif
313 // Data Wishbone master
314 .D_DAT_O (D_DAT_O),
315 .D_ADR_O (D_ADR_O),
316 .D_CYC_O (D_CYC_O),
317 .D_SEL_O (D_SEL_O),
318 .D_STB_O (D_STB_O),
319 .D_WE_O (D_WE_O),
320 .D_CTI_O (D_CTI_O),
321 .D_LOCK_O (D_LOCK_O),
322 .D_BTE_O (D_BTE_O)
323 );
325 wire TRACE_ACK_O;
326 wire [`LM32_WORD_RNG] TRACE_DAT_O;
327 `ifdef CFG_TRACE_ENABLED
328 lm32_trace trace_module (.clk_i (clk_i),
329 .rst_i (rst_i),
330 .stb_i (DEBUG_STB_I & DEBUG_ADR_I[13]),
331 .we_i (DEBUG_WE_I),
332 .sel_i (DEBUG_SEL_I),
333 .dat_i (DEBUG_DAT_I),
334 .adr_i (DEBUG_ADR_I),
335 .trace_pc (trace_pc),
336 .trace_eid (trace_eid),
337 .trace_eret (trace_eret),
338 .trace_bret (trace_bret),
339 .trace_pc_valid (trace_pc_valid),
340 .trace_exception (trace_exception),
341 .ack_o (TRACE_ACK_O),
342 .dat_o (TRACE_DAT_O));
343 `else
344 assign TRACE_ACK_O = 0;
345 assign TRACE_DAT_O = 0;
346 `endif
347 `ifdef DEBUG_ROM
348 wire ROM_ACK_O;
349 wire [`LM32_WORD_RNG] ROM_DAT_O;
351 assign DEBUG_ACK_O = DEBUG_ADR_I[13] ? TRACE_ACK_O : ROM_ACK_O;
352 assign DEBUG_DAT_O = DEBUG_ADR_I[13] ? TRACE_DAT_O : ROM_DAT_O;
354 // ROM monitor
355 lm32_monitor debug_rom (
356 // ----- Inputs -------
357 .clk_i (clk_i),
358 .rst_i (rst_i),
359 .MON_ADR_I (DEBUG_ADR_I),
360 .MON_STB_I (DEBUG_STB_I & ~DEBUG_ADR_I[13]),
361 .MON_CYC_I (DEBUG_CYC_I & ~DEBUG_ADR_I[13]),
362 .MON_WE_I (DEBUG_WE_I),
363 .MON_SEL_I (DEBUG_SEL_I),
364 .MON_DAT_I (DEBUG_DAT_I),
365 .MON_CTI_I (DEBUG_CTI_I),
366 .MON_BTE_I (DEBUG_BTE_I),
367 .MON_LOCK_I (DEBUG_LOCK_I),
368 // ----- Outputs ------
369 .MON_RTY_O (DEBUG_RTY_O),
370 .MON_ERR_O (DEBUG_ERR_O),
371 .MON_ACK_O (ROM_ACK_O),
372 .MON_DAT_O (ROM_DAT_O)
373 );
374 `endif
376 `ifdef CFG_JTAG_ENABLED
377 // JTAG cores
378 jtag_cores jtag_cores (
379 // ----- Inputs -----
380 `ifdef INCLUDE_LM32
381 .reg_d (jtag_reg_d),
382 .reg_addr_d (jtag_reg_addr_d),
383 `endif
384 // ----- Outputs -----
385 `ifdef INCLUDE_LM32
386 .reg_update (jtag_update),
387 .reg_q (jtag_reg_q),
388 .reg_addr_q (jtag_reg_addr_q),
389 `endif
390 .jtck (jtck),
391 .jrstn (jrstn)
392 );
393 `endif
395 endmodule