document/lm32.htm

Sun, 06 Mar 2011 21:04:44 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 06 Mar 2011 21:04:44 +0000
changeset 20
b6d814c2947c
parent 8
07be9df9fee8
child 22
35dc7ba83714
permissions
-rw-r--r--

Fix file modes

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   130 <h1>LatticeMico32 Processor &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<a title="View Reference Manual" href="lm32_archman.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Reference Manual');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1>
   132 <p>The LatticeMico32 processor is a high-performance 32-bit microprocessor 
   133  optimized for Lattice Semiconductor field-programmable gate arrays. </p>
   135 <p class="whs2"><span style="font-style: italic;"><I>*If the 
   136  processor manual fails to open, see the note at the bottom of this page.</I></span></p>
   138 <h2>Revision History</h2>
   140 <table x-use-null-cells cellspacing="0" width="738" height="84" class="whs3">
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   143 //--></script>
   144 <col class="whs4">
   145 <col class="whs5">
   147 <tr valign="top" class="whs6">
   148 <td bgcolor="#DEE8F4" width="93px" class="whs7">
   149 <p class=Table
   150 	style="font-weight: bold;">Version</td>
   151 <td bgcolor="#DEE8F4" width="598px" class="whs8">
   152 <p class=Table
   153 	style="font-weight: bold;">Description</td></tr>
   155 <tr valign="top" class="whs6">
   156 <td colspan="1" rowspan="1" width="93px" class="whs9">
   157 <p class=Table
   158 	style="font-weight: normal;">3.5</td>
   159 <td colspan="1" rowspan="1" width="598px" class="whs10">
   160 <p class=whs10
   161 	style="margin-left: 0px;">Support added to allow Inline Memories to 
   162  be generated as non-power-of-two, as long as they are a multiple of 1024 
   163  bytes</td></tr>
   165 <tr valign="top" class="whs6">
   166 <td colspan="1" rowspan="1" width="93px" class="whs9">
   167 <p class=Table
   168 	style="font-weight: normal;">3.3</td>
   169 <td colspan="1" rowspan="1" width="598px" class="whs10">
   170 <p class=whs10
   171 	style="margin-left: 0px;">Added Inline Memory to support on-chip memory 
   172  connected through a local bus.</td></tr>
   174 <tr valign="top" class="whs6">
   175 <td colspan="1" rowspan="1" width="93px" class="whs9">
   176 <p class=Table
   177 	style="font-weight: normal;">3.2</td>
   178 <td colspan="1" rowspan="1" width="598px" class="whs10">
   179 <p class=whs10
   180 	style="margin-left: 0px;">Added Memory Type to instruction cache and 
   181  data cache.</td></tr>
   183 <tr valign="top" class="whs6">
   184 <td colspan="1" rowspan="1" width="93px" class="whs9">
   185 <p class=Table
   186 	style="font-weight: normal;">3.1</td>
   187 <td colspan="1" rowspan="1" width="598px" class="whs10">
   188 <p class="whs11">Added static predictor to improve the behavior 
   189  of branches.</p>
   190 <p class="whs11">Added support for optionally mapping the register 
   191  file to EBRs (on-chip memory).</p>
   192 <p class="whs11">Added support for selecting between distributed 
   193  RAM and EBRs (pseudo-dual port or true-dual port) for instruction and 
   194  data caches.</td></tr>
   196 <tr valign="top" class="whs6">
   197 <td colspan="1" rowspan="1" width="93px" class="whs9">
   198 <p class=Table
   199 	style="font-weight: normal;"><span style="font-weight: normal;">3.0 
   200  </span></td>
   201 <td colspan="1" rowspan="1" width="598px" class="whs10">
   202 <p class="whs11">Fixed incorrect handling of data cache miss 
   203  in the presence of an instruction cache miss.</td></tr>
   205 <tr valign="top" class="whs6">
   206 <td colspan="1" rowspan="1" width="93px" class="whs9">
   207 <p class="whs11">1.0</td>
   208 <td colspan="1" rowspan="1" width="598px" class="whs10">
   209 <p class="whs11">Initial version.</td></tr>
   210 <script language='JavaScript'><!--
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   213 </table>
   215 &nbsp; 
   217 <h2>Dialog Box Parameters &#8211; 
   218  General Tab</h2>
   220 <table x-use-null-cells cellspacing="0" class="whs12">
   221 <col class="whs13">
   222 <col class="whs14">
   224 <tr valign="top" class="whs15">
   225 <td bgcolor="#DEE8F4" width="167px" class="whs16">
   226 <p class=Table
   227 	style="font-weight: bold;">Parameter</td>
   228 <td bgcolor="#DEE8F4" width="524px" class="whs17">
   229 <p class=Table
   230 	style="font-weight: bold;">Description</td></tr>
   232 <tr valign="top" class="whs15">
   233 <td colspan="1" rowspan="1" width="167px" class="whs18">
   234 <p class=Table
   235 	style="font-weight: normal;">Instance Name</td>
   236 <td colspan="1" rowspan="1" width="524px" class="whs19">
   237 <p class=Table
   238 	style="margin-left: 14px;">Specifies the name of the LatticeMico32 
   239  processor. Alphanumeric values and underscores are supported. The default 
   240  is LM32.</td></tr>
   242 <tr valign="top" class="whs15">
   243 <td colspan="2" rowspan="1" width="691px" class="whs20">
   244 <p class=Table
   245 	style="font-weight: bold;">Settings</td>
   246 </tr>
   248 <tr valign="top" class="whs15">
   249 <td colspan="1" rowspan="1" width="167px" class="whs18">
   250 <p class=Table>Use EBRs for Register File</td>
   251 <td colspan="1" rowspan="1" width="524px" class="whs21">
   252 <p class=Table>Uses embedded block RAMS for the register file.</td></tr>
   254 <tr valign="top" class="whs15">
   255 <td colspan="1" rowspan="1" width="167px" class="whs18">
   256 <p class=Table>Enable Divide</td>
   257 <td colspan="1" rowspan="1" width="524px" class="whs21">
   258 <p class=Table>Enables the divide and modulus instructions (<span style="font-family: Verdana, sans-serif;">divu, 
   259  modu</span>).</td></tr>
   261 <tr valign="top" class="whs15">
   262 <td colspan="1" rowspan="1" width="167px" class="whs18">
   263 <p class=Table>Enable Sign Extend</td>
   264 <td colspan="1" rowspan="1" width="524px" class="whs21">
   265 <p class=Table>Enables the sign-extension instructions (<span style="font-family: Verdana, sans-serif;">sextb, 
   266  sexth</span><span style="font-family: Arial, sans-serif;">)</span>.</td></tr>
   268 <tr valign="top" class="whs15">
   269 <td colspan="1" rowspan="1" width="167px" class="whs18">
   270 <p class=Table>Location of Exception Handlers</td>
   271 <td colspan="1" rowspan="1" width="524px" class="whs21">
   272 <p class=Table>Specifies the default value for the vector table. This can 
   273  be changed by updating the EBA control register or status register.</p>
   274 <p class=Table>This address must be aligned to a 256-byte boundary, since 
   275  the hardware ignores the least-significant byte. Unpredictable behavior 
   276  occurs when the exception base address and the exception vectors are not 
   277  aligned on a 256-byte boundary.</td></tr>
   279 <tr valign="top" class="whs15">
   280 <td colspan="2" rowspan="1" width="691px" class="whs20">
   281 <p class=Table
   282 	style="font-weight: bold;">Multiplier Settings</td>
   283 </tr>
   285 <tr valign="top" class="whs15">
   286 <td colspan="1" rowspan="1" width="167px" class="whs18">
   287 <p class=Table>Enable Multiplier</td>
   288 <td colspan="1" rowspan="1" width="524px" class="whs21">
   289 <p class=Table>Enables the multiply instructions (<span style="font-family: Verdana, sans-serif;">mul, 
   290  muli)</span>.</td></tr>
   292 <tr valign="top" class="whs15">
   293 <td colspan="1" rowspan="1" width="167px" class="whs18">
   294 <p class=Table>Enable Pipelined Multiplier (DSP Block if available)</td>
   295 <td colspan="1" rowspan="1" width="524px" class="whs21">
   296 <p class=Table>Enables the multiplier using the DSP block, if available.</td></tr>
   298 <tr valign="top" class="whs15">
   299 <td colspan="1" rowspan="1" width="167px" class="whs18">
   300 <p class=Table>Enable Multicycle (LUT-based, 32 cycles) Multiplier</td>
   301 <td colspan="1" rowspan="1" width="524px" class="whs21">
   302 <p class=Table>Enables the multiplier using LUTs.</td></tr>
   304 <tr valign="top" class="whs15">
   305 <td colspan="2" rowspan="1" width="691px" class="whs20">
   306 <p class=Table
   307 	style="font-weight: bold;">Instruction Cache</td>
   308 </tr>
   310 <tr valign="top" class="whs15">
   311 <td colspan="1" rowspan="1" width="167px" class="whs18">
   312 <p class=Table>Instruction Cache Enabled</td>
   313 <td colspan="1" rowspan="1" width="524px" class="whs19">
   314 <p class=Table
   315 	style="margin-left: 14px;">Determines whether an instruction cache 
   316  is implemented.</td></tr>
   318 <tr valign="top" class="whs15">
   319 <td colspan="1" rowspan="1" width="167px" class="whs18">
   320 <p class=Table>Number of Sets</td>
   321 <td colspan="1" rowspan="1" width="524px" class="whs19">
   322 <p class=Table
   323 	style="margin-left: 14px;">Specifies the number of sets in the instruction 
   324  cache. Supported values are 128, 256, 512, 1024.</td></tr>
   326 <tr valign="top" class="whs15">
   327 <td colspan="1" rowspan="1" width="167px" class="whs18">
   328 <p class=Table>Set Associativity</td>
   329 <td colspan="1" rowspan="1" width="524px" class="whs19">
   330 <p class=Table
   331 	style="margin-left: 14px;">Specifies the associativity of the instruction 
   332  cache. Supported values are 1, 2.</td></tr>
   334 <tr valign="top" class="whs15">
   335 <td colspan="1" rowspan="1" width="167px" class="whs18">
   336 <p class=Table>Bytes/Cache Line</td>
   337 <td colspan="1" rowspan="1" width="524px" class="whs19">
   338 <p class=Table
   339 	style="margin-left: 15px;">Specifies the number of bytes per instruction 
   340  cache line. Supported values are 4, 8, 16.</td></tr>
   342 <tr valign="top" class="whs15">
   343 <td colspan="1" rowspan="1" width="167px" class="whs18">
   344 <p class=Table>Memory Type</td>
   345 <td colspan="1" rowspan="1" width="524px" class="whs19">
   346 <p class=Table
   347 	style="margin-left: 15px;">Determines the FPGA resource to be used 
   348  to implement the instruction cache. The decision can be left to the synthesis 
   349  tool (Auto), or you can select from the following options:</p>
   350 <ul type="disc" class="whs22">
   352 	<li class=kadov-p-CBullet><p class=Bullet>Auto &#8211; 
   353  Leaves the implementation of the instruction cache to the synthesis tool.</p></li>
   355 	<li class=kadov-p-CBullet><p class=Bullet>Distributed RAM &#8211; 
   356  Implements the instruction cache as distributed RAM.</p></li>
   358 	<li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR &#8211; 
   359  Implements the instruction cache as dual-port EBR (two read/write ports).</p></li>
   361 	<li class=kadov-p-CBullet><p class=Bullet>Pseudo Dual-Port EBR &#8211; Implements 
   362  the instruction cache as pseudo-dual-port EBR (one read port and one write 
   363  port). </p></li>
   364 </ul></td></tr>
   366 <tr valign="top" class="whs15">
   367 <td colspan="2" rowspan="1" width="691px" class="whs20">
   368 <p class=Table
   369 	style="font-weight: bold;">Debug Setting</td>
   370 </tr>
   372 <tr valign="top" class="whs15">
   373 <td colspan="1" rowspan="1" width="167px" class="whs18">
   374 <p class=Table>Enable Debug Interface</td>
   375 <td colspan="1" rowspan="1" width="524px" class="whs21">
   376 <p class=Table>Includes the debugger stub in the CPU, which is required 
   377  for debugging.</td></tr>
   379 <tr valign="top" class="whs15">
   380 <td colspan="1" rowspan="1" width="167px" class="whs18">
   381 <p class=Table># of H/W Watchpoint Registers</td>
   382 <td colspan="1" rowspan="1" width="524px" class="whs21">
   383 <p class=Table
   384 	style="font-weight: normal;">Specifies the number of hardware watchpoint 
   385  registers to be used in the debugging process.</td></tr>
   387 <tr valign="top" class="whs15">
   388 <td colspan="1" rowspan="1" width="167px" class="whs18">
   389 <p class=Table>Enable Debugging Code in Flash or ROM</td>
   390 <td colspan="1" rowspan="1" width="524px" class="whs21">
   391 <p class=Table
   392 	style="font-weight: normal;">Enables you to set hardware breakpoints 
   393  in read-only memory.</td></tr>
   395 <tr valign="top" class="whs15">
   396 <td colspan="1" rowspan="1" width="167px" class="whs18">
   397 <p class=Table># of H/W Breakpoint Registers</td>
   398 <td colspan="1" rowspan="1" width="524px" class="whs21">
   399 <p class=Table>Specifies the number of hardware breakpoint registers to 
   400  be used in the debugging process.</td></tr>
   402 <tr valign="top" class="whs15">
   403 <td colspan="1" rowspan="1" width="167px" class="whs18">
   404 <p class=Table>Enable PC Trace</td>
   405 <td colspan="1" rowspan="1" width="524px" class="whs21">
   406 <p class=Table>Enables the Program Counter Trace feature, which enables 
   407  you to run the program trace during debug to find items in your C or C++ 
   408  Code during debug, such as breakpoints and exceptions. Refer to <span 
   409  style="font-weight: bold;"><B>Help &gt; Help Contents &gt; Lattice Software 
   410  Project Environment &gt; Concepts &gt; Program Counter Trace</B></span> for 
   411  more information on Program Counter Trace.</td></tr>
   413 <tr valign="top" class="whs15">
   414 <td colspan="1" rowspan="1" width="167px" class="whs18">
   415 <p class=Table>Trace Depth</td>
   416 <td colspan="1" rowspan="1" width="524px" class="whs21">
   417 <p class=Table>Enables you to specify the depth of the Program Counter 
   418  Trace buffer. Refer to <span style="font-weight: bold;"><B>Help &gt; Help 
   419  Contents &gt; Lattice Software Project Environment &nbsp;&gt; 
   420  Concepts &gt; Program Counter Trace</B></span> for more information on Program 
   421  Counter Trace.</td></tr>
   423 <tr valign="top" class="whs15">
   424 <td colspan="2" rowspan="1" width="691px" class="whs20">
   425 <p class=Table
   426 	style="font-weight: bold;">Shifter Settings</td>
   427 </tr>
   429 <tr valign="top" class="whs15">
   430 <td colspan="1" rowspan="1" width="167px" class="whs18">
   431 <p class=Table>Enable Shifter</td>
   432 <td colspan="1" rowspan="1" width="524px" class="whs19">
   433 <p>Enables the multi-bit shift instructions (sr, sri, sru, srui, sl, sli). 
   434  </td></tr>
   436 <tr valign="top" class="whs15">
   437 <td colspan="1" rowspan="1" width="167px" class="whs18">
   438 <p class=Table>Enable Piplined Barrel Shifter</td>
   439 <td colspan="1" rowspan="1" width="524px" class="whs19">
   440 <p>Enables the barrel shifter to be pipelined. The barrel shifter is implemented 
   441  to perform a shift operation in three cycles.</td></tr>
   443 <tr valign="top" class="whs15">
   444 <td colspan="1" rowspan="1" width="167px" class="whs18">
   445 <p class=Table>Enable Multicycle Barrel Shifter (up to 32 cycles)</td>
   446 <td colspan="1" rowspan="1" width="524px" class="whs19">
   447 <p>Enables multi-cycle shift operation for the barrel shifter. The barrel 
   448  shifter is implemented to shift one bit per cycle and take thirty-two 
   449  cycles to complete.</td></tr>
   451 <tr valign="top" class="whs15">
   452 <td colspan="2" rowspan="1" width="691px" class="whs20">
   453 <p class=Table><span style="font-weight: bold;"><B>Data Cache</B></span></td>
   454 </tr>
   456 <tr valign="top" class="whs15">
   457 <td colspan="1" rowspan="1" width="167px" class="whs18">
   458 <p class=Table>Data Cache Enabled</td>
   459 <td colspan="1" rowspan="1" width="524px" class="whs21">
   460 <p class=Table>Determines whether a data cache is implemented.</td></tr>
   462 <tr valign="top" class="whs15">
   463 <td colspan="1" rowspan="1" width="167px" class="whs18">
   464 <p class=Table>Number of Sets</td>
   465 <td colspan="1" rowspan="1" width="524px" class="whs21">
   466 <p class=Table>Specifies the number of sets in the data cache. Supported 
   467  values are 128, 256, 512, 1024.</td></tr>
   469 <tr valign="top" class="whs15">
   470 <td colspan="1" rowspan="1" width="167px" class="whs18">
   471 <p class=Table>Set Associativity</td>
   472 <td colspan="1" rowspan="1" width="524px" class="whs21">
   473 <p class=Table>Specifies the associativity of the data cache. Supported 
   474  values are 1, 2.</td></tr>
   476 <tr valign="top" class="whs15">
   477 <td colspan="1" rowspan="1" width="167px" class="whs18">
   478 <p class=Table>Bytes/Cache Line</td>
   479 <td colspan="1" rowspan="1" width="524px" class="whs21">
   480 <p class=Table>Specifies the number of bytes per data cache line. Supported 
   481  values are 4, 8, 16.</td></tr>
   483 <tr valign="top" class="whs15">
   484 <td colspan="1" rowspan="1" width="167px" class="whs23">
   485 <p class=Table>Memory Type</td>
   486 <td colspan="1" rowspan="1" width="524px" class="whs24">
   487 <p class=Table>Determines the FPGA resource to be used to implement the 
   488  data cache. The decision can be left to the synthesis tool (Auto), or 
   489  you can select from the following options:</p>
   490 <ul>
   492 	<li class=kadov-p-CBullet><p class=Bullet>Auto &#8211; 
   493  Leaves the implementation of the data cache to the synthesis tool.</p></li>
   495 	<li class=kadov-p-CBullet><p class=Bullet>Distributed RAM &#8211; 
   496  Implements the data cache as distributed RAM.</p></li>
   498 	<li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR &#8211; 
   499  Implements the data cache as dual-port EBR (two read/write ports).</p></li>
   500 </ul></td></tr>
   501 </table>
   503 <p>&nbsp;</p>
   505 <h2>Dialog Box Parameters &#8211; 
   506  Inline Memory Tab</h2>
   508 <table x-use-null-cells cellspacing="0" class="whs12">
   509 <col class="whs13">
   510 <col class="whs14">
   512 <tr valign="top" class="whs15">
   513 <td bgcolor="#DEE8F4" width="167px" class="whs25">
   514 <p class=Table
   515 	style="font-weight: bold;">Parameter</td>
   516 <td bgcolor="#DEE8F4" width="524px" class="whs26">
   517 <p class=Table
   518 	style="font-weight: bold;">Description</td></tr>
   520 <tr valign="top" class="whs15">
   521 <td rowspan="1" colspan="2" width="691px" class="whs27">
   522 <p class=Table
   523 	style="font-weight: bold;">Instruction Inline Memory</td>
   524 </tr>
   526 <tr valign="top" class="whs15">
   527 <td width="167px" class="whs28">
   528 <p class=Table>Enable</td>
   529 <td width="524px" class="whs29">
   530 <p class=Table>Enables the instruction inline memory</td></tr>
   532 <tr valign="top" class="whs15">
   533 <td width="167px" class="whs28">
   534 <p class=Table>Instance Name</td>
   535 <td width="524px" class="whs29">
   536 <p class=Table>Specifics the name of the instruction inline memory. Alphanumeric 
   537  values and underscores are supported. The default is Instruction_IM.</td></tr>
   539 <tr valign="top" class="whs15">
   540 <td width="167px" class="whs28">
   541 <p class=Table>Base Address</td>
   542 <td width="524px" class="whs29">
   543 <p class=Table>Specifies the base address for the instruction inline memory. 
   544  The default is 0x10000000.</td></tr>
   546 <tr valign="top" class="whs15">
   547 <td width="167px" class="whs28">
   548 <p class=Table>Size of Memory in Bytes</td>
   549 <td width="524px" class="whs29">
   550 <p class=Table>Specifies the size of the instruction inline memory.</td></tr>
   552 <tr valign="top" class="whs15">
   553 <td rowspan="1" colspan="2" width="691px" class="whs27">
   554 <p class=Table><span style="font-weight: bold;"><B>Memory File</B></span></td>
   555 </tr>
   557 <tr valign="top" class="whs15">
   558 <td width="167px" class="whs28">
   559 <p class=Table>Initialization File Name</td>
   560 <td width="524px" class="whs29">
   561 <p class=Table>Specifies the name of the memory initialization file for 
   562  instruction inline memory.</td></tr>
   564 <tr valign="top" class="whs15">
   565 <td width="167px" class="whs28">
   566 <p class=Table>File Format</td>
   567 <td width="524px" class="whs29">
   568 <p class=Table>Specifies the format of the memory initialization file: 
   569  hex or binary.</td></tr>
   571 <tr valign="top" class="whs15">
   572 <td rowspan="1" colspan="2" width="691px" class="whs27">
   573 <p class=Table
   574 	style="font-weight: bold;">Data Inline Memory</td>
   575 </tr>
   577 <tr valign="top" class="whs15">
   578 <td width="167px" class="whs28">
   579 <p class=Table>Enabled</td>
   580 <td width="524px" class="whs29">
   581 <p class=Table>Enables the data inline memory.</td></tr>
   583 <tr valign="top" class="whs15">
   584 <td width="167px" class="whs28">
   585 <p class=Table>Instance Name</td>
   586 <td width="524px" class="whs29">
   587 <p class=Table>Specifies the name of the data inline memory. Alphanumeric 
   588  values and underscores are supported. The default is Data_IM.</td></tr>
   590 <tr valign="top" class="whs15">
   591 <td width="167px" class="whs28">
   592 <p class=Table>Base Address</td>
   593 <td width="524px" class="whs29">
   594 <p class=Table>Specifies the base address for the data inline memory. The 
   595  default is 0x20000000.</td></tr>
   597 <tr valign="top" class="whs15">
   598 <td width="167px" class="whs28">
   599 <p class=Table>Size of Memory in Bytes</td>
   600 <td width="524px" class="whs29">
   601 <p class=Table>Specifies the size of the data inline memory.</td></tr>
   603 <tr valign="top" class="whs15">
   604 <td colspan="2" rowspan="1" width="691px" class="whs27">
   605 <p class=Table
   606 	style="font-weight: bold;">Memory File</td>
   607 </tr>
   609 <tr valign="top" class="whs15">
   610 <td colspan="1" rowspan="1" width="167px" class="whs28">
   611 <p class=Table>Initialization File Name</td>
   612 <td colspan="1" rowspan="1" width="524px" class="whs29">
   613 <p class=Table>Specifies the name of the memory initialization file for 
   614  data inline memory.</td></tr>
   616 <tr valign="top" class="whs15">
   617 <td colspan="1" rowspan="1" width="167px" class="whs30">
   618 <p class=Table>File Format</td>
   619 <td colspan="1" rowspan="1" width="524px" class="whs31">
   620 <p class=Table>Specifies the format of the memory initialization file: 
   621  hex or binary.</td></tr>
   622 </table>
   624 <p>&nbsp;</p>
   626 <p>For the revision history of the component RTL files, refer to the header 
   627  of each component Verilog source file. </p>
   629 <p><span style="font-weight: bold;"><B>Note</B></span>: If the processor manual 
   630  fails to open, click <img src="qm_icon.jpg" x-maintain-ratio="TRUE" width="14px" height="16px" border="0" class="img_whs32"> on the Available Components toolbar, 
   631  and then click the note button.</p>
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