Fri, 13 Aug 2010 01:16:35 +0100
Added tag LM32_V3_5_WITH_PATCHES for changeset 0eb235b23d55
1 // =============================================================================
2 // COPYRIGHT NOTICE
3 // Copyright 2006 (c) Lattice Semiconductor Corporation
4 // ALL RIGHTS RESERVED
5 // This confidential and proprietary software may be used only as authorised by
6 // a licensing agreement from Lattice Semiconductor Corporation.
7 // The entire notice above must be reproduced on all authorized copies and
8 // copies may only be made to the extent permitted by a licensing agreement from
9 // Lattice Semiconductor Corporation.
10 //
11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12 // 5555 NE Moore Court 408-826-6000 (other locations)
13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
14 // U.S.A email: techsupport@latticesemi.com
15 // =============================================================================/
16 // FILE DETAILS
17 // Project : LatticeMico32
18 // File : lm32_monitor.v
19 // Title : Debug monitor memory Wishbone interface
20 // Version : 6.1.17
21 // : Initial Release
22 // Version : 7.0SP2, 3.0
23 // : No Change
24 // Version : 3.3
25 // : Removed port mismatch in instantiation of module
26 // : lm32_monitor_ram.
27 // =============================================================================
29 `include "system_conf.v"
30 `include "lm32_include.v"
32 /////////////////////////////////////////////////////
33 // Module interface
34 /////////////////////////////////////////////////////
36 module lm32_monitor (
37 // ----- Inputs -------
38 clk_i,
39 rst_i,
40 MON_ADR_I,
41 MON_CYC_I,
42 MON_DAT_I,
43 MON_SEL_I,
44 MON_STB_I,
45 MON_WE_I,
46 // ----- Outputs -------
47 MON_ACK_O,
48 MON_RTY_O,
49 MON_DAT_O,
50 MON_ERR_O
51 );
53 /////////////////////////////////////////////////////
54 // Inputs
55 /////////////////////////////////////////////////////
57 input clk_i; // Wishbone clock
58 input rst_i; // Wishbone reset
59 input [10:2] MON_ADR_I; // Wishbone address
60 input MON_STB_I; // Wishbone strobe
61 input MON_CYC_I; // Wishbone cycle
62 input [`LM32_WORD_RNG] MON_DAT_I; // Wishbone write data
63 input [`LM32_BYTE_SELECT_RNG] MON_SEL_I; // Wishbone byte select
64 input MON_WE_I; // Wishbone write enable
66 /////////////////////////////////////////////////////
67 // Outputs
68 /////////////////////////////////////////////////////
70 output MON_ACK_O; // Wishbone acknowlege
71 reg MON_ACK_O;
72 output [`LM32_WORD_RNG] MON_DAT_O; // Wishbone data output
73 reg [`LM32_WORD_RNG] MON_DAT_O;
74 output MON_RTY_O; // Wishbone retry
75 wire MON_RTY_O;
76 output MON_ERR_O; // Wishbone error
77 wire MON_ERR_O;
79 /////////////////////////////////////////////////////
80 // Internal nets and registers
81 /////////////////////////////////////////////////////
83 reg [1:0] state; // Current state of FSM
84 wire [`LM32_WORD_RNG] data, dataB; // Data read from RAM
85 reg write_enable; // RAM write enable
86 reg [`LM32_WORD_RNG] write_data; // RAM write data
88 /////////////////////////////////////////////////////
89 // Instantiations
90 /////////////////////////////////////////////////////
92 lm32_monitor_ram ram (
93 // ----- Inputs -------
94 .ClockA (clk_i),
95 .ClockB (clk_i),
96 .ResetA (rst_i),
97 .ResetB (rst_i),
98 .ClockEnA (`TRUE),
99 .ClockEnB (`FALSE),
100 .AddressA (MON_ADR_I[10:2]),
101 .AddressB (9'b0),
102 .DataInA (write_data),
103 .DataInB (32'b0),
104 .WrA (write_enable),
105 .WrB (`FALSE),
106 // ----- Outputs -------
107 .QA (data),
108 .QB (dataB)
109 );
111 /////////////////////////////////////////////////////
112 // Combinational Logic
113 /////////////////////////////////////////////////////
115 assign MON_RTY_O = `FALSE;
116 assign MON_ERR_O = `FALSE;
118 /////////////////////////////////////////////////////
119 // Sequential Logic
120 /////////////////////////////////////////////////////
122 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
123 begin
124 if (rst_i == `TRUE)
125 begin
126 write_enable <= `FALSE;
127 MON_ACK_O <= `FALSE;
128 MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
129 state <= 2'b00;
130 end
131 else
132 begin
133 case (state)
134 2'b00:
135 begin
136 // Wait for a Wishbone access
137 if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE))
138 state <= 2'b01;
139 end
140 2'b01:
141 begin
142 // Output read data to Wishbone
143 MON_ACK_O <= `TRUE;
144 MON_DAT_O <= data;
145 // Sub-word writes are performed using read-modify-write
146 // as the Lattice EBRs don't support byte enables
147 if (MON_WE_I == `TRUE)
148 write_enable <= `TRUE;
149 write_data[7:0] <= MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0];
150 write_data[15:8] <= MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8];
151 write_data[23:16] <= MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16];
152 write_data[31:24] <= MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24];
153 state <= 2'b10;
154 end
155 2'b10:
156 begin
157 // Wishbone access occurs in this cycle
158 write_enable <= `FALSE;
159 MON_ACK_O <= `FALSE;
160 MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
161 state <= 2'b00;
162 end
163 endcase
164 end
165 end
167 endmodule