Sat, 06 Aug 2011 01:26:56 +0100
remove synthesis delay entities to ease merge
1 // ==================================================================
2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
3 // ------------------------------------------------------------------
4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
5 // ALL RIGHTS RESERVED
6 // ------------------------------------------------------------------
7 //
8 // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
9 //
10 // Permission:
11 //
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14 // Open Source License Agreement.
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17 //
18 // Lattice Semiconductor provides no warranty regarding the use or
19 // functionality of this code. It is the user's responsibility to
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21 // the use of formal verification methods.
22 //
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36 // --------------------------------------------------------------------
37 // FILE DETAILS
38 // Project : LatticeMico32
39 // File : lm32_interrupt.v
40 // Title : Interrupt logic
41 // Dependencies : lm32_include.v
42 // Version : 6.1.17
43 // : Initial Release
44 // Version : 7.0SP2, 3.0
45 // : No Change
46 // Version : 3.1
47 // : No Change
48 // =============================================================================
50 `include "lm32_include.v"
52 /////////////////////////////////////////////////////
53 // Module interface
54 /////////////////////////////////////////////////////
56 module lm32_interrupt (
57 // ----- Inputs -------
58 clk_i,
59 rst_i,
60 // From external devices
61 interrupt_n,
62 // From pipeline
63 stall_x,
64 `ifdef CFG_DEBUG_ENABLED
65 non_debug_exception,
66 debug_exception,
67 `else
68 exception,
69 `endif
70 eret_q_x,
71 `ifdef CFG_DEBUG_ENABLED
72 bret_q_x,
73 `endif
74 csr,
75 csr_write_data,
76 csr_write_enable,
77 // ----- Outputs -------
78 interrupt_exception,
79 // To pipeline
80 csr_read_data
81 );
83 /////////////////////////////////////////////////////
84 // Parameters
85 /////////////////////////////////////////////////////
87 parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts
89 /////////////////////////////////////////////////////
90 // Inputs
91 /////////////////////////////////////////////////////
93 input clk_i; // Clock
94 input rst_i; // Reset
96 input [interrupts-1:0] interrupt_n; // Interrupt pins, active-low
98 input stall_x; // Stall X pipeline stage
100 `ifdef CFG_DEBUG_ENABLED
101 input non_debug_exception; // Non-debug related exception has been raised
102 input debug_exception; // Debug-related exception has been raised
103 `else
104 input exception; // Exception has been raised
105 `endif
106 input eret_q_x; // Return from exception
107 `ifdef CFG_DEBUG_ENABLED
108 input bret_q_x; // Return from breakpoint
109 `endif
111 input [`LM32_CSR_RNG] csr; // CSR read/write index
112 input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
113 input csr_write_enable; // CSR write enable
115 /////////////////////////////////////////////////////
116 // Outputs
117 /////////////////////////////////////////////////////
119 output interrupt_exception; // Request to raide an interrupt exception
120 wire interrupt_exception;
122 output [`LM32_WORD_RNG] csr_read_data; // Data read from CSR
123 reg [`LM32_WORD_RNG] csr_read_data;
125 /////////////////////////////////////////////////////
126 // Internal nets and registers
127 /////////////////////////////////////////////////////
129 wire [interrupts-1:0] asserted; // Which interrupts are currently being asserted
130 //pragma attribute asserted preserve_signal true
131 wire [interrupts-1:0] interrupt_n_exception;
133 // Interrupt CSRs
135 reg ie; // Interrupt enable
136 reg eie; // Exception interrupt enable
137 `ifdef CFG_DEBUG_ENABLED
138 reg bie; // Breakpoint interrupt enable
139 `endif
140 reg [interrupts-1:0] ip; // Interrupt pending
141 reg [interrupts-1:0] im; // Interrupt mask
143 /////////////////////////////////////////////////////
144 // Combinational Logic
145 /////////////////////////////////////////////////////
147 // Determine which interrupts have occured and are unmasked
148 assign interrupt_n_exception = ip & im;
150 // Determine if any unmasked interrupts have occured
151 assign interrupt_exception = (|interrupt_n_exception) & ie;
153 // Determine which interrupts are currently being asserted (active-low) or are already pending
154 assign asserted = ip | ~interrupt_n;
156 assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
157 `ifdef CFG_DEBUG_ENABLED
158 bie,
159 `else
160 1'b0,
161 `endif
162 eie,
163 ie
164 };
165 assign ip_csr_read_data = ip;
166 assign im_csr_read_data = im;
167 generate
168 if (interrupts > 1)
169 begin
170 // CSR read
171 always @(*)
172 begin
173 case (csr)
174 `LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
175 `ifdef CFG_DEBUG_ENABLED
176 bie,
177 `else
178 1'b0,
179 `endif
180 eie,
181 ie
182 };
183 `LM32_CSR_IP: csr_read_data = ip;
184 `LM32_CSR_IM: csr_read_data = im;
185 default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
186 endcase
187 end
188 end
189 else
190 begin
191 // CSR read
192 always @(*)
193 begin
194 case (csr)
195 `LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
196 `ifdef CFG_DEBUG_ENABLED
197 bie,
198 `else
199 1'b0,
200 `endif
201 eie,
202 ie
203 };
204 `LM32_CSR_IP: csr_read_data = ip;
205 default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
206 endcase
207 end
208 end
209 endgenerate
211 /////////////////////////////////////////////////////
212 // Sequential Logic
213 /////////////////////////////////////////////////////
215 generate
216 if (interrupts > 1)
217 begin
218 // IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
219 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
220 begin
221 if (rst_i == `TRUE)
222 begin
223 ie <= `FALSE;
224 eie <= `FALSE;
225 `ifdef CFG_DEBUG_ENABLED
226 bie <= `FALSE;
227 `endif
228 im <= {interrupts{1'b0}};
229 ip <= {interrupts{1'b0}};
230 end
231 else
232 begin
233 // Set IP bit when interrupt line is asserted
234 ip <= asserted;
235 `ifdef CFG_DEBUG_ENABLED
236 if (non_debug_exception == `TRUE)
237 begin
238 // Save and then clear interrupt enable
239 eie <= ie;
240 ie <= `FALSE;
241 end
242 else if (debug_exception == `TRUE)
243 begin
244 // Save and then clear interrupt enable
245 bie <= ie;
246 ie <= `FALSE;
247 end
248 `else
249 if (exception == `TRUE)
250 begin
251 // Save and then clear interrupt enable
252 eie <= ie;
253 ie <= `FALSE;
254 end
255 `endif
256 else if (stall_x == `FALSE)
257 begin
258 if (eret_q_x == `TRUE)
259 // Restore interrupt enable
260 ie <= eie;
261 `ifdef CFG_DEBUG_ENABLED
262 else if (bret_q_x == `TRUE)
263 // Restore interrupt enable
264 ie <= bie;
265 `endif
266 else if (csr_write_enable == `TRUE)
267 begin
268 // Handle wcsr write
269 if (csr == `LM32_CSR_IE)
270 begin
271 ie <= csr_write_data[0];
272 eie <= csr_write_data[1];
273 `ifdef CFG_DEBUG_ENABLED
274 bie <= csr_write_data[2];
275 `endif
276 end
277 if (csr == `LM32_CSR_IM)
278 im <= csr_write_data[interrupts-1:0];
279 if (csr == `LM32_CSR_IP)
280 ip <= asserted & ~csr_write_data[interrupts-1:0];
281 end
282 end
283 end
284 end
285 end
286 else
287 begin
288 // IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
289 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
290 begin
291 if (rst_i == `TRUE)
292 begin
293 ie <= `FALSE;
294 eie <= `FALSE;
295 `ifdef CFG_DEBUG_ENABLED
296 bie <= `FALSE;
297 `endif
298 ip <= {interrupts{1'b0}};
299 end
300 else
301 begin
302 // Set IP bit when interrupt line is asserted
303 ip <= asserted;
304 `ifdef CFG_DEBUG_ENABLED
305 if (non_debug_exception == `TRUE)
306 begin
307 // Save and then clear interrupt enable
308 eie <= ie;
309 ie <= `FALSE;
310 end
311 else if (debug_exception == `TRUE)
312 begin
313 // Save and then clear interrupt enable
314 bie <= ie;
315 ie <= `FALSE;
316 end
317 `else
318 if (exception == `TRUE)
319 begin
320 // Save and then clear interrupt enable
321 eie <= ie;
322 ie <= `FALSE;
323 end
324 `endif
325 else if (stall_x == `FALSE)
326 begin
327 if (eret_q_x == `TRUE)
328 // Restore interrupt enable
329 ie <= eie;
330 `ifdef CFG_DEBUG_ENABLED
331 else if (bret_q_x == `TRUE)
332 // Restore interrupt enable
333 ie <= bie;
334 `endif
335 else if (csr_write_enable == `TRUE)
336 begin
337 // Handle wcsr write
338 if (csr == `LM32_CSR_IE)
339 begin
340 ie <= csr_write_data[0];
341 eie <= csr_write_data[1];
342 `ifdef CFG_DEBUG_ENABLED
343 bie <= csr_write_data[2];
344 `endif
345 end
346 if (csr == `LM32_CSR_IP)
347 ip <= asserted & ~csr_write_data[interrupts-1:0];
348 end
349 end
350 end
351 end
352 end
353 endgenerate
355 endmodule