Sat, 06 Aug 2011 01:32:07 +0100
Merge LM32 v3.8 into local mainline
Changes in this release:
FEATURE: Support for dynamically switching EBA to DEBA via a GPIO
BUGFIX: EA now reports instruction which caused the data abort, rather than the instruction following it
STYLE: Update comments to refer to latest Lattice license
1 // ==================================================================
2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
3 // ------------------------------------------------------------------
4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
5 // ALL RIGHTS RESERVED
6 // ------------------------------------------------------------------
7 //
8 // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
9 //
10 // Permission:
11 //
12 // Lattice Semiconductor grants permission to use this code
13 // pursuant to the terms of the Lattice Semiconductor Corporation
14 // Open Source License Agreement.
15 //
16 // Disclaimer:
17 //
18 // Lattice Semiconductor provides no warranty regarding the use or
19 // functionality of this code. It is the user's responsibility to
20 // verify the user’s design for consistency and functionality through
21 // the use of formal verification methods.
22 //
23 // --------------------------------------------------------------------
24 //
25 // Lattice Semiconductor Corporation
26 // 5555 NE Moore Court
27 // Hillsboro, OR 97214
28 // U.S.A
29 //
30 // TEL: 1-800-Lattice (USA and Canada)
31 // 503-286-8001 (other locations)
32 //
33 // web: http://www.latticesemi.com/
34 // email: techsupport@latticesemi.com
35 //
36 // --------------------------------------------------------------------
37 // FILE DETAILS
38 // Project : LatticeMico32
39 // File : lm32_include.v
40 // Title : CPU global macros
41 // Version : 6.1.17
42 // : Initial Release
43 // Version : 7.0SP2, 3.0
44 // : No Change
45 // Version : 3.1
46 // : No Change
47 // Version : 3.2
48 // : No Change
49 // Version : 3.3
50 // : Support for extended configuration register
51 // =============================================================================
53 `ifdef LM32_INCLUDE_V
54 `else
55 `define LM32_INCLUDE_V
57 //
58 // Common configuration options
59 //
61 `define CFG_EBA_RESET 32'h00000000
62 `define CFG_DEBA_RESET 32'h10000000
64 `define CFG_PL_MULTIPLY_ENABLED
65 `define CFG_PL_BARREL_SHIFT_ENABLED
66 `define CFG_SIGN_EXTEND_ENABLED
67 `define CFG_MC_DIVIDE_ENABLED
68 `define CFG_EBR_POSEDGE_REGISTER_FILE
70 // [found by Milkymist dev'rs]
71 // Bug in Xst:
72 // CFG_ICACHE_ASSOCIATIVITY=2 => works in most cases (random crash on complex software)
73 // CFG_ICACHE_ASSOCIATIVITY=1 => disaster, CPU will not work at all
74 // Works 100% OK with expensive synthesizers.
75 `define CFG_ICACHE_ENABLED
76 `define CFG_ICACHE_ASSOCIATIVITY 1
77 `define CFG_ICACHE_SETS 256
78 `define CFG_ICACHE_BYTES_PER_LINE 16
79 `define CFG_ICACHE_BASE_ADDRESS 32'h0
80 `define CFG_ICACHE_LIMIT 32'h7FFF_FFFF
82 `define CFG_DCACHE_ENABLED
83 `define CFG_DCACHE_ASSOCIATIVITY 1
84 `define CFG_DCACHE_SETS 256
85 `define CFG_DCACHE_BYTES_PER_LINE 16
86 `define CFG_DCACHE_BASE_ADDRESS 32'h0
87 `define CFG_DCACHE_LIMIT 32'h0FFF_FFFF
89 // Enable Debugging
90 //`define CFG_JTAG_ENABLED
91 //`define CFG_JTAG_UART_ENABLED
92 //`define CFG_DEBUG_ENABLED
93 //`define CFG_HW_DEBUG_ENABLED
94 //`define CFG_ROM_DEBUG_ENABLED
95 //`define CFG_BREAKPOINTS 32'h0
96 //`define CFG_WATCHPOINTS 32'h0
98 //
99 // End of common configuration options
100 //
102 `ifdef TRUE
103 `else
104 `define TRUE 1'b1
105 `define FALSE 1'b0
106 `define TRUE_N 1'b0
107 `define FALSE_N 1'b1
108 `endif
110 // Wishbone configuration
111 `define CFG_IWB_ENABLED
112 `define CFG_DWB_ENABLED
114 // Data-path width
115 `define LM32_WORD_WIDTH 32
116 `define LM32_WORD_RNG (`LM32_WORD_WIDTH-1):0
117 `define LM32_SHIFT_WIDTH 5
118 `define LM32_SHIFT_RNG (`LM32_SHIFT_WIDTH-1):0
119 `define LM32_BYTE_SELECT_WIDTH 4
120 `define LM32_BYTE_SELECT_RNG (`LM32_BYTE_SELECT_WIDTH-1):0
122 // Register file size
123 `define LM32_REGISTERS 32
124 `define LM32_REG_IDX_WIDTH 5
125 `define LM32_REG_IDX_RNG (`LM32_REG_IDX_WIDTH-1):0
127 // Standard register numbers
128 `define LM32_RA_REG `LM32_REG_IDX_WIDTH'd29
129 `define LM32_EA_REG `LM32_REG_IDX_WIDTH'd30
130 `define LM32_BA_REG `LM32_REG_IDX_WIDTH'd31
132 // Range of Program Counter. Two LSBs are always 0.
133 // `ifdef CFG_ICACHE_ENABLED
134 // `define LM32_PC_WIDTH (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2)
135 // `else
136 // `ifdef CFG_IWB_ENABLED
137 `define LM32_PC_WIDTH (`LM32_WORD_WIDTH-2)
138 // `else
139 // `define LM32_PC_WIDTH `LM32_IROM_ADDRESS_WIDTH
140 // `endif
141 // `endif
142 `define LM32_PC_RNG (`LM32_PC_WIDTH+2-1):2
144 // Range of an instruction
145 `define LM32_INSTRUCTION_WIDTH 32
146 `define LM32_INSTRUCTION_RNG (`LM32_INSTRUCTION_WIDTH-1):0
148 // Adder operation
149 `define LM32_ADDER_OP_ADD 1'b0
150 `define LM32_ADDER_OP_SUBTRACT 1'b1
152 // Shift direction
153 `define LM32_SHIFT_OP_RIGHT 1'b0
154 `define LM32_SHIFT_OP_LEFT 1'b1
156 // Bus errors
157 //`define CFG_BUS_ERRORS_ENABLED
159 // Derive macro that indicates whether we have single-stepping or not
160 `ifdef CFG_ROM_DEBUG_ENABLED
161 `define LM32_SINGLE_STEP_ENABLED
162 `else
163 `ifdef CFG_HW_DEBUG_ENABLED
164 `define LM32_SINGLE_STEP_ENABLED
165 `endif
166 `endif
168 // Derive macro that indicates whether JTAG interface is required
169 `ifdef CFG_JTAG_UART_ENABLED
170 `define LM32_JTAG_ENABLED
171 `else
172 `ifdef CFG_DEBUG_ENABLED
173 `define LM32_JTAG_ENABLED
174 `else
175 `endif
176 `endif
178 // Derive macro that indicates whether we have a barrel-shifter or not
179 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
180 `define LM32_BARREL_SHIFT_ENABLED
181 `else // CFG_PL_BARREL_SHIFT_ENABLED
182 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
183 `define LM32_BARREL_SHIFT_ENABLED
184 `else
185 `define LM32_NO_BARREL_SHIFT
186 `endif
187 `endif // CFG_PL_BARREL_SHIFT_ENABLED
189 // Derive macro that indicates whether we have a multiplier or not
190 `ifdef CFG_PL_MULTIPLY_ENABLED
191 `define LM32_MULTIPLY_ENABLED
192 `else
193 `ifdef CFG_MC_MULTIPLY_ENABLED
194 `define LM32_MULTIPLY_ENABLED
195 `endif
196 `endif
198 // Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
199 `ifdef CFG_MC_DIVIDE_ENABLED
200 `define LM32_MC_ARITHMETIC_ENABLED
201 `endif
202 `ifdef CFG_MC_MULTIPLY_ENABLED
203 `define LM32_MC_ARITHMETIC_ENABLED
204 `endif
205 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
206 `define LM32_MC_ARITHMETIC_ENABLED
207 `endif
209 // Derive macro that indicates if we are using an EBR register file
210 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
211 `define LM32_EBR_REGISTER_FILE
212 `endif
213 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
214 `define LM32_EBR_REGISTER_FILE
215 `endif
217 // Revision number
218 `define LM32_REVISION 6'h02
220 // Logical operations - Function encoded directly in instruction
221 `define LM32_LOGIC_OP_RNG 3:0
223 // Conditions for conditional branches
224 `define LM32_CONDITION_WIDTH 3
225 `define LM32_CONDITION_RNG (`LM32_CONDITION_WIDTH-1):0
226 `define LM32_CONDITION_E 3'b001
227 `define LM32_CONDITION_G 3'b010
228 `define LM32_CONDITION_GE 3'b011
229 `define LM32_CONDITION_GEU 3'b100
230 `define LM32_CONDITION_GU 3'b101
231 `define LM32_CONDITION_NE 3'b111
232 `define LM32_CONDITION_U1 3'b000
233 `define LM32_CONDITION_U2 3'b110
235 // Size of load or store instruction - Encoding corresponds to opcode
236 `define LM32_SIZE_WIDTH 2
237 `define LM32_SIZE_RNG 1:0
238 `define LM32_SIZE_BYTE 2'b00
239 `define LM32_SIZE_HWORD 2'b11
240 `define LM32_SIZE_WORD 2'b10
241 `define LM32_ADDRESS_LSBS_WIDTH 2
243 // Width and range of a CSR index
244 `ifdef CFG_DEBUG_ENABLED
245 `define LM32_CSR_WIDTH 5
246 `define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
247 `else
248 `ifdef CFG_JTAG_ENABLED
249 `define LM32_CSR_WIDTH 4
250 `define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
251 `else
252 `define LM32_CSR_WIDTH 3
253 `define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
254 `endif
255 `endif
257 // CSR indices
258 `define LM32_CSR_IE `LM32_CSR_WIDTH'h0
259 `define LM32_CSR_IM `LM32_CSR_WIDTH'h1
260 `define LM32_CSR_IP `LM32_CSR_WIDTH'h2
261 `define LM32_CSR_ICC `LM32_CSR_WIDTH'h3
262 `define LM32_CSR_DCC `LM32_CSR_WIDTH'h4
263 `define LM32_CSR_CC `LM32_CSR_WIDTH'h5
264 `define LM32_CSR_CFG `LM32_CSR_WIDTH'h6
265 `define LM32_CSR_EBA `LM32_CSR_WIDTH'h7
266 `ifdef CFG_DEBUG_ENABLED
267 `define LM32_CSR_DC `LM32_CSR_WIDTH'h8
268 `define LM32_CSR_DEBA `LM32_CSR_WIDTH'h9
269 `endif
270 `define LM32_CSR_CFG2 `LM32_CSR_WIDTH'ha
271 `ifdef CFG_JTAG_ENABLED
272 `define LM32_CSR_JTX `LM32_CSR_WIDTH'he
273 `define LM32_CSR_JRX `LM32_CSR_WIDTH'hf
274 `endif
275 `ifdef CFG_DEBUG_ENABLED
276 `define LM32_CSR_BP0 `LM32_CSR_WIDTH'h10
277 `define LM32_CSR_BP1 `LM32_CSR_WIDTH'h11
278 `define LM32_CSR_BP2 `LM32_CSR_WIDTH'h12
279 `define LM32_CSR_BP3 `LM32_CSR_WIDTH'h13
280 `define LM32_CSR_WP0 `LM32_CSR_WIDTH'h18
281 `define LM32_CSR_WP1 `LM32_CSR_WIDTH'h19
282 `define LM32_CSR_WP2 `LM32_CSR_WIDTH'h1a
283 `define LM32_CSR_WP3 `LM32_CSR_WIDTH'h1b
284 `endif
286 // Values for WPC CSR
287 `define LM32_WPC_C_RNG 1:0
288 `define LM32_WPC_C_DISABLED 2'b00
289 `define LM32_WPC_C_READ 2'b01
290 `define LM32_WPC_C_WRITE 2'b10
291 `define LM32_WPC_C_READ_WRITE 2'b11
293 // Exception IDs
294 `define LM32_EID_WIDTH 3
295 `define LM32_EID_RNG (`LM32_EID_WIDTH-1):0
296 `define LM32_EID_RESET 3'h0
297 `define LM32_EID_BREAKPOINT 3'd1
298 `define LM32_EID_INST_BUS_ERROR 3'h2
299 `define LM32_EID_WATCHPOINT 3'd3
300 `define LM32_EID_DATA_BUS_ERROR 3'h4
301 `define LM32_EID_DIVIDE_BY_ZERO 3'h5
302 `define LM32_EID_INTERRUPT 3'h6
303 `define LM32_EID_SCALL 3'h7
305 // Pipeline result selection mux controls
307 `define LM32_D_RESULT_SEL_0_RNG 0:0
308 `define LM32_D_RESULT_SEL_0_REG_0 1'b0
309 `define LM32_D_RESULT_SEL_0_NEXT_PC 1'b1
311 `define LM32_D_RESULT_SEL_1_RNG 1:0
312 `define LM32_D_RESULT_SEL_1_ZERO 2'b00
313 `define LM32_D_RESULT_SEL_1_REG_1 2'b01
314 `define LM32_D_RESULT_SEL_1_IMMEDIATE 2'b10
316 `define LM32_USER_OPCODE_WIDTH 11
317 `define LM32_USER_OPCODE_RNG (`LM32_USER_OPCODE_WIDTH-1):0
319 // Derive a macro to indicate if either of the caches are implemented
320 `ifdef CFG_ICACHE_ENABLED
321 `define LM32_CACHE_ENABLED
322 `else
323 `ifdef CFG_DCACHE_ENABLED
324 `define LM32_CACHE_ENABLED
325 `endif
326 `endif
328 /////////////////////////////////////////////////////
329 // Interrupts
330 /////////////////////////////////////////////////////
332 // Always enable interrupts
333 `define CFG_INTERRUPTS_ENABLED
335 // Currently this is fixed to 32 and should not be changed
336 `define CFG_INTERRUPTS 32
337 `define LM32_INTERRUPT_WIDTH `CFG_INTERRUPTS
338 `define LM32_INTERRUPT_RNG (`LM32_INTERRUPT_WIDTH-1):0
340 /////////////////////////////////////////////////////
341 // General
342 /////////////////////////////////////////////////////
344 // Sub-word range types
345 `define LM32_BYTE_WIDTH 8
346 `define LM32_BYTE_RNG 7:0
347 `define LM32_HWORD_WIDTH 16
348 `define LM32_HWORD_RNG 15:0
350 // Word sub-byte indicies
351 `define LM32_BYTE_0_RNG 7:0
352 `define LM32_BYTE_1_RNG 15:8
353 `define LM32_BYTE_2_RNG 23:16
354 `define LM32_BYTE_3_RNG 31:24
356 // Word sub-halfword indices
357 `define LM32_HWORD_0_RNG 15:0
358 `define LM32_HWORD_1_RNG 31:16
360 // Use an asynchronous reset
361 // To use a synchronous reset, define this macro as nothing
362 //`define CFG_RESET_SENSITIVITY or posedge rst_i
363 `define CFG_RESET_SENSITIVITY
365 // Whether to include context registers for debug exceptions
366 // in addition to standard exception handling registers
367 `define CFG_DEBUG_EXCEPTIONS_ENABLED
369 // Wishbone defines
370 // Refer to Wishbone System-on-Chip Interconnection Architecture
371 // These should probably be moved to a Wishbone common file
373 // Wishbone cycle types
374 `define LM32_CTYPE_WIDTH 3
375 `define LM32_CTYPE_RNG (`LM32_CTYPE_WIDTH-1):0
376 `define LM32_CTYPE_CLASSIC 3'b000
377 `define LM32_CTYPE_CONSTANT 3'b001
378 `define LM32_CTYPE_INCREMENTING 3'b010
379 `define LM32_CTYPE_END 3'b111
381 // Wishbone burst types
382 `define LM32_BTYPE_WIDTH 2
383 `define LM32_BTYPE_RNG (`LM32_BTYPE_WIDTH-1):0
384 `define LM32_BTYPE_LINEAR 2'b00
385 `define LM32_BTYPE_4_BEAT 2'b01
386 `define LM32_BTYPE_8_BEAT 2'b10
387 `define LM32_BTYPE_16_BEAT 2'b11
389 `endif