IPCores/lm32_cpu / changelog

reduce size of caches to fit in DE1 FPGA

• Mon, 05 Apr 2010 21:00:31 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Mon, 05 Apr 2010 21:00:31 +0100] rev 6
• reduce size of caches to fit in DE1 FPGA
  
  The default cache size makes the Icache and Dcache "just a bit" too big to
  fit in the EP2C20 FPGA on the DE1 board. This commit reduces the Icache and
  Dcache sizes to the defaults shown in the LatticeMico32 Processor Reference
  Manual (pages 36 and 37).

disable caches, they use too much RAM :(

• Mon, 05 Apr 2010 20:25:37 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Mon, 05 Apr 2010 20:25:37 +0100] rev 5
• disable caches, they use too much RAM :(

add better comment re Xilinx Xst cache issues

• Mon, 05 Apr 2010 20:23:04 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Mon, 05 Apr 2010 20:23:04 +0100] rev 4
• add better comment re Xilinx Xst cache issues

remove more Lattice-specific fluff

• Sun, 04 Apr 2010 22:05:07 +0100
• by Philip Pemberton <philpem@philpem.me.uk> [Sun, 04 Apr 2010 22:05:07 +0100] rev 3
• remove more Lattice-specific fluff
  
  Code now synthesizes properly on Altera Quartus 9.0 build 235